diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/compressed/head-omap.S linux-2.4.19/arch/arm/boot/compressed/head-omap.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/compressed/head-omap.S	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/boot/compressed/head-omap.S	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,48 @@
+/* 
+ * linux/arch/arm/boot/compressed/head-omap.S
+ * 
+ * Copyright (C) 1999 Nicolas Pitre <nico@cam.org>
+ * 
+ * OMAP specific tweaks.  This is merged into head.S by the linker.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/mach-types.h>
+
+		.section        ".start", "ax"
+
+__OMAP_start:
+
+		@ Preserve r8/r7 i.e. kernel entry values
+
+#if	defined(CONFIG_OMAP_INNOVATOR)
+		mov	r7, #MACH_TYPE_INNOVATOR
+		mov	r8, #0
+#elif	defined(CONFIG_OMAP_PERSEUS)
+		mov	r7, #MACH_TYPE_TI925
+		mov	r8, #0
+#elif	defined(CONFIG_ARCH_OMAP)
+		mov	r7, #MACH_TYPE_TI925
+		mov	r8, #0
+#endif
+
+		@ Data cache might be active.
+		@ Be sure to flush kernel binary out of the cache,
+		@ whatever state it is, before it is turned off.
+		@ This is done by fetching through currently executed
+		@ memory to be sure we hit the same cache.
+		bic	r2, pc, #0x1f
+		add	r3, r2, #0x4000		@ 16 kb is quite enough...
+1:		ldr	r0, [r2], #32
+		teq	r2, r3
+		bne	1b
+		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+		mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+		@ disabling MMU and caches
+		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+		bic	r0, r0, #0x0d		@ clear WB, DC, MMU
+		bic	r0, r0, #0x1000		@ clear Icache
+		mcr	p15, 0, r0, c1, c0, 0
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/compressed/Makefile linux-2.4.19/arch/arm/boot/compressed/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/compressed/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/boot/compressed/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -63,6 +63,10 @@
 OBJS		+= head-sa1100.o
 endif
 
+ifeq ($(CONFIG_ARCH_OMAP),y)
+OBJS		+= head-omap.o
+endif
+
 ifeq ($(CONFIG_ARCH_SA1100),y)
 OBJS		+= head-sa1100.o
 endif
Binary files ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/Image and linux-2.4.19/arch/arm/boot/Image differ
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/Makefile linux-2.4.19/arch/arm/boot/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/boot/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/boot/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -90,6 +90,20 @@
 INITRD_PHYS	 = 0x00700000
 endif
 
+ifeq ($(CONFIG_ARCH_TI925),y)
+ZRELADDR         = 0x04008000
+endif
+
+ifeq ($(CONFIG_ARCH_OMAP1510),y)
+ZRELADDR         = 0x10008000
+INITRD_PHYS	 = 0x10200000
+endif
+
+ifeq ($(CONFIG_ARCH_OMAP710),y)
+ZRELADDR         = 0x10008000
+INITRD_PHYS	 = 0x10200000
+endif
+
 ifeq ($(CONFIG_ARCH_OMAHA),y)
 ZTEXTADDR	 = 0x0c008000
 PARAMS_PHYS	 = 0x0C000100
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/config.in linux-2.4.19/arch/arm/config.in
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/config.in	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/config.in	2003-01-15 09:53:42.000000000 +0200
@@ -48,6 +48,7 @@
 	 RiscPC			CONFIG_ARCH_RPC \
 	 RiscStation		CONFIG_ARCH_RISCSTATION \
 	 SA1100-based		CONFIG_ARCH_SA1100 \
+	 TI925/OMAP		CONFIG_ARCH_OMAP \
 	 Shark			CONFIG_ARCH_SHARK" RiscPC
 
 mainmenu_option next_comment
@@ -164,6 +165,53 @@
 fi
 endmenu
 
+if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+   mainmenu_option next_comment
+   comment 'TI OMAP Implementations'
+   dep_bool '  Innovator' CONFIG_OMAP_INNOVATOR $CONFIG_ARCH_OMAP
+   dep_bool '  1510DC P1 EVM' CONFIG_OMAP_1510P1 $CONFIG_ARCH_OMAP
+   dep_bool '  Perseus1 P1 EVM' CONFIG_OMAP_PERSEUS1 $CONFIG_ARCH_OMAP
+   dep_bool '  TI925 EVM' CONFIG_OMAP_TI925 $CONFIG_ARCH_OMAP
+
+   if [ "$CONFIG_OMAP_INNOVATOR" = "y" -o \
+        "$CONFIG_OMAP_1510P1" = "y" ]; then
+      define_bool CONFIG_ARCH_OMAP1510 y
+      define_bool CONFIG_ARCH_OMAP710 n
+      define_bool CONFIG_CLOCK_COUNTS_DOWN y
+   fi
+
+   if [ "$CONFIG_OMAP_PERSEUS1" = "y" ]; then
+      define_bool CONFIG_ARCH_OMAP1510 n
+      define_bool CONFIG_ARCH_OMAP710 y
+   fi
+
+   if [ "$CONFIG_OMAP_TI925" = "y" ]; then
+      define_bool CONFIG_ARCH_TI925 y
+   fi
+
+   comment 'OMAP Feature Selections'
+   bool 'OMAP1510 Power Management' CONFIG_OMAP1510_PM
+   dep_bool 'Disable compiler optimizations (EXPERIMENTAL)' CONFIG_NO_OPTIMIZE $CONFIG_ARCH_OMAP
+   dep_bool ' OMAP ARM 168 MHz CPU' CONFIG_OMAP_ARM_168MHZ $CONFIG_ARCH_OMAP $CONFIG_ARCH_OMAP1510
+   dep_bool ' OMAP ARM 120 MHz CPU' CONFIG_OMAP_ARM_120MHZ $CONFIG_ARCH_OMAP
+   dep_bool ' OMAP ARM 60 MHz CPU' CONFIG_OMAP_ARM_60MHZ $CONFIG_ARCH_OMAP
+   dep_bool ' OMAP ARM 30 MHz CPU' CONFIG_OMAP_ARM_30MHZ $CONFIG_ARCH_OMAP
+   if [ "$CONFIG_OMAP_ARM_120MHZ" = "n" -a \
+        "$CONFIG_OMAP_ARM_60MHZ"  = "n" -a \
+        "$CONFIG_OMAP_ARM_168MHZ"  = "n" -a \
+        "$CONFIG_OMAP_ARM_30MHZ"  = "n" ]; then
+      define_bool CONFIG_OMAP_ARM_60MHZ y
+   fi
+
+   dep_tristate 'OMAP1510 PWT driver' CONFIG_OMAP1510_PWT $CONFIG_ARCH_OMAP1510
+   tristate 'OMAP Timer driver' CONFIG_OMAP_TIMER
+   if [ "$CONFIG_OMAP_TIMER" != "n" ]; then
+      tristate 'OMAP Timer /proc driver' CONFIG_OMAP_TIMER_PROC
+   fi
+
+   endmenu
+fi
+
 # Definitions to make life easier
 if [ "$CONFIG_ARCH_ARCA5K" = "y" -o \
      "$CONFIG_ARCH_RPC" = "y" ]; then
@@ -294,6 +342,27 @@
    define_bool CONFIG_PLD n
 fi
 
+# ARM925T
+if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+    define_bool CONFIG_CPU_ARM925T y
+    bool '  ARM925 CPU idle' CONFIG_CPU_ARM925_CPU_IDLE
+    bool '  ARM925 I-Cache on' CONFIG_CPU_ARM925_I_CACHE_ON
+    if [ "$CONFIG_CPU_ARM925_I_CACHE_ON" = "y" ] ; then
+       bool '  ARM925 non streaming mode on' CONFIG_CPU_ARM925_NON_STREAMING_ON 
+    fi
+    bool '  ARM925 D-Cache on' CONFIG_CPU_ARM925_D_CACHE_ON
+#    if [ "$CONFIG_CPU_ARM925_D_CACHE_ON" = "y" ] ; then
+       bool '  Force write through caches on ARM925T' CONFIG_CPU_ARM925_WRITETHROUGH
+       # bool '  ARM925 D-Cache fixups for early silicon' CONFIG_CPU_ARM925_CACHE_PROTECT
+#       if [ "$CONFIG_CPU_ARM925_WRITETHROUGH" != "y" ] ; then
+          bool '  ARM925 Writebuffer on' CONFIG_CPU_ARM925_WRITEBUFFER_ON
+          bool '  ARM925 D-Cache VIVT algorithm' CONFIG_CPU_ARM925_VIVT
+          # Errata says can't have copyback cache and transparent?:
+          bool '  ARM925 transparent on' CONFIG_CPU_ARM925_TRANSPARENT_ON 
+#       fi
+#    fi
+fi
+
 # ARM926T
 if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
    bool 'Support ARM926T processor' CONFIG_CPU_ARM926T
@@ -351,6 +420,7 @@
      "$CONFIG_ARCH_INTEGRATOR" = "y" -o "$CONFIG_ARCH_SA1100"   = "y" -o \
      "$CONFIG_ARCH_L7200"      = "y" -o "$CONFIG_ARCH_ANAKIN"	= "y" -o \
      "$CONFIG_ARCH_CAMELOT"    = "y" -o "$CONFIG_ARCH_MX1ADS"   = "y" -o \
+     "$CONFIG_ARCH_OMAP"       = "y" -o \
      "$CONFIG_ARCH_OMAHA"      = "y" ]; then
    define_bool CONFIG_CPU_32v4 y
 else
@@ -483,6 +553,7 @@
      "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
      "$CONFIG_ARCH_CDB89712" = "y" -o   \
      "$CONFIG_ARCH_P720T" = "y" -o	\
+     "$CONFIG_ARCH_OMAP" = "y" -o       \
      "$CONFIG_ARCH_OMAHA" = "y" ]; then
    bool 'Timer and CPU usage LEDs' CONFIG_LEDS
    if [ "$CONFIG_LEDS" = "y" ]; then
@@ -611,6 +682,7 @@
    # Select the keyboard type for this architecture.
    if [ "$CONFIG_FOOTBRIDGE_HOST" = "y" -o \
         "$CONFIG_ARCH_CLPS7500" = "y" -o   \
+        "$CONFIG_ARCH_OMAP" = "y" -o \
         "$CONFIG_ARCH_SHARK" = "y" ]; then
       define_bool CONFIG_PC_KEYB y
    fi
@@ -630,7 +702,8 @@
         "$CONFIG_ARCH_TBOX" = "y" -o       \
         "$CONFIG_ARCH_CLPS7500" = "y" -o   \
         "$CONFIG_ARCH_P720T" = "y" -o      \
-        "$CONFIG_ARCH_ANAKIN" = "y" -o      \
+        "$CONFIG_ARCH_ANAKIN" = "y" -o     \
+        "$CONFIG_ARCH_OMAP" = "y" -o       \
 	"$CONFIG_ARCH_MX1ADS" = "y" ]; then
       define_bool CONFIG_PC_KEYMAP y
    fi
@@ -647,6 +720,7 @@
      "$CONFIG_ARCH_TBOX" = "y" -o \
      "$CONFIG_ARCH_SHARK" = "y" -o \
      "$CONFIG_ARCH_SA1100" = "y" -o \
+     "$CONFIG_ARCH_OMAP" = "y" -o \
      "$CONFIG_PCI" = "y" ]; then
    mainmenu_option next_comment
    comment 'Sound'
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/def-configs/evm linux-2.4.19/arch/arm/def-configs/evm
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/def-configs/evm	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/def-configs/evm	2003-01-15 12:32:09.000000000 +0200
@@ -0,0 +1,717 @@
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ADIFCC is not set
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP1200 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_MX1ADS is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CEP is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_FRODO is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_BADGE4 is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_PT_SYSTEM3 is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+
+#
+# Intel PXA250/210 Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_ARCH_PXA_CERF is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_FORTUNET is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+
+#
+# TI OMAP Implementations
+#
+# CONFIG_OMAP_INNOVATOR is not set
+CONFIG_OMAP_1510P1=y
+# CONFIG_OMAP_PERSEUS1 is not set
+# CONFIG_OMAP_TI925 is not set
+CONFIG_ARCH_OMAP1510=y
+# CONFIG_ARCH_OMAP710 is not set
+CONFIG_CLOCK_COUNTS_DOWN=y
+# CONFIG_OMAP1510_PM is not set
+# CONFIG_NO_OPTIMIZE is not set
+# CONFIG_OMAP_ARM_168MHZ is not set
+CONFIG_OMAP_ARM_120MHZ=y
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+# CONFIG_OMAP1510_PWT is not set
+CONFIG_OMAP_TIMER=y
+CONFIG_OMAP_TIMER_PROC=y
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_PLD is not set
+CONFIG_CPU_ARM925T=y
+CONFIG_CPU_ARM925_CPU_IDLE=y
+CONFIG_CPU_ARM925_I_CACHE_ON=y
+CONFIG_CPU_ARM925_NON_STREAMING_ON=y
+CONFIG_CPU_ARM925_D_CACHE_ON=y
+# CONFIG_CPU_ARM925_WRITETHROUGH is not set
+# CONFIG_CPU_ARM925_WRITEBUFFER_ON is not set
+CONFIG_CPU_ARM925_VIVT=y
+# CONFIG_CPU_ARM925_TRANSPARENT_ON is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+# CONFIG_CPU_SA1100 is not set
+# CONFIG_XSCALE_BDI2000 is not set
+# CONFIG_ARM_THUMB is not set
+# CONFIG_DISCONTIGMEM is not set
+# CONFIG_EMBEDDED_OOM_KILLER is not set
+# CONFIG_RTSCHED is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=10C08000
+CONFIG_ZBOOT_ROM_BSS=10200000
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_MULTITHREADED_CORES is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_PM=y
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="mem=32M root=/dev/ram0 rw init=/bin/sh console=tty0 console=ttyS0,57600"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ILATENCY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+# CONFIG_NETDEVICES is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_OMAP710_KEYPAD is not set
+# CONFIG_OMAP1510_KEYPAD is not set
+# CONFIG_OMAP1510_TOUCHSCREEN is not set
+# CONFIG_OMAP1510_HID is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_OMAP1510_HWERROR is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_BITLP is not set
+# CONFIG_I2C_BITELV is not set
+# CONFIG_I2C_BITVELLE is not set
+# CONFIG_I2C_ALGOPCF is not set
+CONFIG_I2C_BIT_OMAP_GPIO=y
+# CONFIG_I2C_MAINBOARD is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PROC=y
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_BIT_OMAP_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Hardware sensors support
+#
+CONFIG_SENSORS=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1024 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_MAXILIFE is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_MTP008 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+CONFIG_SENSORS_OTHER=y
+# CONFIG_SENSORS_BT869 is not set
+# CONFIG_SENSORS_DDCMON is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_MATORB is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_21285_WATCHDOG is not set
+# CONFIG_977_WATCHDOG is not set
+# CONFIG_SA1100_WATCHDOG is not set
+# CONFIG_PXA_WATCHDOG is not set
+# CONFIG_OMAP1510_WATCHDOG is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_VR41XX_WDT is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_OMAP710_RTC is not set
+# CONFIG_X1226_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYB=y
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_SA1100 is not set
+# CONFIG_FB_PXA is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_SDRAM is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MQ200 is not set
+# CONFIG_FB_IT8181 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+# CONFIG_MCP_UCB1400_TS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_OMAP1510 is not set
+# CONFIG_USB_NON_PCI_OHCI is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Omap1510 USB Client support
+#
+# CONFIG_OMAP1510_USB_CLIENT is not set
+# CONFIG_OMAP1510_USB_CLIENT_TEST is not set
+# CONFIG_OMAP1510_USB_CLIENT_MASS_STORAGE is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel tracing
+#
+# CONFIG_TRACE is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
+# CONFIG_KGDB is not set
+# CONFIG_KGDB_SERIAL is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_KGDB_SYSRQ is not set
+# CONFIG_KGDB_MORE is not set
+# CONFIG_DEBUG_OMAP710_REGS is not set
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/def-configs/innovator linux-2.4.19/arch/arm/def-configs/innovator
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/def-configs/innovator	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/def-configs/innovator	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,1097 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_ADIFCC is not set
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP1200 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_MX1ADS is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CEP is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_FRODO is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_BADGE4 is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_PT_SYSTEM3 is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+
+#
+# Intel PXA250/210 Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_ARCH_PXA_CERF is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_FORTUNET is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_OMAP_INNOVATOR=y
+# CONFIG_OMAP_1510P1 is not set
+# CONFIG_OMAP_PERSEUS1 is not set
+# CONFIG_OMAP_TI925 is not set
+CONFIG_ARCH_OMAP1510=y
+# CONFIG_ARCH_OMAP710 is not set
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP1510_PM=y
+# CONFIG_NO_OPTIMIZE is not set
+CONFIG_OMAP_ARM_168MHZ=y
+# CONFIG_OMAP_ARM_120MHZ is not set
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+CONFIG_OMAP1510_PWT=m
+CONFIG_OMAP_TIMER=m
+CONFIG_OMAP_TIMER_PROC=m
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_PLD is not set
+CONFIG_CPU_ARM925T=y
+CONFIG_CPU_ARM925_CPU_IDLE=y
+CONFIG_CPU_ARM925_I_CACHE_ON=y
+CONFIG_CPU_ARM925_NON_STREAMING_ON=y
+CONFIG_CPU_ARM925_D_CACHE_ON=y
+# CONFIG_CPU_ARM925_WRITETHROUGH is not set
+# CONFIG_CPU_ARM925_WRITEBUFFER_ON is not set
+CONFIG_CPU_ARM925_VIVT=y
+# CONFIG_CPU_ARM925_TRANSPARENT_ON is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+# CONFIG_CPU_SA1100 is not set
+# CONFIG_XSCALE_BDI2000 is not set
+# CONFIG_ARM_THUMB is not set
+# CONFIG_DISCONTIGMEM is not set
+# CONFIG_EMBEDDED_OOM_KILLER is not set
+# CONFIG_RTSCHED is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+CONFIG_ZBOOT_ROM=y
+CONFIG_ZBOOT_ROM_TEXT=10C08000
+CONFIG_ZBOOT_ROM_BSS=10200000
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=m
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_ELF=y
+# CONFIG_MULTITHREADED_CORES is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_PM=y
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_PREEMPT is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+CONFIG_MTD_CFI_B2=y
+# CONFIG_MTD_CFI_B4 is not set
+# CONFIG_MTD_CFI_B8 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+# CONFIG_MTD_SA1100 is not set
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_IQ80321 is not set
+# CONFIG_MTD_EPXA10DB is not set
+# CONFIG_MTD_LUBBOCK is not set
+# CONFIG_MTD_BRH is not set
+CONFIG_MTD_OMAP=y
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_ARM_AM79C961A is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+CONFIG_NET_VENDOR_SMC=y
+# CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
+# CONFIG_ULTRA is not set
+# CONFIG_ULTRA32 is not set
+CONFIG_SMC9194=y
+# CONFIG_SMC91111 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+# CONFIG_HHNET is not set
+# CONFIG_NPNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+CONFIG_PPPOE=m
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_NSC_FIR is not set
+# CONFIG_WINBOND_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=m
+CONFIG_INPUT_KEYBDEV=m
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_OMAP710_KEYPAD is not set
+CONFIG_OMAP1510_KEYPAD=m
+CONFIG_OMAP1510_TOUCHSCREEN=m
+CONFIG_OMAP1510_HID=m
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_OMAP1510_HWERROR=m
+
+#
+# I2C support
+#
+CONFIG_I2C=m
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_BITLP is not set
+# CONFIG_I2C_BITELV is not set
+# CONFIG_I2C_BITVELLE is not set
+# CONFIG_I2C_ALGOPCF is not set
+CONFIG_I2C_BIT_OMAP_GPIO=m
+# CONFIG_I2C_MAINBOARD is not set
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_PROC=m
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_BIT_OMAP_GPIO is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Hardware sensors support
+#
+CONFIG_SENSORS=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1024 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_MAXILIFE is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_MTP008 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+CONFIG_SENSORS_OTHER=y
+# CONFIG_SENSORS_BT869 is not set
+# CONFIG_SENSORS_DDCMON is not set
+CONFIG_SENSORS_EEPROM=m
+# CONFIG_SENSORS_MATORB is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_21285_WATCHDOG is not set
+# CONFIG_977_WATCHDOG is not set
+# CONFIG_SA1100_WATCHDOG is not set
+# CONFIG_PXA_WATCHDOG is not set
+CONFIG_OMAP1510_WATCHDOG=m
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_VR41XX_WDT is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_OMAP710_RTC is not set
+# CONFIG_X1226_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=m
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=m
+CONFIG_JFFS_FS_VERBOSE=0
+# CONFIG_JFFS_PROC_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRAMFS=y
+CONFIG_TMPFS=y
+CONFIG_RAMFS=m
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=m
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+CONFIG_ZLIB_FS_INFLATE=y
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_SMB_NLS=y
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYB=y
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_SA1100 is not set
+# CONFIG_FB_PXA is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_SDRAM is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MQ200 is not set
+# CONFIG_FB_IT8181 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+CONFIG_FBCON_FONTWIDTH8_ONLY=y
+CONFIG_FBCON_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+CONFIG_FONT_ACORN_8x8=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_OMAP=m
+# CONFIG_DSP_MCBSP1 is not set
+# CONFIG_SOUND_OMAP_UDA1341 is not set
+CONFIG_SOUND_OMAP_AIC23=m
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
+# CONFIG_SOUND_PXA_AC97 is not set
+# CONFIG_SOUND_TVMIXER is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+# CONFIG_MCP_UCB1400_TS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_NON_PCI_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+# CONFIG_USB_HID is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_WACOM is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel tracing
+#
+# CONFIG_TRACE is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
+# CONFIG_KGDB is not set
+# CONFIG_KGDB_SERIAL is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_KGDB_SYSRQ is not set
+# CONFIG_KGDB_MORE is not set
+# CONFIG_DEBUG_OMAP710_REGS is not set
+CONFIG_ZLIB=m
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/debug-armv.S linux-2.4.19/arch/arm/kernel/debug-armv.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/debug-armv.S	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/kernel/debug-armv.S	2003-01-15 09:46:38.000000000 +0200
@@ -411,6 +411,33 @@
 		bne	1001b
 		.endm
 
+#elif	defined(CONFIG_ARCH_OMAP1510)
+
+		.macro	addruart,rx
+		@ REVISIT: MMIO virt:phys is 1:1	
+		mov	\rx, #0xff000000
+
+		orr	\rx, \rx, #0x00fb0000	@ UART1
+		orr	\rx, \rx, #0x00000000
+		.endm
+
+		.macro	senduart,rd,rx
+		strb	\rd, [\rx]
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		ldrb	\rd, [\rx, #(0x5 << 2)]
+		and	\rd, \rd, #0x60
+		teq	\rd, #0x60
+		bne	1002b
+		.endm
+
+		.macro	waituart,rd,rx
+1001:		ldrb	\rd, [\rx, #(0x6 << 2)]
+		tst	\rd, #0x10
+		beq	1001b
+		.endm
+
 #else
 #error Unknown architecture
 #endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/entry-armv.S linux-2.4.19/arch/arm/kernel/entry-armv.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/entry-armv.S	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/kernel/entry-armv.S	2003-01-09 19:49:04.000000000 +0200
@@ -598,6 +598,35 @@
 		.text
 		.endm
 
+#elif defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP710)
+	
+		.macro	disable_fiq
+		.endm
+/* load the itr and look for an interrupt, 
+ * we get the correct irq in irq_fixup 
+ */
+		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+		ldr	\base, =IO_ADDRESS(INTERRUPT_HANDLER_BASE)
+		ldr	\irqnr, [\base, #INTERRUPT_INPUT_REGISTER]
+
+                /*
+                ;; Apparently it's possible for a device to assert a bit in the
+                ;; input register even if the bit is masked out in the mask
+                ;; register. In this case the device did not really cause an 
+                ;; interrupt, and we won't clear the bit because we won't run 
+                ;; the device's ISR. So below we're checking the input register
+                ;; against the mask register.
+                */
+        
+                ldr     \tmp, [\base, #INTERRUPT_MASK_REGISTER]
+                mov     \base,  #0xffffffff
+                bic     \tmp, \base, \tmp
+        
+               	tst	\irqnr, \tmp
+		.endm
+
+		.macro	irq_prio_table
+		.endm
 #else
 #error Unknown architecture
 #endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/head-armv.S linux-2.4.19/arch/arm/kernel/head-armv.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/head-armv.S	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/kernel/head-armv.S	2003-01-15 09:46:59.000000000 +0200
@@ -129,6 +129,15 @@
  * FIXME - No bootloader, so manually set 'r1' with our architecture number.
  */
 		mov	r1, #MACH_TYPE_L7200
+#elif defined(CONFIG_OMAP_INNOVATOR)
+		mov	r1, #MACH_TYPE_INNOVATOR
+#elif defined(CONFIG_OMAP_1510P1)
+		/* FIXME: 1510 should get assigned a new machine id */
+		mov	r1, #MACH_TYPE_INNOVATOR
+#elif defined(CONFIG_OMAP_PERSEUS)
+		mov	r1, #MACH_TYPE_PERSEUS
+#elif defined(CONFIG_ARCH_OMAP)
+		mov	r1, #MACH_TYPE_TI925
 #endif
 
 		mov	r0, #F_BIT | I_BIT | MODE_SVC	@ make sure svc mode
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/irq.c linux-2.4.19/arch/arm/kernel/irq.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/irq.c	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/kernel/irq.c	2003-01-09 19:49:04.000000000 +0200
@@ -413,6 +413,12 @@
 	__backtrace();
 #endif
 out:
+
+#if defined(CONFIG_ARCH_OMAP)
+	/* Mask it if we removed the only service routine (gjm) */
+	if (irq_desc[irq].action == NULL)
+		irq_desc[irq].mask(irq);
+#endif
 	spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/Makefile linux-2.4.19/arch/arm/kernel/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/kernel/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/kernel/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -44,7 +44,8 @@
 no-irq-arch	:= $(CONFIG_ARCH_INTEGRATOR) $(CONFIG_ARCH_CLPS711X) \
 		   $(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \
 		   $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT) \
-		   $(CONFIG_ARCH_MX1ADS) $(CONFIG_ARCH_OMAHA)
+		   $(CONFIG_ARCH_MX1ADS) $(CONFIG_ARCH_OMAHA) \
+		   $(CONFIG_ARCH_OMAP1510)
 
 ifneq ($(findstring y,$(no-irq-arch)),y)
   obj-y		+= irq-arch.o
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/apm.c linux-2.4.19/arch/arm/mach-omap1510/apm.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/apm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/apm.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,514 @@
+/*
+ * bios-less APM driver for ARM Linux 
+ *  Jamey Hicks <jamey@crl.dec.com>
+ *  adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com)
+ *
+ * APM 1.2 Reference:
+ *   Intel Corporation, Microsoft Corporation. Advanced Power Management
+ *   (APM) BIOS Interface Specification, Revision 1.2, February 1996.
+ *
+ * [This document is available from Microsoft at:
+ *    http://www.microsoft.com/hwdev/busbios/amp_12.htm]
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/poll.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <linux/timer.h>
+#include <linux/fcntl.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/proc_fs.h>
+#include <linux/miscdevice.h>
+#include <linux/apm_bios.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pm.h>
+#include <linux/kernel.h>
+#include <linux/smp_lock.h>
+
+#include <asm/system.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_SA1100_H3XXX
+#include <asm/arch/h3600_hal.h>
+#endif
+
+#if defined(CONFIG_APM_DISPLAY_BLANK) && defined(CONFIG_VT)
+extern int (*console_blank_hook)(int);
+#endif
+
+struct apm_bios_info apm_bios_info = {
+        /* this driver simulates APM version 1.2 */
+        version: 0x102,
+        flags: APM_32_BIT_SUPPORT
+};
+
+/*
+ * The apm_bios device is one of the misc char devices.
+ * This is its minor number.
+ */
+#define	APM_MINOR_DEV	134
+
+/*
+ * See Documentation/Config.help for the configuration options.
+ *
+ * Various options can be changed at boot time as follows:
+ * (We allow underscores for compatibility with the modules code)
+ *	apm=on/off			enable/disable APM
+ *	    [no-]debug			log some debugging messages
+ *	    [no-]power[-_]off		power off on shutdown
+ */
+
+/*
+ * Need to poll the APM BIOS every second
+ */
+#define APM_CHECK_TIMEOUT	(HZ)
+
+/*
+ * Ignore suspend events for this amount of time after a resume
+ */
+#define DEFAULT_BOUNCE_INTERVAL		(3 * HZ)
+
+/*
+ * Maximum number of events stored
+ */
+#define APM_MAX_EVENTS		20
+
+/*
+ * The per-file APM data
+ */
+struct apm_user {
+	int		magic;
+	struct apm_user *	next;
+	int		suser: 1;
+	int		suspend_wait: 1;
+	int		suspend_result;
+	int		suspends_pending;
+	int		standbys_pending;
+	int		suspends_read;
+	int		standbys_read;
+	int		event_head;
+	int		event_tail;
+	apm_event_t	events[APM_MAX_EVENTS];
+};
+
+/*
+ * The magic number in apm_user
+ */
+#define APM_BIOS_MAGIC		0x4101
+
+/*
+ * Local variables
+ */
+//static int			suspends_pending;
+//static int			standbys_pending;
+//static int			ignore_normal_resume;
+
+#ifdef CONFIG_APM_RTC_IS_GMT
+#	define	clock_cmos_diff	0
+#	define	got_clock_diff	1
+#else
+//static long			clock_cmos_diff;
+//static int			got_clock_diff;
+#endif
+static int			debug;
+static int			apm_disabled;
+#ifdef CONFIG_SMP
+static int			power_off;
+#else
+static int			power_off = 1;
+#endif
+static int			exit_kapmd;
+static int			kapmd_running;
+
+static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
+static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
+static struct apm_user *	user_list = NULL;
+
+static char			driver_version[] = "1.13";	/* no spaces */
+
+typedef struct lookup_t {
+	int	key;
+	char *	msg;
+} lookup_t;
+
+static const lookup_t error_table[] = {
+/* N/A	{ APM_SUCCESS,		"Operation succeeded" }, */
+	{ APM_DISABLED,		"Power management disabled" },
+	{ APM_CONNECTED,	"Real mode interface already connected" },
+	{ APM_NOT_CONNECTED,	"Interface not connected" },
+	{ APM_16_CONNECTED,	"16 bit interface already connected" },
+/* N/A	{ APM_16_UNSUPPORTED,	"16 bit interface not supported" }, */
+	{ APM_32_CONNECTED,	"32 bit interface already connected" },
+	{ APM_32_UNSUPPORTED,	"32 bit interface not supported" },
+	{ APM_BAD_DEVICE,	"Unrecognized device ID" },
+	{ APM_BAD_PARAM,	"Parameter out of range" },
+	{ APM_NOT_ENGAGED,	"Interface not engaged" },
+	{ APM_BAD_FUNCTION,     "Function not supported" },
+	{ APM_RESUME_DISABLED,	"Resume timer disabled" },
+	{ APM_BAD_STATE,	"Unable to enter requested state" },
+/* N/A	{ APM_NO_EVENTS,	"No events pending" }, */
+	{ APM_NO_ERROR,		"BIOS did not set a return code" },
+	{ APM_NOT_PRESENT,	"No APM present" }
+};
+#define ERROR_COUNT	(sizeof(error_table)/sizeof(lookup_t))
+
+static int apm_get_power_status(u_char *ac_line_status,
+                                u_char *battery_status,
+                                u_char *battery_flag,
+                                u_char *battery_percentage,
+                                u_short *battery_life)
+{
+        //platform_apm_get_power_status(ac_line_status, battery_status, battery_flag, battery_percentage, battery_life);
+	return APM_SUCCESS;
+}
+
+static int queue_empty(struct apm_user *as)
+{
+	return as->event_head == as->event_tail;
+}
+
+static apm_event_t get_queued_event(struct apm_user *as)
+{
+	as->event_tail = (as->event_tail + 1) % APM_MAX_EVENTS;
+	return as->events[as->event_tail];
+}
+
+static int check_apm_user(struct apm_user *as, const char *func)
+{
+	if ((as == NULL) || (as->magic != APM_BIOS_MAGIC)) {
+		printk(KERN_ERR "apm: %s passed bad filp\n", func);
+		return 1;
+	}
+	return 0;
+}
+
+static ssize_t do_read(struct file *fp, char *buf, size_t count, loff_t *ppos)
+{
+	struct apm_user *	as;
+	int			i;
+	apm_event_t		event;
+	DECLARE_WAITQUEUE(wait, current);
+
+	as = fp->private_data;
+	if (check_apm_user(as, "read"))
+		return -EIO;
+	if (count < sizeof(apm_event_t))
+		return -EINVAL;
+	if (queue_empty(as)) {
+		if (fp->f_flags & O_NONBLOCK)
+			return -EAGAIN;
+		add_wait_queue(&apm_waitqueue, &wait);
+                printk("do_read: waiting\n");
+repeat:
+		set_current_state(TASK_INTERRUPTIBLE);
+		if (queue_empty(as) && !signal_pending(current)) {
+			schedule();
+			goto repeat;
+		}
+		set_current_state(TASK_RUNNING);
+		remove_wait_queue(&apm_waitqueue, &wait);
+	}
+	i = count;
+	while ((i >= sizeof(event)) && !queue_empty(as)) {
+		event = get_queued_event(as);
+                printk("  do_read: event=%d\n", event);
+		if (copy_to_user(buf, &event, sizeof(event))) {
+			if (i < count)
+				break;
+			return -EFAULT;
+		}
+		switch (event) {
+		case APM_SYS_SUSPEND:
+		case APM_USER_SUSPEND:
+			as->suspends_read++;
+			break;
+
+		case APM_SYS_STANDBY:
+		case APM_USER_STANDBY:
+			as->standbys_read++;
+			break;
+		}
+		buf += sizeof(event);
+		i -= sizeof(event);
+	}
+	if (i < count)
+		return count - i;
+	if (signal_pending(current))
+		return -ERESTARTSYS;
+	return 0;
+}
+
+static unsigned int do_poll(struct file *fp, poll_table * wait)
+{
+	struct apm_user * as;
+
+	as = fp->private_data;
+	if (check_apm_user(as, "poll"))
+		return 0;
+	poll_wait(fp, &apm_waitqueue, wait);
+	if (!queue_empty(as))
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+extern int pm_do_suspend(void);
+
+static int do_ioctl(struct inode * inode, struct file *filp,
+		    u_int cmd, u_long arg)
+{
+	struct apm_user *	as;
+	struct pm_dev *		pm;
+
+	as = filp->private_data;
+	if (check_apm_user(as, "ioctl"))
+		return -EIO;
+	if (!as->suser)
+		return - EPERM;
+	switch (cmd) {
+        case APM_IOC_SUSPEND:
+		omap_pm_suspend();
+		break;
+        case APM_IOC_SET_WAKEUP:
+		if ((pm = pm_find((pm_dev_t)arg,NULL)) == NULL)
+			return -EINVAL;
+		pm_send(pm,PM_SET_WAKEUP,NULL);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int do_release(struct inode * inode, struct file * filp)
+{
+	struct apm_user *	as;
+
+	as = filp->private_data;
+	if (check_apm_user(as, "release"))
+		return 0;
+	filp->private_data = NULL;
+	lock_kernel();
+	unlock_kernel();
+	kfree(as);
+	return 0;
+}
+
+static int do_open(struct inode * inode, struct file * filp)
+{
+	struct apm_user *	as;
+
+	as = (struct apm_user *)kmalloc(sizeof(*as), GFP_KERNEL);
+	if (as == NULL) {
+		printk(KERN_ERR "apm: cannot allocate struct of size %d bytes\n",
+		       sizeof(*as));
+		return -ENOMEM;
+	}
+	as->magic = APM_BIOS_MAGIC;
+	as->event_tail = as->event_head = 0;
+	as->suspends_pending = as->standbys_pending = 0;
+	as->suspends_read = as->standbys_read = 0;
+	/*
+	 * XXX - this is a tiny bit broken, when we consider BSD
+         * process accounting. If the device is opened by root, we
+	 * instantly flag that we used superuser privs. Who knows,
+	 * we might close the device immediately without doing a
+	 * privileged operation -- cevans
+	 */
+	as->suser = capable(CAP_SYS_ADMIN);
+	as->next = user_list;
+	user_list = as;
+	filp->private_data = as;
+	return 0;
+}
+
+static int apm_get_info(char *buf, char **start, off_t fpos, int length)
+{
+	char *		p;
+	unsigned short	dx;
+	unsigned short	error;
+	unsigned char   ac_line_status = 0xff;
+	unsigned char   battery_status = 0xff;
+	unsigned char   battery_flag   = 0xff;
+        unsigned char   percentage     = 0xff;
+	int             time_units     = -1;
+	char            *units         = "?";
+
+	p = buf;
+
+	if ((smp_num_cpus == 1) &&
+	    !(error = apm_get_power_status(&ac_line_status,
+                                           &battery_status, &battery_flag, &percentage, &dx))) {
+		if (apm_bios_info.version > 0x100) {
+			if (dx != 0xffff) {
+				units = (dx & 0x8000) ? "min" : "sec";
+				time_units = dx & 0x7fff;
+			}
+		}
+	}
+	/* Arguments, with symbols from linux/apm_bios.h.  Information is
+	   from the Get Power Status (0x0a) call unless otherwise noted.
+
+	   0) Linux driver version (this will change if format changes)
+	   1) APM BIOS Version.  Usually 1.0, 1.1 or 1.2.
+	   2) APM flags from APM Installation Check (0x00):
+	      bit 0: APM_16_BIT_SUPPORT
+	      bit 1: APM_32_BIT_SUPPORT
+	      bit 2: APM_IDLE_SLOWS_CLOCK
+	      bit 3: APM_BIOS_DISABLED
+	      bit 4: APM_BIOS_DISENGAGED
+	   3) AC line status
+	      0x00: Off-line
+	      0x01: On-line
+	      0x02: On backup power (BIOS >= 1.1 only)
+	      0xff: Unknown
+	   4) Battery status
+	      0x00: High
+	      0x01: Low
+	      0x02: Critical
+	      0x03: Charging
+	      0x04: Selected battery not present (BIOS >= 1.2 only)
+	      0xff: Unknown
+	   5) Battery flag
+	      bit 0: High
+	      bit 1: Low
+	      bit 2: Critical
+	      bit 3: Charging
+	      bit 7: No system battery
+	      0xff: Unknown
+	   6) Remaining battery life (percentage of charge):
+	      0-100: valid
+	      -1: Unknown
+	   7) Remaining battery life (time units):
+	      Number of remaining minutes or seconds
+	      -1: Unknown
+	   8) min = minutes; sec = seconds */
+
+	p += sprintf(p, "%s %d.%d 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n",
+		     driver_version,
+		     (apm_bios_info.version >> 8) & 0xff,
+		     apm_bios_info.version & 0xff,
+		     apm_bios_info.flags,
+		     ac_line_status,
+		     battery_status,
+		     battery_flag,
+		     percentage,
+		     time_units,
+		     units);
+
+	return p - buf;
+}
+
+#ifndef MODULE
+static int __init apm_setup(char *str)
+{
+	int	invert;
+
+	while ((str != NULL) && (*str != '\0')) {
+		if (strncmp(str, "off", 3) == 0)
+			apm_disabled = 1;
+		if (strncmp(str, "on", 2) == 0)
+			apm_disabled = 0;
+		invert = (strncmp(str, "no-", 3) == 0);
+		if (invert)
+			str += 3;
+		if (strncmp(str, "debug", 5) == 0)
+			debug = !invert;
+		if ((strncmp(str, "power-off", 9) == 0) ||
+		    (strncmp(str, "power_off", 9) == 0))
+			power_off = !invert;
+		str = strchr(str, ',');
+		if (str != NULL)
+			str += strspn(str, ", \t");
+	}
+	return 1;
+}
+
+__setup("apm=", apm_setup);
+#endif
+
+static struct file_operations apm_bios_fops = {
+	owner:		THIS_MODULE,
+	read:		do_read,
+	poll:		do_poll,
+	ioctl:		do_ioctl,
+	open:		do_open,
+	release:	do_release,
+};
+
+static struct miscdevice apm_device = {
+	APM_MINOR_DEV,
+	"apm_bios",
+	&apm_bios_fops
+};
+
+#define APM_INIT_ERROR_RETURN	return -1
+
+/*
+ * Just start the APM thread. We do NOT want to do APM BIOS
+ * calls from anything but the APM thread, if for no other reason
+ * than the fact that we don't trust the APM BIOS. This way,
+ * most common APM BIOS problems that lead to protection errors
+ * etc will have at least some level of being contained...
+ *
+ * In short, if something bad happens, at least we have a choice
+ * of just killing the apm thread..
+ */
+static int __init apm_init(void)
+{
+	if (apm_bios_info.version == 0) {
+		printk(KERN_INFO "apm: BIOS not found.\n");
+		APM_INIT_ERROR_RETURN;
+	}
+	printk(KERN_INFO
+		"apm: BIOS version %d.%d Flags 0x%02x (Driver version %s)\n",
+		((apm_bios_info.version >> 8) & 0xff),
+		(apm_bios_info.version & 0xff),
+		apm_bios_info.flags,
+		driver_version);
+
+	if (apm_disabled) {
+		printk(KERN_NOTICE "apm: disabled on user request.\n");
+		APM_INIT_ERROR_RETURN;
+	}
+
+	if (PM_IS_ACTIVE()) {
+		printk(KERN_NOTICE "apm: overridden by ACPI.\n");
+		APM_INIT_ERROR_RETURN;
+	}
+	pm_active = 1;
+
+	create_proc_info_entry("apm", 0, NULL, apm_get_info);
+
+	misc_register(&apm_device);
+
+	return 0;
+}
+
+static void __exit apm_exit(void)
+{
+	misc_deregister(&apm_device);
+	remove_proc_entry("apm", NULL);
+	if (power_off)
+		pm_power_off = NULL;
+	exit_kapmd = 1;
+	while (kapmd_running)
+		schedule();
+	pm_active = 0;
+}
+
+module_init(apm_init);
+module_exit(apm_exit);
+
+MODULE_AUTHOR("Jamey Hicks, pulling bits from original by Stephen Rothwell");
+MODULE_DESCRIPTION("A minimal emulation of APM");
+MODULE_PARM(debug, "i");
+MODULE_PARM_DESC(debug, "Enable debug mode");
+MODULE_PARM(power_off, "i");
+MODULE_PARM_DESC(power_off, "Enable power off");
+
+EXPORT_NO_SYMBOLS;
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/arch.c linux-2.4.19/arch/arm/mach-omap1510/arch.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/arch.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/arch.c	2003-01-15 09:50:36.000000000 +0200
@@ -0,0 +1,181 @@
+/*
+ *  linux/arch/arm/mach-omap1510/arch.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   sets up the mach_type definition
+ *
+ * Copyright (C) 2000 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/major.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/ck.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+int
+cpu_type(void)
+{
+	int processor_type;
+	processor_type = inl(OMAP1510_ID_CODE_REG);
+	if (processor_type == 0) {
+		return OMAP1509;
+	} else {
+		return OMAP1510;
+	}
+}
+
+void
+board_init(void)
+{
+
+	/*
+	   Enable Bluetooth UART gating (BT serial port).  All other UART ports
+	   are disabled between FUNC_MUX_CTRL_0 and the FPGA's power settings.
+	 */
+	if (cpu_type() == OMAP1509) {
+#if defined (CONFIG_OMAP_1510P1)
+		outl(((1 << 25) | (1 << 9)), FUNC_MUX_CTRL_0);
+#endif
+#if defined (CONFIG_OMAP_INNOVATOR)
+		outl((1 << 24), FUNC_MUX_CTRL_0);
+#endif
+	}
+
+	if (cpu_type() == OMAP1510) {
+		/* Set up advanced config registers for 1510 mode */
+		outl(0x00000000, FUNC_MUX_CTRL_3);
+		outl(0x00000000, FUNC_MUX_CTRL_4);
+		outl(0x00000000, FUNC_MUX_CTRL_5);
+		outl(0x00000012, FUNC_MUX_CTRL_6);
+		outl(0x00000000, FUNC_MUX_CTRL_7);
+		outl(0x00000009, FUNC_MUX_CTRL_8);
+		outl(0x08201000, FUNC_MUX_CTRL_9);
+		outl(0x00000001, FUNC_MUX_CTRL_A);
+		outl(0x00000000, FUNC_MUX_CTRL_B);
+		outl(0x09000000, FUNC_MUX_CTRL_C);
+		outl(0x00000000, FUNC_MUX_CTRL_D);
+		outl(0xfffeffff, PULL_DWN_CTRL_0);
+
+		//outl(0xd1fb8000, PULL_DWN_CTRL_1);
+		//outl(0xd1838000, PULL_DWN_CTRL_1);
+		outl(0xd1808000, PULL_DWN_CTRL_1);
+
+		outl(0x00200c5b, PULL_DWN_CTRL_2);
+		outl(0xffffc1fe, PULL_DWN_CTRL_3);
+		outl(0x00000000, GATE_INH_CTRL_0);
+		outl(0x00000007, VOLTAGE_CTRL_0);
+		outl(0x00000007, TEST_DBG_CTRL_0);
+
+		//outl(0x0d010000, MOD_CONF_CTRL_0);
+		outl(0x0b010000, MOD_CONF_CTRL_0);
+		
+		/* Then change to 1510 mode */
+		outl(0xeaef, COMP_MODE_CTRL_0);
+	}
+
+	/*
+	   Set TC EMIFF and EMIFS values based on clock speed.
+	   rrload leaves them higher than they may need to be.
+	 */
+
+	/*
+	  EMIFS_CS0_CONFIG values
+	  bits 0x210000: FL=1,BW=0,RDMODE=001 (4 word page mode read)
+	  0x212139: PGWST/WELEN=0010,WRWST=0001,RDWST=0011,RT=0,FCLKDIV=01
+	  0x21213a: PGWST/WELEN=0010,WRWST=0001,RDWST=0011,RT=0,FCLKDIV=02
+	  0x212080: PGWST/WELEN=0010,WRWST=0000,RDWST=1000,RT=0,FCLKDIV=00
+	  0x2130b0: PGWST/WELEN=0011,WRWST=0000,RDWST=1011,RT=0,FCLKDIV=00
+	  FCLKDIV values 0: /1, 1: /2. 2: /4, 3: /6
+	 */
+#if defined(CONFIG_OMAP_ARM_168MHZ)
+	outl(0x2130b0, EMIFS_CS0_CONFIG);
+	outl(0x102fcf8, EMIFF_SDRAM_CONFIG);
+#else
+	outl(0x212080, EMIFS_CS0_CONFIG);
+	outl(0x102fcf8, EMIFF_SDRAM_CONFIG);
+#endif
+
+#if defined(CONFIG_OMAP_1510P1)
+	/* FIXME: This may not be needed */
+	outl(0x102fcb8, EMIFF_SDRAM_CONFIG);
+	outl(0x27, EMIFF_MRS);
+#endif
+
+	/*
+	   Set TIPB to buffer writes to all 4 TIPB MPU strobes.
+	 */
+#if	0
+	outw(0x3, MPU_PUBLIC_TIPB_CNTL_REG);
+	outw(0x3, MPU_PRIVATE_TIPB_CNTL_REG);
+#else
+	/* REVISIT: Refer to 5910 Errata, Advisory SYS_1: "Timeout Abort
+	 * on aPosted Write in the TIPB Bridge".
+	 */
+	outw(0x0, MPU_PUBLIC_TIPB_CNTL_REG);
+	outw(0x0, MPU_PRIVATE_TIPB_CNTL_REG);
+#endif
+
+	printk("XXX calling init_ck, this is where things may hang...\n");
+	init_ck();
+	printk("XXX got done with init_ck\n");
+}
+
+void __init
+omap1510_fixup(struct machine_desc *desc, struct param_struct *params,
+	       char **cmdline, struct meminfo *mi)
+{
+	setup_initrd(0xc0200000, 0x300000);
+#define RRLOAD_MAGIC "kcmdline-->"
+#define RRLOAD_CMDLINE ((char*) 0xC0000100)
+	*cmdline = &RRLOAD_CMDLINE[strlen(RRLOAD_MAGIC) + 1];
+	if (strncmp(RRLOAD_MAGIC, RRLOAD_CMDLINE, strlen(RRLOAD_MAGIC)) ||
+	    (**cmdline == 0)) {
+		*cmdline = CONFIG_CMDLINE;
+	}
+}
+
+extern void omap1510_map_io(void);
+extern void irq_init_irq(void);
+
+MACHINE_START(INNOVATOR, "OMAP Innovator")
+    MAINTAINER("MontaVista Software, Inc.")
+    BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
+    FIXUP(omap1510_fixup)
+    MAPIO(omap1510_map_io)
+    INITIRQ(irq_init_irq)
+    MACHINE_END
+EXPORT_SYMBOL(cpu_type);
+
+/* ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/arch_timer.h linux-2.4.19/arch/arm/mach-omap1510/arch_timer.h
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/arch_timer.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/arch_timer.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,151 @@
+/*
+ * File: arch_timer.h
+ *
+ * Arch-specific timer internals
+ *
+ * DESCRIPTION                                                                   
+ *    This file attempts to encapsulate all the arch-specific details needed
+ *    by the generic timer.c. All arch_timer.h headers need to provide the
+ *    definitions in the 'interface' section. The stuff in the 'internals'
+ *    section may vary.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: <author> <author-email> <date>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#ifndef dsplinux_arch_timer_h
+#define dsplinux_arch_timer_h
+
+#ifndef __TIMER_INTERNAL__
+#error Only timer.c should include this file
+#endif
+
+#include <asm/arch/irqs.h>
+
+/* In case it isn't obvious, most of this crap is a bad idea. The timer table
+   is ok, and the register access macros are borderline, but the masks and 
+   feature macros are too much. Let this serve as a cautionary example to
+   myself and others.
+   --gmcnutt   
+ */
+
+/*****************************************************************************
+                          I n t e r f a c e
+ *****************************************************************************/
+#define TIMER_N sizeof(__timer_table)/sizeof(timer_info_t)
+#define TIMER_MAX_RATE 120	/* hack alert! this really depends on DPLL1 */
+#define TIMER_MIN_RATE 12	/* hack alert! assumes CLKIN */
+#define TIMER_SLOW_INPUT_CK clkin
+#define TIMER_FAST_INPUT_CK ck_gen1
+#define TIMER_MAX_DIV (1 << TIMER_MAX_PTV)
+#define TIMER_MAX_PTV 8
+
+#define TIMER_CK(timer) \
+        (TIMER_IS_WDG(timer) ? clkin /* hack */: mputim_ck)
+#define TIMER_COUNT_MAX(timer) \
+        (TIMER_IS_WDG((timer)) ? 0xffff : 0xffffffff)
+#define TIMER_IRQ(timer) __timer_table[(timer)].irq
+#define TIMER_CNTL_REG(timer) __timer_table[(timer)].cntl
+#define TIMER_LOAD_REG(timer) __timer_table[(timer)].load
+#define TIMER_READ_REG(timer) __timer_table[(timer)].read
+#define TIMER_MODE_REG(timer) __timer_table[(timer)].mode
+#define TIMER_FEATS(timer) __timer_table[(timer)].feats
+
+#define TIMER_CHECK(timer) (((timer) >= 0) && ((timer) < TIMER_N))
+#define TIMER_START_MASK(timer) __timer_table[(timer)].start_mask
+#define TIMER_PTV_MASK(timer) __timer_table[(timer)].ptv_mask
+#define TIMER_STOP_MASK(timer) TIMER_START_MASK(timer)
+#define TIMER_CAN_RST(timer) (__timer_table[(timer)].feats & TIMERF_RST)
+#define TIMER_MODE_MASK(timer) __timer_table[(timer)].mode_mask
+#define TIMER_IS_WDG(timer) TIMER_CAN_RST(timer)
+/*****************************************************************************
+                          I n t e r n a l s
+ *****************************************************************************/
+typedef struct {
+	int irq;
+	volatile __u32 *cntl;
+	volatile __u32 *load;
+	volatile __u32 *read;
+	volatile __u32 *mode;	/* Only applies to watchdog timer */
+	__u8 start_mask;
+	__u16 ptv_mask;
+	__u16 mode_mask;
+	int feats;
+} timer_info_t;
+
+#define TIMER_STD_FEATS (TIMERF_PERIODIC|TIMERF_ONESHOT|TIMERF_INT)
+#define TIMER_WDT_FEATS (TIMERF_PERIODIC|TIMERF_ONESHOT|TIMERF_INT|TIMERF_RST)
+#define TIMER_STD_SMASK ((1 << 5) | 1)
+#define TIMER_STD_PMASK (7 << 2)
+#define TIMER_STD_MMASK (1 << 1)
+
+/* Keep the watchdog timer first so that people scanning for it at runtime will
+   find it immediately.
+*/
+timer_info_t __timer_table[] = {
+	{
+	      cntl:(volatile __u32 *) 0xfffec800,
+	      load:(volatile __u32 *) 0xfffec804,
+	      read:(volatile __u32 *) 0xfffec804,
+					/* Yes, same as load */
+	      mode:(volatile __u32 *) 0xfffec808,
+	      feats:TIMER_WDT_FEATS,
+	      start_mask:(1 << 7),
+	      ptv_mask:(7 << 9),
+	      mode_mask:(1 << 8),
+      irq:INT_WD_TIMER},
+	{
+	      cntl:(volatile __u32 *) 0xfffec500,
+	      load:(volatile __u32 *) 0xfffec504,
+	      read:(volatile __u32 *) 0xfffec508,
+	      feats:TIMER_STD_FEATS,
+	      start_mask:TIMER_STD_SMASK,
+	      ptv_mask:TIMER_STD_PMASK,
+	      mode_mask:TIMER_STD_MMASK,
+      irq:INT_TIMER1},
+	{
+	      cntl:(volatile __u32 *) 0xfffec600,
+	      load:(volatile __u32 *) 0xfffec604,
+	      read:(volatile __u32 *) 0xfffec608,
+	      feats:TIMER_STD_FEATS,
+	      start_mask:TIMER_STD_SMASK,
+	      ptv_mask:TIMER_STD_PMASK,
+	      mode_mask:TIMER_STD_MMASK,
+      irq:INT_TIMER2},
+	{
+	      cntl:(volatile __u32 *) 0xfffec700,
+	      load:(volatile __u32 *) 0xfffec704,
+	      read:(volatile __u32 *) 0xfffec708,
+	      feats:TIMER_STD_FEATS,
+	      start_mask:TIMER_STD_SMASK,
+	      ptv_mask:TIMER_STD_PMASK,
+	      mode_mask:TIMER_STD_MMASK,
+      irq:INT_TIMER3},
+};
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/ck.c linux-2.4.19/arch/arm/mach-omap1510/ck.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/ck.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/ck.c	2003-01-15 10:30:04.000000000 +0200
@@ -0,0 +1,651 @@
+/*
+ * File: ck.c
+ *
+ * Implements the clock interface for the omap
+ *
+ * Created 2001, Copyright (C) 2001 RidgeRun, Inc.  All rights reserved.
+ * Author: Gordon McNutt <gmcnutt@ridgerun.com>
+ * History:
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <asm/arch/ck.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/page.h>		/* for BUG */
+#include <asm/bitops.h>
+//#include <string.h>
+
+/*****************************************************************************/
+/* omap-specific section */
+
+typedef struct {
+	char *name;
+	__u8 flags;
+	ck_t parent;
+	volatile __u16 *rreg;
+	volatile __u16 *ereg;
+	volatile __u16 *ireg;
+	volatile __u16 *sreg;
+	__s8 rshift;
+	__s8 eshift;
+	__s8 ishift;
+	__s8 sshift;
+} ck_info_t;
+
+#define CK_NAME(ck) ck_info_table[ck].name
+#define CK_FLAGS(ck) ck_info_table[ck].flags
+#define CK_PARENT(ck) ck_info_table[ck].parent
+#define CK_RATE_REG(ck) ck_info_table[ck].rreg
+#define CK_ENABLE_REG(ck) ck_info_table[ck].ereg
+#define CK_IDLE_REG(ck) ck_info_table[ck].ireg
+#define CK_SELECT_REG(ck) ck_info_table[ck].sreg
+#define CK_RATE_SHIFT(ck) ck_info_table[ck].rshift
+#define CK_ENABLE_SHIFT(ck) ck_info_table[ck].eshift
+#define CK_IDLE_SHIFT(ck) ck_info_table[ck].ishift
+#define CK_SELECT_SHIFT(ck) ck_info_table[ck].sshift
+#define CK_CAN_CHANGE_RATE(cl) (CK_FLAGS(ck) & CK_RATEF)
+#define CK_CAN_DISABLE(cl) (CK_FLAGS(ck) & CK_ENABLEF)
+#define CK_CAN_IDLE(cl) (CK_FLAGS(ck) & CK_IDLEF)
+#define CK_CAN_SWITCH(cl) (CK_FLAGS(ck) & CK_SELECTF)
+
+static ck_info_t ck_info_table[] = {
+	{
+	      name:"clkin",
+	      flags:0,
+	      parent:clkin,
+	 },
+	{
+	      name:"ck_gen1",
+	      flags:CK_RATEF | CK_IDLEF,
+	      rreg:CK_DPLL1,
+	      ireg:ARM_IDLECT1,
+	      ishift:IDLDPLL_ARM,
+	      parent:clkin,
+	 },
+	{
+	      name:"ck_gen2",
+	      flags:0,
+	      parent:ck_gen1,
+	 },
+	{
+	      name:"ck_gen3",
+	      flags:0,
+	      parent:ck_gen1,
+	 },
+	{
+	      name:"tc_ck",
+	      flags:CK_RATEF | CK_IDLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      rshift:TCDIV,
+      ishift:IDLIF_ARM},
+	{
+	      name:"arm_ck",
+	      flags:CK_IDLEF | CK_RATEF,
+	      parent:ck_gen1,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      rshift:ARMDIV,
+	      ishift:SETARM_IDLE,
+	 },
+	{
+	      name:"mpuper_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen1,
+	      rreg:ARM_CKCTL,
+	      ereg:ARM_IDLECT2,
+	      ireg:ARM_IDLECT1,
+	      rshift:PERDIV,
+	      eshift:EN_PERCK,
+      ishift:IDLPER_ARM},
+	{
+	      name:"arm_gpio_ck",
+	      flags:CK_ENABLEF,
+	      parent:ck_gen1,
+	      ereg:ARM_IDLECT2,
+      eshift:EN_GPIOCK},
+	{
+	      name:"mpuxor_ck",
+	      flags:CK_ENABLEF | CK_IDLEF,
+	      parent:clkin,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      ishift:IDLXORP_ARM,
+      eshift:EN_XORPCK},
+	{
+	      name:"mputim_ck",
+	      flags:CK_IDLEF | CK_ENABLEF | CK_SELECTF,
+	      parent:ck_gen1,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      sreg:ARM_CKCTL,
+	      ishift:IDLTIM_ARM,
+	      eshift:EN_TIMCK,
+      sshift:ARM_TIMXO},
+	{
+	      name:"mpuwd_ck",
+	      flags:CK_IDLEF | CK_ENABLEF,
+	      parent:clkin,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      ishift:IDLWDT_ARM,
+	      eshift:EN_WDTCK,
+	 },
+	{
+	      name:"dsp_ck",
+	      flags:CK_RATEF | CK_ENABLEF,
+	      parent:ck_gen2,
+	      rreg:ARM_CKCTL,
+	      ereg:ARM_CKCTL,
+	      rshift:DSPDIV,
+	      eshift:EN_DSPCK,
+	 },
+	{
+	      name:"dspmmu_ck",
+	      flags:CK_RATEF | CK_ENABLEF,
+	      parent:ck_gen2,
+	      rreg:ARM_CKCTL,
+	      ereg:ARM_CKCTL,
+	      rshift:DSPMMUDIV,
+	      eshift:EN_DSPCK,
+	 },
+	{
+	      name:"dma_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      rshift:TCDIV,
+	      ishift:IDLIF_ARM,
+      eshift:DMACK_REQ},
+	{
+	      name:"api_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      rshift:TCDIV,
+	      ishift:IDLAPI_ARM,
+	      eshift:EN_APICK,
+	 },
+	{
+	      name:"hsab_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      rshift:TCDIV,
+	      ishift:IDLHSAB_ARM,
+	      eshift:EN_HSABCK,
+	 },
+	{
+	      name:"lbfree_ck",
+	      flags:CK_RATEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ereg:ARM_IDLECT2,
+	      rshift:TCDIV,
+	      eshift:EN_LBFREECK,
+	 },
+	{
+	      name:"lb_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      rshift:TCDIV,
+	      ishift:IDLLB_ARM,
+	      eshift:EN_LBCK,
+	 },
+	{
+	      name:"lcd_ck",
+	      flags:CK_RATEF | CK_IDLEF | CK_ENABLEF,
+	      parent:ck_gen3,
+	      rreg:ARM_CKCTL,
+	      ireg:ARM_IDLECT1,
+	      ereg:ARM_IDLECT2,
+	      rshift:LCDDIV,
+	      ishift:IDLLCD_ARM,
+	      eshift:EN_LCDCK,
+	 },
+};
+
+/*****************************************************************************/
+
+#define CK_IN_RANGE(ck) (!((ck < CK__MIN) || (ck > CK__MAX)))
+
+#define CK_MAX_PLL_FREQ CK__MAX_RATE
+
+int ck_auto_unclock = 1;
+int ck_debug = 0;
+
+static __u8 ck_valid_table[CK_MAX_PLL_FREQ / 8 + 1];
+static __u8 ck_lookup_table[CK_MAX_PLL_FREQ];
+
+int
+ck_set_input(ck_t ck, ck_t input)
+{
+	int ret = 0, shift;
+	volatile __u16 *reg;
+
+	if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	reg = CK_SELECT_REG(ck);
+	shift = CK_SELECT_SHIFT(ck);
+
+	if (input == clkin) {
+		*((volatile __u16 *) reg) &= ~(1 << shift);
+		goto exit;
+	} else if (input == CK_PARENT(ck)) {
+		*((volatile __u16 *) reg) |= (1 << shift);
+		goto exit;
+	}
+
+	ret = -EINVAL;
+      exit:
+	return ret;
+}
+
+int
+ck_get_input(ck_t ck, ck_t * input)
+{
+	int ret = -EINVAL;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	ret = 0;
+
+	if (CK_CAN_SWITCH(ck)) {
+		int shift;
+		volatile __u16 *reg;
+
+		reg = CK_SELECT_REG(ck);
+		shift = CK_SELECT_SHIFT(ck);
+		if (*reg & (1 << shift)) {
+			*input = CK_PARENT(ck);
+			goto exit;
+		}
+	}
+
+	*input = clkin;
+
+      exit:
+	return ret;
+}
+
+static int
+__ck_set_pll_rate(ck_t ck, int rate)
+{
+	volatile __u16 *pll;
+
+	if ((rate < 0) || (rate > CK_MAX_PLL_FREQ))
+		return -EINVAL;
+
+	/* scan downward for the closest matching frequency */
+	while (rate && !test_bit(rate, &ck_valid_table))
+		rate--;
+
+	if (!rate) {
+		printk(__FUNCTION__ ": couldn't find a matching rate\n");
+		return -EINVAL;
+	}
+
+	pll = (volatile __u16 *) CK_RATE_REG(ck);
+
+	/* clear the rate bits */
+	*pll &= ~(0x1f << 5);
+
+	/* set the rate bits */
+	*pll |= (ck_lookup_table[rate - 1] << 5);
+
+	return 0;
+}
+
+static int
+__ck_set_clkm_rate(ck_t ck, int rate)
+{
+	int shift, prate, div, ret;
+	volatile __u16 *reg;
+
+	/* Now. We can only set this clock's value to a fraction of its 
+	   parent's value. The interface says I'll round down when necessary.
+	   So first let's get the parent's current rate. */
+	prate = ck_get_rate(CK_PARENT(ck));
+
+	/* Now let's just start with the highest fraction and keep searching
+	   down through available rates until we find one less than or equal 
+	   to the desired rate. */
+	for (div = 0; div < 4; div++) {
+		if (prate <= rate)
+			break;
+		prate = prate / 2;
+	}
+
+	/* Oops. Looks like the caller wants a rate lower than we can support.
+	   Sorry, sucker. */
+	if (div == 5) {
+		printk(__FUNCTION__ ": %d is too low\n", rate);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	/* One more detail: if this clock supports more than one parent, then
+	   we're going to automatically switch over to the parent which runs
+	   through the divisor. For omap this is not ambiguous because for all
+	   such clocks one choice is always CLKIN (which doesn't run through 
+	   the divisor) and the other is whatever I encoded as CK_PARENT. Note
+	   that I wait until we get this far because I don't want to switch
+	   the input until we're sure this is going to work. */
+	if (CK_CAN_SWITCH(ck))
+		if ((ret = ck_set_input(ck, CK_PARENT(ck))) < 0) {
+			BUG();
+			goto exit;
+		}
+
+	/* Now, at last, we can set the divisor. Clear the old rate bits and
+	   set the new ones. */
+	reg = (volatile __u16 *) CK_RATE_REG(ck);
+	shift = CK_RATE_SHIFT(ck);
+	*reg &= ~(3 << shift);
+	*reg |= (div << shift);
+
+	/* And return the new (actual, after rounding down) rate. */
+	ret = prate;
+
+      exit:
+	return ret;
+}
+
+int
+ck_set_rate(ck_t ck, int rate)
+{
+	int ret = -EINVAL;
+
+	if (!CK_IN_RANGE(ck) || !CK_CAN_CHANGE_RATE(ck))
+		goto exit;
+
+	switch (ck) {
+
+	default:
+		ret = __ck_set_clkm_rate(ck, rate);
+		break;
+
+	case ck_gen1:
+		ret = __ck_set_pll_rate(ck, rate);
+		break;
+
+	};
+
+      exit:
+	return ret;
+}
+
+static int
+__ck_get_pll_rate(ck_t ck)
+{
+	int m, d;
+
+	__u16 pll = *((volatile __u16 *) CK_RATE_REG(ck));
+
+	m = (pll & (0x1f << 7)) >> 7;
+	m = m ? m : 1;
+	d = (pll & (3 << 5)) >> 5;
+	d++;
+
+	return ((CK_CLKIN * m) / d);
+}
+
+static int
+__ck_get_clkm_rate(ck_t ck)
+{
+	static int bits2div[] = { 1, 2, 4, 8 };
+	int in, bits, reg, shift;
+
+	reg = *(CK_RATE_REG(ck));
+	shift = CK_RATE_SHIFT(ck);
+
+	in = ck_get_rate(CK_PARENT(ck));
+	bits = (reg & (3 << shift)) >> shift;
+	return (in / bits2div[bits]);
+}
+
+int
+ck_get_rate(ck_t ck)
+{
+	int ret = 0;
+	ck_t parent;
+
+	if (!CK_IN_RANGE(ck)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	switch (ck) {
+
+	case ck_gen1:
+		ret = __ck_get_pll_rate(ck);
+		break;
+
+	case clkin:
+		ret = CK_CLKIN;
+		break;
+
+	case mpuxor_ck:
+	case ck_gen2:
+	case ck_gen3:
+	case arm_gpio_ck:
+		ret = ck_get_rate(CK_PARENT(ck));
+		break;
+
+	case arm_ck:
+	case mpuper_ck:
+	case dsp_ck:
+	case dspmmu_ck:
+	case lcd_ck:
+	case tc_ck:
+	case dma_ck:
+	case api_ck:
+	case hsab_ck:
+	case lbfree_ck:
+	case lb_ck:
+		ret = __ck_get_clkm_rate(ck);
+		break;
+
+	case mputim_ck:
+		ck_get_input(ck, &parent);
+		ret = ck_get_rate(parent);
+		break;
+
+	case mpuwd_ck:
+		/* Note that this evaluates to zero when CK_CLKIN is 12MHz. */
+		ret = CK_CLKIN / 14;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+      exit:
+	return ret;
+}
+
+int
+ck_enable(ck_t ck)
+{
+	volatile __u16 *reg;
+	int ret = -EINVAL, shift;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	if (ck_debug)
+		printk(__FUNCTION__ " %s\n", CK_NAME(ck));
+
+	ret = 0;
+
+	if (!CK_CAN_DISABLE(ck))
+		/* Then it must be on... */
+		goto exit;
+
+	reg = CK_ENABLE_REG(ck);
+	shift = CK_ENABLE_SHIFT(ck);
+	*reg |= (1 << shift);
+
+      exit:
+	return ret;
+}
+
+int
+ck_disable(ck_t ck)
+{
+	volatile __u16 *reg;
+	int ret = -EINVAL, shift;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	if (ck_debug)
+		printk(__FUNCTION__ " %s\n", CK_NAME(ck));
+
+	if (!CK_CAN_DISABLE(ck))
+		goto exit;
+
+	ret = 0;
+
+	if (ck == clkin)
+		return -EINVAL;
+
+	reg = CK_ENABLE_REG(ck);
+	shift = CK_ENABLE_SHIFT(ck);
+	*reg &= ~(1 << shift);
+
+      exit:
+	return ret;
+}
+static void
+__ck_make_lookup_table(void)
+{
+	__u8 m, d;
+
+	memset(ck_valid_table, 0, sizeof (ck_valid_table));
+
+	for (m = 1; m < 32; m++)
+		for (d = 1; d < 5; d++) {
+
+			int rate = ((CK_CLKIN * m) / (d));
+
+			if (rate > CK_MAX_PLL_FREQ)
+				continue;
+			if (test_bit(rate, &ck_valid_table))
+				continue;
+			set_bit(rate, &ck_valid_table);
+			ck_lookup_table[rate - 1] = (m << 2) | (d - 1);
+		}
+}
+
+int __init
+init_ck(void)
+{
+//        printk("DSPLinux Clock Control (c) 2001 RidgeRun, Inc.\n");
+	__ck_make_lookup_table();
+
+#if defined(CONFIG_OMAP_ARM_120MHZ)
+	printk("XXX configuring clock for 120MHz\n");
+#ifdef CONFIG_OMAP_1510P1
+	/* FIXME: These need to be verified on 1510DC, Innovator values are unstable */
+	printk("XXX Setting clocks, this needs to be checked in ck.c\n");
+	outw(0x1005, CLKGEN_RESET_BASE);
+	outw(0x2390, CLKGEN_RESET_BASE + 0x100); /* More stable than 0x2510 */
+#else
+	/* Innovator */
+	outw(0x110a, CLKGEN_RESET_BASE);
+	outw(0x2510, CLKGEN_RESET_BASE + 0x100);
+#endif
+#elif defined(CONFIG_OMAP_ARM_60MHZ)
+	printk("XXX configuring clock for 60MHz\n");
+	outw(0x1005, CLKGEN_RESET_BASE);
+	outw(0x2290, CLKGEN_RESET_BASE + 0x100);
+#elif defined(CONFIG_OMAP_ARM_30MHZ)
+	printk("XXX configuring clock for 30MHz\n");
+	outw(0x1555, CLKGEN_RESET_BASE);
+	outw(0x2290, CLKGEN_RESET_BASE + 0x100);
+#elif defined(CONFIG_OMAP_ARM_168MHZ)
+	printk("XXX configuring clock for 168MHz\n");
+	outw(0x110f, CLKGEN_RESET_BASE);
+	outw(0x2710, CLKGEN_RESET_BASE + 0x100);
+#else
+#error "OMAP MHZ not set, please run make xconfig"
+#endif
+
+	// Turn off some other junk the bootloader might have turned
+	// on.
+	*ARM_CKCTL &= 0x1fff;	// Turn off DSP, ARM_INTHCK
+	*ARM_RSTCT1 = 0;	// Put DSP/MPUI into reset until needed.
+	*ARM_RSTCT2 = 1;
+	*ARM_IDLECT1 = 0x400;
+	if (inl(OMAP_LCD_CONTROL) & 1)	// Test to see if LCD is enabled.
+		*ARM_IDLECT2 = 0x108;	// Leave LCD clock on if LCD is on
+	else
+		*ARM_IDLECT2 = 0x100;	// Turn LCD clock off also.
+
+	// Only enable those clocks we will need, let the drivers
+	// enable other clocks as necessary.
+	ck_enable(mpuper_ck);
+	ck_enable(arm_gpio_ck);
+	ck_enable(mpuxor_ck);
+
+	return 0;
+}
+
+#ifdef MODULE
+static void __exit
+exit_ck(void)
+{
+}
+
+module_init(init_ck);
+module_exit(exit_ck);
+#endif
+
+EXPORT_SYMBOL(ck_get_rate);
+EXPORT_SYMBOL(ck_set_rate);
+EXPORT_SYMBOL(ck_enable);
+EXPORT_SYMBOL(ck_disable);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/dma-omap.c linux-2.4.19/arch/arm/mach-omap1510/dma-omap.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/dma-omap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/dma-omap.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,702 @@
+/*
+ * arch/arm/dsplinux/common/dma-omap.c
+ *   Derived from arch/arm/kernel/dma-sa1100.c
+ *
+ * Support functions for the OMAP internal DMA channels.
+ *
+ * Copyright (C) 2000 Nicolas Pitre
+ * Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#include <linux/delay.h>
+#endif
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+
+/*
+  The TEST code is an attempt to make auto_init work with Power management.
+  It adds some placeholders so I can see state, and it checks to see if 
+  AI is in use before it stops a current buffer.  It looks ugly,
+  but I'm leaving it in for now.
+*/
+//#define TEST        
+#undef TEST
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+//#define DPRINTK( s, arg... )  printk(" dma<%s>: " s, dma->device_id , ##arg )
+#define DPRINTK( arg... )  printk( ##arg )
+#define inline
+#else
+#define DPRINTK( x... )
+#endif
+
+#define OMAP_DMA_RESERVED_CHANNEL_BITMAP ((1 << 0) | (1 << 6))
+
+static dma_regs_t *dma_base = (dma_regs_t *) OMAP_DMA_BASE;
+static volatile u16 *gcr = (u16 *) (OMAP_DMA_BASE + 0x400);	// global control
+
+typedef struct {
+	const char *device_id;	/* device name */
+	dma_device_t device;	/* this channel device, 0  if unused */
+	dma_callback_t callback;	/* to call when DMA completes */
+	void *data;		/* ... with private data ptr */
+	dma_direction_t dir;	/* copy to device or from device? */
+	u16 status;		/* A read clears status, so we need to keep it around */
+	u8 irq;			/* IRQ used by the channel */
+	u8 in_use;		/* Does someone own the channel?  */
+	int bufcnt;		/* count of queued buffers--should be 0, 1, or 2 */
+} omap_dma_t;
+
+omap_dma_t dma_chan[MAX_OMAP_DMA_CHANNELS];
+
+#define MIN(a,b)		((a) < (b) ? (a) : (b))
+
+static spinlock_t dma_list_lock = SPIN_LOCK_UNLOCKED;
+
+static void
+dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+	dma_regs_t *dma_regs = dev_id;
+	omap_dma_t *dma =
+	    dma_chan +
+	    (((u_int) dma_regs - OMAP_DMA_BASE) / sizeof (dma_regs_t));
+	int status;
+
+	// If dma channel < 3, we share interrupts and CSR.
+	// When you check status, also set status for channel + 6.
+	if (irq < INT_DMA_CH3) {
+		status = dma_regs->csr;	// A read clears all dma status bits
+		dma->status |= (status & 0x7f);
+		dma_chan[(irq - INT_DMA_CH0_6 + 6)].status |= status >> 7;
+	} else if (irq > INT_DMA_CH5) {
+		// A read clears all dma status bits
+		status = *(u16 *) (&dma_regs->csr - (6 * sizeof (dma_regs_t)));
+		dma_chan[(irq - INT_DMA_CH0_6)].status |= (status & 0x7f);
+		dma->status |= status >> 7;
+	} else {		// Channels 3-5
+		status = dma_regs->csr;	// A read clears all dma status bits
+		dma->status |= status;
+	}
+
+	DPRINTK(__FUNCTION__ ": status = 0x%04x, dma->status = 0x%04x, bufcnt = %d\n",
+		status, dma->status, dma->bufcnt);
+	if (dma->status & (DCSR_ERROR)) {
+		// NOTE error, but don't do anything about it for now.
+		printk(KERN_ERR "DMA %x on \"%s\" caused an error %x\n", irq,
+		       dma->device_id, dma->status);
+		dma->status &= ~DCSR_ERROR;
+		dma_regs->ccr &= ~(DCCR_EN);	// disable channel so it can be re-enabled later
+	}
+	
+	if (dma->bufcnt > 0)
+		--dma->bufcnt;
+        if (dma->bufcnt == 0)
+		dma_regs->ccr &= ~(DCCR_EN);	// disable channel 
+	if (dma->callback) {
+		dma->callback(dma->data);
+	}
+	if ((dma->status & ~(DCSR_ERROR)) == 0) {
+		DPRINTK("DMA ended with no status\n");
+	}
+#ifdef DEBUG
+	if ((dma->status & 0x20) == 0) {
+		DPRINTK("DMA status %x\n", dma->status);
+	}
+#endif
+	dma->status = 0;	// reset status after callback has had a chance to process it
+
+}
+
+/*
+ * omap_dma_autoidle_set - Enable or disable the auto idle bit in the DMA global control
+ * register.
+ *
+ * Params:
+ *  set = 0 clears the bit disabling the auto idle function.  DMA clocks always on.
+ *  set = !0 sets the bit enabling the auto idle function.
+ */
+
+void
+omap_dma_autoidle_set(int set)
+{
+	if (set)
+		*gcr |= 0x8;
+	else
+		*gcr &= ~0x8;
+}
+
+/**
+ *	omap_request_dma - allocate one of the OMAP's DMA chanels
+ *	@device: The OMAP peripheral targeted by this request
+ *	@device_id: An ascii name for the claiming device
+ *	@callback: Function to be called when the DMA completes
+ *	@data: A cookie passed back to the callback function
+ *	@dma_regs: Pointer to the location of the allocated channel's identifier
+ *
+ * 	This function will search for a free DMA channel and returns the
+ * 	address of the hardware registers for that channel as the channel
+ * 	identifier. This identifier is written to the location pointed by
+ * 	@dma_regs. The list of possible values for @device are listed into
+ * 	linux/include/asm-arm/arch-omap1510/dma.h as a dma_device_t enum.
+ *
+ * 	Note that reading from a port and writing to the same port are
+ * 	actually considered as two different streams requiring separate
+ * 	DMA registrations.
+ *
+ * 	The @callback function is called from interrupt context when one
+ * 	of the two possible DMA buffers in flight has terminated. That
+ * 	function has to be small and efficient while posponing more complex
+ * 	processing to a lower priority execution context.
+ *
+ * 	If no channels are available, or if the desired @device is already in
+ * 	use by another DMA channel, then an error code is returned.  This
+ * 	function must be called before any other DMA calls.
+ **/
+
+int
+omap_request_dma(dma_device_t device, const char *device_id,
+		 dma_callback_t callback, void *data, dma_regs_t ** dma_regs)
+{
+	omap_dma_t *dma = NULL;
+	dma_regs_t *regs;
+	int i, err, status;
+
+	*dma_regs = NULL;
+
+	err = 0;
+	spin_lock(&dma_list_lock);
+	for (i = 0; i < MAX_OMAP_DMA_CHANNELS; i++) {
+		if (dma_chan[i].in_use) {
+			if ((dma_chan[i].device == device) &&
+			    (device != eDMANotSync)) {
+				err = -EBUSY;
+				break;
+			}
+		} else if (!dma) {
+			dma = &dma_chan[i];
+		}
+	}
+	if (!err) {
+		if (dma)
+			dma->device = device;
+		else
+			err = -ENOSR;
+	}
+	spin_unlock(&dma_list_lock);
+	if (err)
+		return err;
+
+	i = dma - dma_chan;
+	regs = &dma_base[i];
+
+	// NOTE:
+	//  Changed from SA_INTERRUPT to SA_SHIRQ because we may
+	// share channels 0&6, 1&7, 2&8.
+	err = request_irq(dma->irq, dma_irq_handler, SA_SHIRQ, device_id, regs);
+
+	if (err) {
+		printk(KERN_ERR
+		       "%s: unable to request IRQ %d for DMA channel\n",
+		       device_id, dma->irq);
+		return err;
+	}
+
+	*dma_regs = regs;
+	dma->device_id = device_id;
+	dma->callback = callback;
+	dma->data = data;
+	dma->in_use = 1;
+	dma->bufcnt = 0;
+
+	/*  Reset to default values */
+	regs->csdp = 0;
+	regs->ccr = device;
+	regs->cicr = 0x3;
+	status = regs->csr;	// read status to clear it.
+	regs->cssa_l = 0;
+	regs->cssa_u = 0;
+	regs->cdsa_l = 0;
+	regs->cdsa_u = 0;
+	regs->cen = 0;
+	regs->cfn = 0;
+	regs->cfi = 0;
+	regs->cei = 0;
+
+	DPRINTK("requested dma device %x\n", device);
+	return 0;
+}
+
+/**
+ * 	omap_free_dma - free a OMAP DMA channel
+ * 	@regs: identifier for the channel to free
+ *
+ * 	This clears all activities on a given DMA channel and releases it
+ * 	for future requests.  The @regs identifier is provided by a
+ * 	successful call to omap_request_dma().
+ **/
+
+void
+omap_free_dma(dma_regs_t * regs)
+{
+	int i;
+
+	for (i = 0; i < MAX_OMAP_DMA_CHANNELS; i++)
+		if (regs == &dma_base[i])
+			break;
+	if (i >= MAX_OMAP_DMA_CHANNELS) {
+		printk(KERN_ERR __FUNCTION__ ": bad DMA identifier\n");
+		return;
+	}
+
+	if (!dma_chan[i].device) {
+		printk(KERN_ERR __FUNCTION__ "Trying to free free DMA\n");
+		return;
+	}
+
+	regs->ccr = 0;
+	free_irq(dma_chan[i].irq, regs);
+	dma_chan[i].device = 0;
+        dma_chan[i].bufcnt = 0;
+	dma_chan[i].in_use = 0;
+}
+
+/**
+ * 	omap_start_dma - submit a data buffer for DMA
+ * 	@regs: identifier for the channel to use
+ * 	@dma_ptr: buffer physical (or bus) start address
+ * 	@size: buffer size
+ *
+ * 	This function hands the given data buffer to the hardware for DMA
+ * 	access. If another buffer is already in flight then this buffer
+ * 	will be queued so the DMA engine will switch to it automatically
+ * 	when the previous one is done.  The DMA engine is actually toggling
+ * 	between two buffers so at most 2 successful calls can be made before
+ * 	one of them terminates and the callback function is called.
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ *
+ * 	The @size must not be larger than %MAX_DMA_SIZE.  If a given buffer
+ * 	is larger than that then it's the caller's responsibility to split
+ * 	it into smaller chunks and submit them separately. If this is the
+ * 	case then a @size of %CUT_DMA_SIZE is recommended to avoid ending
+ * 	up with too small chunks. The callback function can be used to chain
+ * 	submissions of buffer chunks.
+ *
+ *      If the @size parameter is 0, then this assumes the user has set
+ *      up the appropriate registers that calculate DMA size, and this
+ *      doesn't try to reset them.  
+ *
+ *      If you want to DMA more than 64K, this will try to calculate registers
+ *      for you.  If you send in an odd size, this may take some time for the 
+ *      calculations, which are done with interrupts off.  So try to limit
+ *      the DMA size or send in a regs->pfn value that evenly divides the
+ *      size you send in.
+ *
+ * 	Error return values:
+ * 	%-EOVERFLOW:	Given buffer size is too big.
+ * 	%-EBUSY:	Both DMA buffers are already in use.
+ * 	%-EAGAIN:	Both buffers were busy but one of them just completed
+ * 			but the interrupt handler has to execute first.
+ *      %-EINVAL:       Can't make a valid dma request with given size parameter
+ *
+ * 	This function returs 0 on success.
+ **/
+
+int
+omap_start_dma(dma_regs_t * regs, dma_addr_t dma_ptr, u_int size)
+{
+	unsigned long flags;
+	int ret = 0;
+	int channel = (((u_int) regs - OMAP_DMA_BASE) / sizeof (dma_regs_t));
+	omap_dma_t *dma = &dma_chan[channel];
+
+	if (size > MAX_DMA_SIZE)
+		return -EOVERFLOW;
+
+	local_irq_save(flags);
+
+	if (dma->bufcnt == 2) {
+		/* if two DMA transfers are already queued then we 
+		 * can't queue another
+		 */
+		local_irq_restore(flags);
+		return -EBUSY;
+	}
+
+	DPRINTK(__FUNCTION__ ": chan = %d, bufcnt = %d, dma_ptr =  0x%08x, size = %d\n",
+		channel, dma->bufcnt, dma_ptr, size);
+	DPRINTK(__FUNCTION__ ": csdp = 0x%04x, ccr = 0x%04x, cicr = 0x%04x, cpc = 0x%04x\n",
+		regs->csdp, regs->ccr, regs->cicr, regs->cpc);
+
+        regs->ccr &= ~(DCCR_EP | DCCR_REPEAT); 
+
+	/*
+	   NOTE:
+
+	   Auto initialization conflicts with power management.  To keep track
+	   of two buffers and be able to stop and restart them correctly
+	   would require a pretty significant rewrite.  But if I turn
+	   off AI, sound playback is affected.
+
+	   So rather than affecting sound playback, note that if we go
+	   into power saving while an audio buffer is playing, we will
+	   probably not recover correctly.
+
+	   #ifdef CONFIG_PM
+	   if (auto_init) {
+	   	local_irq_restore(flags);
+	   	return -EBUSY;
+	   }
+	   #endif        
+	 */
+
+	// Setup simple transfer.
+	if (dma->dir == eDmaOut) {
+		regs->cssa_l = dma_ptr;
+		regs->cssa_u = dma_ptr >> 16;
+	} else {
+		regs->cdsa_l = dma_ptr;
+		regs->cdsa_u = dma_ptr >> 16;
+	}
+
+	// size is in bytes.  Check csdp to see how many elements to transfer:
+	if ((regs->csdp & 0x3) == 0x1) {	// 16-bit transfers
+		size >>= 1;
+	} else if ((regs->csdp & 0x3) == 0x2) {	// 32-bit transfers
+		size >>= 2;
+	}
+
+	/*
+	   If size = 0, that means the user has set up the c*n and c*i
+	   registers, so don't mess with anything.
+
+	   Otherwise, now that we know how many bytes are being sent, 
+	   let's see how they're organized.  Default case
+	   is a simple contiguous buffer with CEN=size
+	   and CFN=1.
+	   But have to check other cases, too.
+	 */
+	if (size) {
+		if ((regs->cfn == 0) || (regs->cfn == 1)) {
+			// Probably default values set by this routine.  Try using 1
+			//  for cfn, cen is 16-bit max.
+			if (size < 0x10000) {
+				regs->cen = size;
+				regs->cfn = 1;
+			} else {
+				int divider = 2;
+				while (!(((size / divider) < 0x10000) &&
+					 ((size % divider) == 0))) {
+					divider++;
+					if (divider > 0xffff) {
+						// Can't get a valid pair.
+						local_irq_restore(flags);
+						return -EINVAL;
+					}
+				}
+				regs->cen = (size / divider);
+				regs->cfn = divider;
+			}
+		} else {
+			// Assume cfn was set by user, use set value if possible
+			if ((size % regs->cfn) == 0) {
+				regs->cen = (size / regs->cfn);
+			} else {	// Numbers don't match, try to find matching ones
+				int divider = 1;
+				while (!(((size / divider) < 0x10000) &&
+					 ((size % divider) == 0))) {
+					divider++;
+					if (divider > 0xffff) {
+						// Can't get a valid pair.
+						local_irq_restore(flags);
+						return -EINVAL;
+					}
+				}
+				regs->cen = (size / divider);
+				regs->cfn = divider;
+			}
+		}
+	}
+	
+	++dma->bufcnt;
+	if (regs->ccr & DCCR_EN) {
+		/* DMA channel is running, so we need to set AI and REPEAT bits 
+		 * to tell the DMA controller to start the new transfer as soon 
+		 * as the current one is finished.
+		 */
+                regs->ccr |= DCCR_AI | DCCR_REPEAT | DCCR_EN;
+	}
+	else {
+		/* DMA channel is not running, so we don't set the REPEAT bit. */
+		regs->ccr |= DCCR_AI | DCCR_EN;
+	}
+	DPRINTK("started transfer %x, ccr = 0x%04x, cfn = 0x%04x, cen=0x%04, bufcnt=%d\n", 
+		dma_ptr, regs->ccr, regs->cfn, regs->cen, dma->bufcnt);
+	wmb();		// make sure previous writes are done before we enable.
+
+	local_irq_restore(flags);
+	return ret;
+}
+
+/**
+ * 	omap_get_dma_pos - return current DMA position
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This function returns the current physical (or bus) address for the
+ * 	given DMA channel.  If the channel is running i.e. not in a stopped
+ * 	state then the caller must disable interrupts prior calling this
+ * 	function and process the returned value before re-enabling them to
+ * 	prevent races with the completion interrupt handler and the callback
+ * 	function. The validation of the returned value is the caller's
+ * 	responsibility as well 
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ **/
+
+dma_addr_t
+omap_get_dma_pos(dma_regs_t * regs)
+{
+
+	return (dma_addr_t) (regs->cpc | (regs->cssa_u << 16));
+
+}
+
+/**
+ * 	omap_reset_dma - reset a DMA channel
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This function resets and reconfigure the given DMA channel. This is
+ * 	particularly useful after a sleep/wakeup event.
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ **/
+
+void
+omap_reset_dma(dma_regs_t * regs)
+{
+	int i;
+
+	for (i = 0; i < MAX_OMAP_DMA_CHANNELS; i++)
+		if (regs == &dma_base[i])
+			break;
+	if (i >= MAX_OMAP_DMA_CHANNELS) {
+		printk(KERN_ERR __FUNCTION__ ": bad DMA identifier\n");
+		return;
+	}
+
+	omap_clear_dma(regs);
+
+}
+
+#ifdef CONFIG_PM
+/* Drivers should call this from their PM callback function */
+
+// Bitfields so we can keep track of which
+// channels have been modified by PM.
+static int channel_auto;
+
+#ifdef TEST
+static int channel_external_auto;
+static int sleep_regs[100];
+static int wake_regs[100];
+static int sleep_request;
+static int wake_request;
+#endif
+
+// Returns 1 if DMA is busy, 0 otherwise
+static int
+dma_channel_moving_data(dmach_t channel)
+{
+	dma_regs_t *regs = &dma_base[channel];
+
+	// Check to see if enabled.
+	if (regs->ccr & DCCR_EN)
+		return 1;
+	return 0;
+}
+
+// Returns 1 if DMA is busy, 0 otherwise
+//  Called from PM code to check if we can idle.
+int
+omap_dma_busy(void)
+{
+	dmach_t channel;
+	for (channel = 0; channel < MAX_OMAP_DMA_CHANNELS; channel++) {
+		if (dma_chan[channel].in_use) {
+			if (dma_channel_moving_data(channel)) {
+				return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+#ifdef TEST
+// Returns 1 if turned off AI, 0 otherwise
+static int
+dma_disable_auto_init(dmach_t channel)
+{
+//        omap_dma_t *dma = &dma_chan[channel];
+	dma_regs_t *regs = &dma_base[channel];
+
+	if (regs->ccr & DCCR_AI) {
+		// Turn off auto init if enabled.
+		regs->ccr &= ~(DCCR_AI | DCCR_EP | DCCR_REPEAT);
+		return 1;
+	}
+	return 0;
+}
+#else
+static inline int
+dma_disable_auto_init(dmach_t channel)
+{
+	return 0;
+}
+#endif
+
+/*
+  Local Power management.
+*/
+
+static int
+dma_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
+{
+	dmach_t channel;
+	int channel_enabled = 0;
+	int try_count = 0;
+
+	DPRINTK(__FUNCTION__ ": %d\n", rqst);
+
+	if (rqst == PM_SUSPEND) {
+		for (channel = 0; channel < MAX_OMAP_DMA_CHANNELS; channel++) {
+			if (dma_chan[channel].in_use) {
+				if (dma_channel_moving_data(channel)) {
+					channel_auto |=
+					    (dma_disable_auto_init(channel) <<
+					     channel);
+					channel_enabled |= (1 << channel);
+				}
+			}
+		}
+
+		while (channel_enabled && (try_count++ < 50)) {
+			udelay(100);
+			DPRINTK(KERN_INFO __FUNCTION__ ": channel_enabled %x\n",
+				channel_enabled);
+			for (channel = 0; channel < MAX_OMAP_DMA_CHANNELS;
+			     channel++) {
+				if (channel_enabled & (1 << channel)) {
+					if (!dma_channel_moving_data(channel)) {
+						channel_enabled &=
+						    ~(1 << channel);
+					}
+				}
+			}
+		}
+		if (channel_enabled) {
+			printk(KERN_INFO
+			       "Can't suspend, DMA channel(s) busy, bitmap: 0x%x\n",
+			       channel_enabled);
+			return 1;	// tell suspend we can't stop now.
+		}
+	} else if (rqst == PM_RESUME) {
+		for (channel = 0; channel < MAX_OMAP_DMA_CHANNELS; channel++) {
+			if ((dma_chan[channel].in_use) &&
+			    (channel_auto & (1 << channel))) {
+				dma_regs_t *regs = &dma_base[channel];
+				regs->ccr |= DCCR_EN;
+				channel_auto &= ~(1 << channel);
+				DPRINTK(KERN_INFO "re-enable channel %d\n",
+					channel);
+			}
+		}
+	}
+	return 0;
+}
+#endif				// CONFIG_PM
+
+int
+omap_dma_setup(dma_device_t device, dma_direction_t direction)
+{
+
+	int i;
+
+	for (i = 0; i < MAX_OMAP_DMA_CHANNELS; i++)
+		if (device == dma_chan[i].device)
+			break;
+	if (i >= MAX_OMAP_DMA_CHANNELS || !dma_chan[i].in_use) {
+		printk(KERN_ERR __FUNCTION__ ": bad DMA identifier\n");
+		return -EINVAL;
+	}
+
+	dma_chan[i].dir = direction;
+
+	return 0;
+}
+
+static inline int
+omap_dma_channel_reserved(int channel)
+{
+	return ((1 << channel) & OMAP_DMA_RESERVED_CHANNEL_BITMAP);
+}
+
+static int __init
+omap_init_dma(void)
+{
+	int channel;
+	int status;
+	dma_regs_t *regs;
+
+	for (channel = 0; channel < MAX_OMAP_DMA_CHANNELS; channel++) {
+
+		regs = &dma_base[channel];
+
+		status = regs->csr;
+		if (omap_dma_channel_reserved(channel))
+			dma_chan[channel].in_use = 1;
+
+		//  Channels 0&6, 1&7, and 2&8 share interrupts.
+		if (channel < 6) {
+			dma_chan[channel].irq = INT_DMA_CH0_6 + channel;
+		} else {
+			dma_chan[channel].irq = INT_DMA_CH0_6 + channel - 6;
+		}
+	}
+
+#ifdef CONFIG_PM
+	pm_register(PM_SYS_DEV, PM_SYS_ARCH_SPECIFIC, dma_pm_callback);
+#endif
+
+	return 0;
+}
+
+__initcall(omap_init_dma);
+
+EXPORT_SYMBOL(omap_request_dma);
+EXPORT_SYMBOL(omap_free_dma);
+EXPORT_SYMBOL(omap_dma_setup);
+EXPORT_SYMBOL(omap_start_dma);
+EXPORT_SYMBOL(omap_get_dma_pos);
+EXPORT_SYMBOL(omap_reset_dma);
+EXPORT_SYMBOL(omap_dma_busy);
+EXPORT_SYMBOL(omap_dma_autoidle_set);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/fpga.c linux-2.4.19/arch/arm/mach-omap1510/fpga.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/fpga.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/fpga.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,73 @@
+/*
+ *  linux/arch/arm/mach-ti925/omap1510-fpga.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP1510 fpga supprt
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+// REVISIT: gdl
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/arch/fpga.h>
+
+void
+fpga_write(unsigned char val, int reg)
+{
+	outb(val, reg);
+}
+
+unsigned char
+fpga_read(int reg)
+{
+	return inb(reg);
+}
+
+void
+fpga_init(void)
+{
+
+#ifdef CONFIG_OMAP_1510P1
+	printk("OMAP1510P1 FPGA REV %d.%d BOARD REV %d\n",
+	       fpga_read(OMAP1510P1_FPGA_REV_HIGH),
+	       fpga_read(OMAP1510P1_FPGA_REV_LOW),
+	       fpga_read(OMAP1510P1_FPGA_BOARD_REV));
+
+	fpga_write(OMAP1510P1_FPGA_RESET_VALUE, OMAP1510P1_FPGA_POWER);
+#endif
+
+}
+
+EXPORT_SYMBOL(fpga_read);
+EXPORT_SYMBOL(fpga_write);
+
+  /*---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/gpio.c linux-2.4.19/arch/arm/mach-omap1510/gpio.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/gpio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/gpio.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,53 @@
+/*
+ *  linux/arch/arm/mach-omap1510/gpio.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP1510 gpio supprt
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+
+void
+gpio_init(void)
+{
+	/* REVISIT -- this shouldn't be necessary anymore due to recent
+	   changes in irq.h
+	   (gmcnutt)
+	 */
+	printk(KERN_INFO "DSPLinux: configuring GPIO\n");
+	outw(~((1 << 4) | (1 << 5) | (1 << 13)), GPIO_DIR_CONTROL_REG);
+	outw((1 << 13) | inw(GPIO_INT_CONTROL_REG), GPIO_INT_CONTROL_REG);
+	outw(~(1 << 13) & inw(GPIO_INT_MASK_REG), GPIO_INT_MASK_REG);
+}
+
+  /*---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/iram_test.c linux-2.4.19/arch/arm/mach-omap1510/iram_test.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/iram_test.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/iram_test.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,68 @@
+/*
+ * File: onchip.c
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Gordon McNutt <gmcnutt@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+static char *testBuf1, *testBuf2;
+
+static int __init
+onchip_init(void)
+{
+	testBuf1 = kmalloc(512, GFP_KERNEL | GFP_IRAM);
+	if (!testBuf1)
+		return -ENOMEM;
+	printk("IRAM: virt=0x%x, phys=0x%x\n", (int) testBuf1,
+	       (int) virt_to_phys(testBuf1));
+
+	testBuf2 = kmalloc(512, GFP_KERNEL);
+	if (!testBuf2) {
+		kfree(testBuf1);
+		return -ENOMEM;
+	}
+	printk("Offchip: virt=0x%x, phys=0x%x\n", (int) testBuf2,
+	       (int) virt_to_phys(testBuf2));
+
+	return 0;
+}
+
+static void __exit
+onchip_exit(void)
+{
+	kfree(testBuf1);
+	kfree(testBuf2);
+}
+
+module_init(onchip_init);
+module_exit(onchip_exit);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/irq.c linux-2.4.19/arch/arm/mach-omap1510/irq.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/irq.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/irq.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,525 @@
+/*
+ *  irq.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP1510 irq interface
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/irq.h>
+
+#include <asm/io.h>
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...)
+#  define ENTRY()
+#endif
+
+/*
+ *      FPGA irq routines
+ */
+/* The FPGA multiplexes the interrupts from several peripherals into one
+   interrupt line that goes to GPIO pin 14. We treat the FPGA like another
+   level of interrupt handling.
+   (gmcnutt)
+ */
+#ifdef PARANOIA
+#define FPGA_CHECK_IRQ(irq) \
+        if ((irq < IH_FPGA_BASE) || (irq > (IH_FPGA_BASE + 16))) \
+                BUG();
+#else
+#define FPGA_CHECK_IRQ(irq)
+#endif
+
+void
+fpga_mask_irq(unsigned int irq)
+{
+	FPGA_CHECK_IRQ(irq);
+
+	irq -= IH_FPGA_BASE;
+
+	if (irq < 8)
+		outb((inb(OMAP1510P1_FPGA_IMR_LO) & ~(1 << irq)),
+		     OMAP1510P1_FPGA_IMR_LO);
+	else
+		outb((inb(OMAP1510P1_FPGA_IMR_HI) & ~(1 << (irq - 8))),
+		     OMAP1510P1_FPGA_IMR_HI);
+}
+
+void
+fpga_ack_irq(unsigned int irq)
+{
+	// Subtle. The GPIO level is edge-triggered, but the FPGA bits are
+	// level-sensitive. Consider:
+	// 1. ethernet chip asserts its irq to the fpga
+	// 2. fpga asserts its irq to the gpio, which latches it
+	// 3. ethernet irq handler runs
+	// 4. ethernet chip deasserts its irq to the fpga
+	// 5. fpga deasserts to gpio (but it's still latched)
+	// 6. do_IRQ finds gpio irq still asserted, so calls gpio_fixup_irq
+	// 7. which calls fpga_fixup_irq
+	// 8. which finds nothing asserted so it returns
+	// 9. just before gpio_fixup_irq() acks the latched irq (which would
+	//    clear it), the ethernet chip asserts its irq line
+	// 10. gpio_fixup_irq acks the fpga bit and clears it, and so we miss
+	//    the new ethernet interrupt
+	//
+	// To eliminate this race we must eliminate the time delay between
+	// fpga_fixup_irq and gpio_fixup_irq. The way to do that is to ack
+	// the GPIO pin *here*, after we've correctly identified the interrupt,
+	// and before we've called its handler (see do_IRQ() for full context).
+	//
+	// However, if more than one irq into the FPGA is asserted then we 
+	// cannot clear the GPIO irq pin or we will lose the one we haven't
+	// started handling yet. In that case we need to leave the GPIO irq
+	// asserted and clear it the next time through when we process the
+	// last one.
+	//
+
+	int stat, count = 0;
+
+	// Get the unmasked irqs asserted to the fpga.
+	stat =
+	    (inb(OMAP1510P1_FPGA_ISR_HI) & inb(OMAP1510P1_FPGA_IMR_HI)) << 8 |
+	    (inb(OMAP1510P1_FPGA_ISR_LO) & inb(OMAP1510P1_FPGA_IMR_LO));
+
+	// Check if more than one is set. If so then do *not* ack the irq
+	// asserted by the fpga to the gpio.
+	while (stat) {
+		if (stat & 1) {
+			if (++count > 1)
+				return;
+		}
+		stat = stat >> 1;
+	}
+
+	// If we got here then it's safe to ack at the gpio level.
+	outw((inw(GPIO_INT_STATUS_REG) | (1 << (INT_FPGA - IH_GPIO_BASE))),
+	     GPIO_INT_STATUS_REG);
+
+}
+
+void
+fpga_unmask_irq(unsigned int irq)
+{
+	FPGA_CHECK_IRQ(irq);
+
+	irq -= IH_FPGA_BASE;
+
+	if (irq < 8)
+		outb((inb(OMAP1510P1_FPGA_IMR_LO) | (1 << irq)),
+		     OMAP1510P1_FPGA_IMR_LO);
+	else
+		outb((inb(OMAP1510P1_FPGA_IMR_HI) | (1 << (irq - 8))),
+		     OMAP1510P1_FPGA_IMR_HI);
+}
+
+void
+fpga_mask_ack_irq(unsigned int irq)
+{
+	FPGA_CHECK_IRQ(irq);
+
+	fpga_mask_irq(irq);
+	fpga_ack_irq(irq);
+}
+
+void
+fpga_init_irq(void)
+{
+	int i;
+
+	outb(0, OMAP1510P1_FPGA_IMR_LO);
+	outb(0, OMAP1510P1_FPGA_IMR_HI);
+
+	/* I allow probing of the FPGA interrupts for the ethernet driver. This
+	   means one less custom modification to the stock smc9194 driver. Probing
+	   means that we'll briefly unmask probable irqs and try to force a device
+	   to cause an interrupt. Spurious interrupts are automatically masked 
+	   back out, so the danger should be pretty low... (gjm)
+	 */
+	for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + 16); i++) {
+		irq_desc[i].valid = 1;
+		irq_desc[i].probe_ok = 1;
+		irq_desc[i].mask_ack = fpga_mask_ack_irq;
+		irq_desc[i].mask = fpga_mask_irq;
+		irq_desc[i].unmask = fpga_unmask_irq;
+	}
+
+}
+int
+fpga_fixup_irq(int irq)
+{
+	int stat =
+	    (inb(OMAP1510P1_FPGA_ISR_HI) & inb(OMAP1510P1_FPGA_IMR_HI)) << 8 |
+	    (inb(OMAP1510P1_FPGA_ISR_LO) & inb(OMAP1510P1_FPGA_IMR_LO));
+	if (!stat)
+		return irq;
+
+	irq = IH_FPGA_BASE;
+
+	while (!(stat & 1)) {
+		stat = stat >> 1;
+		irq++;
+	}
+
+	return irq;
+
+}
+
+/*
+ *      GPIO irq routines
+ */
+/* The GPIO multiplexes the interrupts from all of its pins into one irq. We
+   treat GPIO like another level of interrupt handlers.
+   (gmcnutt)
+ */
+#ifdef PARANOIA
+#define GPIO_CHECK_IRQ(irq) \
+        if ((irq < IH_GPIO_BASE) || (irq > (IH_GPIO_BASE + 16))) \
+                BUG();
+#else
+#define GPIO_CHECK_IRQ(irq)
+#endif
+void
+gpio_mask_irq(unsigned int irq)
+{
+	GPIO_CHECK_IRQ(irq);
+
+	/* Hack -- don't mask out FPGA */
+	if (irq == INT_FPGA)
+		return;
+
+	irq -= IH_GPIO_BASE;
+	/* Set the bit to disable the interrupt */
+	outw((inw(GPIO_INT_MASK_REG) | (1 << irq)), GPIO_INT_MASK_REG);
+}
+
+void
+gpio_ack_irq(unsigned int irq)
+{
+	GPIO_CHECK_IRQ(irq);
+	/* Set the bit to clear the status  */
+	outw((inw(GPIO_INT_STATUS_REG) | (1 << irq)), GPIO_INT_STATUS_REG);
+}
+
+void
+gpio_unmask_irq(unsigned int irq)
+{
+	GPIO_CHECK_IRQ(irq);
+	irq -= IH_GPIO_BASE;
+	/* Clear the bit to enable the interrupt */
+	outw((inw(GPIO_INT_MASK_REG) & ~(1 << irq)), GPIO_INT_MASK_REG);	// ok!
+}
+
+void
+gpio_mask_ack_irq(unsigned int irq)
+{
+	GPIO_CHECK_IRQ(irq);
+	gpio_mask_irq(irq);
+	gpio_ack_irq(irq);
+}
+
+void
+gpio_init_irq(void)
+{
+	int i;
+
+	outw(0xffff, GPIO_INT_MASK_REG);
+	outw(0xffff, GPIO_INT_STATUS_REG);
+
+	for (i = IH_GPIO_BASE; i < (IH_GPIO_BASE + 16); i++) {
+		irq_desc[i].valid = 1;
+		irq_desc[i].probe_ok = 0;
+		irq_desc[i].mask_ack = gpio_mask_ack_irq;
+		irq_desc[i].mask = gpio_mask_irq;
+		irq_desc[i].unmask = gpio_unmask_irq;
+	}
+
+	fpga_init_irq();
+
+	/* The FPGA interrupt line comes in on pin 13. Claim this pin for the
+	   ARM. */
+	outw((inb(GPIO_PIN_CONTROL_REG) | (1 << 13)), GPIO_PIN_CONTROL_REG);
+
+	/* Configure it as an input pin. */
+	outw((inw(GPIO_DIR_CONTROL_REG) | (1 << 13)), GPIO_DIR_CONTROL_REG);
+
+	/* Configure it to fire on low-to-high */
+	outw((inw(GPIO_INT_CONTROL_REG) | (1 << 13)), GPIO_INT_CONTROL_REG);
+
+	/* Always leave the FPGA pin interrupt enabled. Interrupts coming in 
+	   from the FPGA peripherals should be masked out in the FPGA 
+	   registers, not here. */
+	gpio_unmask_irq(INT_FPGA);
+
+}
+
+int
+gpio_fixup_irq(int irq)
+{
+	/* Invert the mask because 0 = enabled */
+	int stat = inw(GPIO_INT_STATUS_REG) & ~(inw(GPIO_INT_MASK_REG));
+
+	if (!stat)
+		return irq;
+
+	irq = IH_GPIO_BASE;
+
+	while (!(stat & 1)) {
+		stat = stat >> 1;
+		irq++;
+	}
+
+	if (irq == INT_FPGA)
+		irq = fpga_fixup_irq(irq);
+
+	return irq;
+}
+
+/*
+ *      Standard irq routines
+ */
+#ifdef PARANOIA
+#define CHECK_IRQ(irq) \
+        if ((irq < 0) || (irq > (IH2_BASE + 32))) \
+                BUG();
+#else
+#define CHECK_IRQ(irq)
+#endif
+
+inline void
+write_ih(int level, int reg, int value)
+{
+//        printk("write addr: %8.8x value: %x\n", (IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) +   (reg))), value);
+	outl(value,
+	     (IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) + (reg))));
+}
+
+inline unsigned long
+read_ih(int level, int reg)
+{
+	unsigned long value =
+	    inl((IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) + (reg))));
+	//      printk("read  addr: %8.8x value %x\n", 
+	//       IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) +
+	//                  (reg)), value);
+	return value;
+}
+
+inline int
+get_level(int irq)
+{
+	return (((irq) < IH2_BASE) ? 0 : 1);
+}
+
+inline int
+get_irq_num(int irq)
+{
+	return (((irq) < IH2_BASE) ? irq : irq - IH2_BASE);
+}
+
+void
+mask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	int level = get_level(irq);
+	int irq_num = get_irq_num(irq);
+
+	CHECK_IRQ(irq);
+
+	/* Hack -- don't mask out GPIO */
+	if (irq == INT_GPIO)
+		return;
+
+	if (irq != TIMER_IRQ)
+		ENTRY();
+	if (irq != TIMER_IRQ)
+		DBG("irq: %d\n", irq);
+
+	mask = read_ih(level, IRQ_MIR);
+	mask = mask | (1 << irq_num);
+
+	if (irq != TIMER_IRQ)
+		DBG(" mask: %8.8x\n", (int) mask);
+
+	write_ih(level, IRQ_MIR, mask);	// mask the interrupt
+}
+
+void
+ack_irq(unsigned int irq)
+{
+	int level = get_level(irq);
+
+	CHECK_IRQ(irq);
+
+	if (irq != TIMER_IRQ)
+		ENTRY();
+
+	/* __DO NOT__ try to ack level-sensitive interrupts by clearing their 
+	   bits in the ITR or you will drop timer interrupts.
+	   (gjm)
+	 */
+
+	do {
+		write_ih(level, IRQ_CONTROL_REG, 0x3);
+	} while (level--);
+
+}
+
+void
+unmask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	int level = get_level(irq);
+	int irq_num = get_irq_num(irq);
+
+	CHECK_IRQ(irq);
+
+	if (irq != TIMER_IRQ)
+		ENTRY();
+	if (irq != TIMER_IRQ)
+		DBG("irq %d\n", irq);
+
+	mask = read_ih(level, IRQ_MIR);
+	if (irq != TIMER_IRQ)
+		DBG("before mask: %8.8x\n", (int) mask);
+	mask &= ~((1 << irq_num));
+	if (irq != TIMER_IRQ)
+		DBG("after mask : %8.8x\n", (int) mask);
+	write_ih(level, IRQ_MIR, mask);
+}
+
+void
+mask_ack_irq(unsigned int irq)
+{
+
+	CHECK_IRQ(irq);
+
+	if (irq != TIMER_IRQ)
+		ENTRY();
+	mask_irq(irq);
+	ack_irq(irq);
+}
+
+#if 0				/* dead code? */
+void
+ack_level_irq(int irq)
+{
+	if (irq != TIMER_IRQ)
+		ENTRY();
+	mask_ack_irq(irq);
+	unmask_irq(irq);
+}
+#endif
+void
+irq_priority(int irq, int fiq, int priority, int trigger)
+{
+	int level, irq_num;
+	unsigned long reg_value, reg_addr;
+
+	CHECK_IRQ(irq);
+
+	level = get_level(irq);
+	irq_num = get_irq_num(irq);
+        // FIQ only available on level 0 interrupts
+        fiq = level ? 0 : (fiq & 0x1);
+	reg_value = (fiq) | ((priority & 0xf) << 3) |
+	    ((trigger & 0x1) << 1);
+	reg_addr = (IRQ_ILR0 + irq_num * 0x4);
+	write_ih(level, reg_addr, reg_value);
+}
+
+void
+irq_init_irq(void)
+{
+	int i;
+	uint trigger;
+	write_ih(0, IRQ_MIR, ~0x0);	// mask all interrupts
+	write_ih(0, IRQ_ITR, 0x0);	// clear all interrupts
+	write_ih(1, IRQ_MIR, ~0x0);	// mask all interrupts
+	write_ih(1, IRQ_ITR, 0x0);	// clear all interrupts
+	for (i = 0; i < IH_GPIO_BASE; i++) {
+		irq_desc[i].valid = 1;
+		irq_desc[i].probe_ok = 0;
+		irq_desc[i].mask_ack = mask_ack_irq;
+		irq_desc[i].mask = mask_irq;
+		irq_desc[i].unmask = unmask_irq;
+
+		DBG("initing irq %d\n", i);
+
+		trigger = ((i < 32) ? (0xb3fe3fff >> i) :
+			   (0xf7bfffed >> (i - 32))) & 1;
+
+		irq_priority(i, 0, 0, trigger);
+	}
+
+	gpio_init_irq();
+
+	unmask_irq(INT_GPIO);
+	unmask_irq(INT_IH2_IRQ);
+}
+
+int
+fixup_irq(unsigned int irq)
+{
+	int level = 0;
+
+	irq = read_ih(level, IRQ_SIR_FIQ);
+	if (!irq) {
+		irq = read_ih(level, IRQ_SIR_IRQ);
+		if (irq == INT_IH2_IRQ) {
+			level = 1;
+			irq = read_ih(level, IRQ_SIR_IRQ);
+		}
+	}
+
+	irq += (level ? IH2_BASE : 0);
+
+	if (irq == INT_GPIO)
+		irq = gpio_fixup_irq(irq);
+
+	return irq;
+}
+
+/*---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/leds.c linux-2.4.19/arch/arm/mach-omap1510/leds.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/leds.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/leds.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,130 @@
+/*
+ *  linux/arch/arm/mach-omap1510/leds.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP1510 7-line LED driver
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+
+static inline void
+led_write(unsigned long x)
+{
+	outb(x, OMAP1510P1_FPGA_LED_DIGIT);
+}
+
+static unsigned char led_array[] = {
+	0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0, 0x00, 0x20, 0x10, 0x06,
+	0x8c, 0x4e, 0x42, 0x0c, 0x1c, 0x18
+};
+
+static inline int
+heartbeat(void)
+{
+	int ret = 2;
+	static unsigned cnt = 0, period = 0, dist = 0;
+	if (cnt == 0 || cnt == dist)
+		ret = 0;
+	else if (cnt == 7 || cnt == dist + 7)
+		ret = 1;
+	if (++cnt > period) {
+		cnt = 0;
+		/* The hyperbolic function below modifies the heartbeat period
+		 * length in dependency of the current (5min) load. It goes
+		 * through the points f(0)=126, f(1)=86, f(5)=51,
+		 * f(inf)->30. */
+		period =
+		    ((672 << FSHIFT) / (5 * avenrun[0] + (7 << FSHIFT))) + 30;
+		dist = period / 4;
+	}
+	return ret;
+}
+
+static void
+omap1510_leds_event(led_event_t ledevt)
+{
+	static int state = 0;
+	static int led = 0xff;
+	unsigned long flags;
+	int hr;
+
+#define LOAD_INT(x) ((x) >> FSHIFT)
+#define LOAD_FRAC(x) LOAD_INT(((x) & (FIXED_1-1)) * 4)
+
+	local_irq_save(flags);
+
+	if (!(state++ & 0xff)) {
+		int load = avenrun[0] + (FIXED_1 / 200);
+		led = LOAD_INT(load) * 4 + LOAD_FRAC(load);
+		if (led > 9)
+			led = 9;
+		led = led_array[led];
+	}
+	hr = heartbeat();
+	if (hr < 2)
+		led |= hr & 0x1;
+
+	switch (ledevt) {
+	case led_idle_start:
+		led_write(led);
+		break;
+
+	case led_idle_end:
+		led_write(0xff);
+		break;
+
+	case led_timer:
+		led_write(led);
+		break;
+
+	default:
+		break;
+	}
+	local_irq_restore(flags);
+}
+
+static int __init
+leds_init(void)
+{
+	leds_event = omap1510_leds_event;
+	return 0;
+}
+
+__initcall(leds_init);
+/* ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/Makefile linux-2.4.19/arch/arm/mach-omap1510/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/Makefile	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/Makefile	2003-01-10 12:16:02.000000000 +0200
@@ -0,0 +1,53 @@
+#
+# Makefile for the linux kernel.
+#
+# Copyright 2001 RidgeRun, Inc (glonnon@ridgerun.com) info@ridgerun.com
+# http://www.ridgerun.com
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET		:= omap1510.o
+
+export-objs		:= irq.o arch.o
+export-objs		+= timer.o
+export-objs		+= fpga.o
+export-objs		+= dma-omap.o
+# export-objs		+= copy_page-dma.o # use standard copy_page for now
+export-objs		+= ck.o
+
+# Object file lists.
+obj-y 			:= time.o gpio.o arch.o mm.o irq.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+obj-y				+= fpga.o
+obj-y				+= dma-omap.o
+# copy_page-dma.o needs to come after dma-omap.o, since they
+# both have init calls and copy_page depends on the DMA.
+# obj-y				+= copy_page-dma.o
+obj-$(CONFIG_LEDS)		+= leds.o
+obj-$(CONFIG_OMAP_TIMER)	+= timer.o
+obj-$(CONFIG_OMAP_TIMER_PROC)	+= timer_proc.o
+obj-$(CONFIG_PM)		+= ck.o
+obj-$(CONFIG_OMAP_PWT)		+= pwt.o
+obj-$(CONFIG_OMAP1510_PM)	+= pm.o sleep.o  apm.o
+
+
+# Files that are both resident and modular; remove from modular.
+
+obj-m		:= $(filter-out $(obj-y), $(obj-m))
+
+# Translate to Rules.make lists.
+
+O_OBJS		:= $(filter-out $(export-objs), $(obj-y))
+OX_OBJS 	:= $(filter	$(export-objs), $(obj-y))
+M_OBJS		:= $(sort $(filter-out $(export-objs), $(obj-m)))
+MX_OBJS 	:= $(sort $(filter     $(export-objs), $(obj-m)))
+
+include $(TOPDIR)/Rules.make
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/mm.c linux-2.4.19/arch/arm/mach-omap1510/mm.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/mm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/mm.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,103 @@
+/*
+ *  linux/arch/arm/mach-omap1510/mm.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   maps in the hardware correctly
+ *
+ * Copyright (C) 2000 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/config.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/arch/sizes.h>
+#include <asm/mach/map.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Map the various IO regions onto 0xExxx.xxxx.  For
+ * example, SC_BASE (0x1100.0000) gets mapped
+ * to 0xF110.0000
+ */
+
+#define MAP_DESC(base,start,size) { base,start,size,DOMAIN_IO,0,1,0,0 }
+
+static struct map_desc io_desc[] __initdata = {
+	MAP_DESC(IO_BASE,
+		 IO_START,
+		 IO_SIZE),
+	MAP_DESC(OMAP1510P1_FPGA_BASE,
+		 OMAP1510P1_FPGA_START,
+		 OMAP1510P1_FPGA_SIZE),
+	MAP_DESC(OMAP1510_GPIO_BASE,
+		 OMAP1510_GPIO_START,
+		 OMAP1510_GPIO_SIZE),
+	MAP_DESC(OMAP1510_MCBSP1_BASE,
+		 OMAP1510_MCBSP1_START,
+		 OMAP1510_MCBSP1_SIZE),
+	MAP_DESC(OMAP1510_MCBSP3_BASE,
+		 OMAP1510_MCBSP3_START,
+		 OMAP1510_MCBSP3_SIZE),
+	MAP_DESC(OMAP1510_DSP_BASE,
+		 OMAP1510_DSP_START,
+		 OMAP1510_DSP_SIZE),
+	MAP_DESC(OMAP1510_DSPREG_BASE,
+		 OMAP1510_DSPREG_START,
+		 OMAP1510_DSPREG_SIZE),
+	MAP_DESC(OMAP1510_SRAM_BASE,
+		 OMAP1510_SRAM_START,
+		 OMAP1510_SRAM_SIZE),
+	MAP_DESC(OMAP_FLASH_0_BASE,
+		 OMAP_FLASH_0_START,
+		 OMAP_FLASH_0_SIZE),
+#if defined(CONFIG_OMAP_INNOVATOR)
+	MAP_DESC(OMAP_FLASH_1_BASE,
+		 OMAP_FLASH_1_START,
+		 OMAP_FLASH_1_SIZE),
+#endif
+	LAST_DESC
+};
+extern void board_init(void);
+extern void fpga_init(void);
+extern void gpio_init(void);
+
+void __init
+omap1510_map_io(void)
+{
+	iotable_init(io_desc);
+	board_init();
+	fpga_init();
+	gpio_init();
+}
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/pm.c linux-2.4.19/arch/arm/mach-omap1510/pm.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/pm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/pm.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,436 @@
+/*
+ * OMAP1510 Power Management Routines
+ *
+ * Original code for the SA11x0:
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * Modified for the PXA250 by Nicolas Pitre:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Modified for the OMAP1510 by David Singleton:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>   
+#include <linux/sysctl.h>
+#include <linux/errno.h>
+#include <linux/serial_reg.h>
+#include <linux/delay.h>
+
+#include <asm/memory.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+#include <asm/arch/innovator.h>
+#include <asm/arch/hardware.h>
+#include <asm/pm.h>
+
+
+static unsigned short arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
+static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
+static unsigned int mpui_sleep_save[MPUI_SLEEP_SAVE_SIZE];
+
+void omap_pm_suspend(void)
+{
+	unsigned short mask16 = 0;
+	unsigned long mask32 = 0;
+	int (*func_ptr)(void);
+	unsigned long *addr;
+	int i;
+
+	/*
+	 * Step 0: turn off interrupts
+	 */
+
+	cli();
+	clf();
+	MPUI_SAVE(IRQ_MIR1);
+	MPUI_SAVE(IRQ_MIR2);
+
+	/*
+	 * The omap is a strange/beautiful device.  The caches, memory
+	 * and regsigter state are preserved across power saves.
+	 * We have to save and restore very little register state to
+	 * idle the omap.
+	 */
+
+	/*
+	 * Save MPUI control registers for wake up.
+	 */
+
+	MPUI_SAVE(MPUI_CTRL_REG);
+	MPUI_SAVE(MPUI_DSP_BOOT_CONFIG);
+	MPUI_SAVE(MPUI_DSP_API_CONFIG);
+	MPUI_SAVE(EMIFS_CONFIG_REG);
+	MPUI_SAVE(EMIFF_SDRAM_CONFIG);
+
+	/*
+	 * Sleep algorithm:
+	 *
+	 * if (DSP_IS_NOT_RUNNING) {
+	 * 	a) Enable DSP/MPUI clocks
+	 *	b) setup default MPUI config
+	 *	c) set boot mode for DSP 0x2
+	 *	d) disable SARAM access by ARM
+	 *	e) release reset on DSP (boot DSP)
+	 *	f) wait for DSP to idle bit 6 of ARM_SYSST = DSP_IDLE (0x0020)
+	 * } 
+	 * if (DSP_IS_IDLE) {
+	 *	if (LCD_IS_ON) {
+	 *		leave LCD clock enabled EN_LCDCK in ARM_IDLECT2
+	 *		ARM_IDLE_REQUEST &= ~EN_LCDCK
+	 *	}
+	 * }
+	 * call omap1510_cpu_suspend which will:
+	 * put ARM/LCD/TC/whatever clocks into the state you want them
+	 * and then put SDRAM into self refresh and idle the ARM and its 
+	 * unused peripherals into sleep using the ARM_IDLE bits.
+	 *	
+	 * Save ARM control registers
+	 */
+
+	ARM_SAVE(ARM_CKCTL);
+	ARM_SAVE(ARM_IDLECT1);
+	ARM_SAVE(ARM_IDLECT2);
+	ARM_SAVE(ARM_EWUPCT);
+	ARM_SAVE(ARM_RSTCT1);
+	ARM_SAVE(ARM_RSTCT2);
+	ARM_SAVE(ARM_SYSST);
+	ULPD_SAVE(ULPD_CLOCK_CTRL_REG);
+	ULPD_SAVE(ULPD_STATUS_REQ_REG);
+
+	mask16 = *ARM_RSTCT1;
+	if (mask16 & DSP_ENABLE) {
+
+		mask16 = *ARM_SYSST;
+		/*
+		 * DSP is not running, do steps a - f.
+		 */
+		mask16 = (1<<EN_DSPCK);				/* a */
+		*ARM_CKCTL = mask16;
+		mask16 = (1<<EN_APICK);
+		*ARM_IDLECT2 = mask16;
+
+		mask16 = 0x4;
+		*ARM_RSTCT1 = mask16;				/* b */
+		mask32 = DEFAULT_MPUI_CONFIG;
+		*MPUI_CTRL_REG = mask32;
+
+		mask32 = 0x0002;
+		*MPUI_DSP_BOOT_CONFIG = mask32;			/* c*/
+
+		mask32 = 0x0;
+		*MPUI_DSP_API_CONFIG = mask32;			/* d */
+
+		mask16 = DSP_RESET;
+		*ARM_RSTCT1 = mask16;				/* e */
+		mask16 = DSP_ENABLE;
+		*ARM_RSTCT1 = mask16;
+
+		mdelay(DSP_IDLE_DELAY);
+		for (i = 0; i < SUFFICIENT_DSP_RESET_TIME; i++) {
+			mask16 = (unsigned short)*ARM_SYSST;  /* f */
+			if (mask16 & DSP_IDLE) {
+				break;
+			}
+		}
+	}
+
+	mask16 = *ARM_SYSST;
+	if (mask16 & DSP_IDLE) {
+		/*
+		 * enable DSP clock to be shut off in idle
+		 */
+
+		mask16 = *ARM_CKCTL;
+		mask16 |= ~(DSP_RESET);
+		*ARM_CKCTL = mask16;
+	}
+
+	/*
+	 * enable arm xor clock and release peripheral from reset by
+	 * writing 1 to PER_EN bit in ARM_RSTCT2, this is required
+	 * for COM UART configuration to use UART2 to wake up.
+	 */
+	 
+	mask16 = *ARM_IDLECT2;
+	mask16 |= ENABLE_XORCLK;
+	*ARM_IDLECT2 = mask16;
+
+	*ARM_RSTCT2 = 0x1;
+
+	mask16 = MODEM_32K_EN;
+	*ULPD_CLOCK_CTRL_REG = mask16;
+
+	/*
+	 * Turn off all interrupts except UART1, and UART2
+	 * Leave 2nd level cascae enabled, but disable all other
+	 * level 1 interrupts.
+	 */
+
+	addr = (void *)(OMAP_IH1_BASE + IRQ_MIR);
+	mask32 = *addr;
+	mask32 = ~3;
+	*addr = mask32;
+
+	addr = (void *)(OMAP_IH2_BASE + IRQ_MIR);
+	mask32 = *addr;
+	mask32 = ~((1<<14) | (1<<15));
+	*addr = mask32;
+
+	/*
+	 * Save UART and ethernet state so we have a working console and
+	 * ethernet after power save. (or is that register state preserved too?)
+	 */
+
+
+	/*
+	 * set bit 2,3 in the RSTCT1 so we can program the EMIF registers
+	 * and reset the DSP
+	 */ 
+	mask16 = *ARM_RSTCT1;
+	mask16 |= 0x6;
+	*ARM_RSTCT1 = mask16; 
+
+	/*
+	 * Since the omap1510_cpu_suspend routine has been copied to
+	 * SRAM, we'll do an indirect procedure call to it and pass the
+	 * contents of arm_idlect1 and arm_idlect2 so it can restore
+	 * them when it wakes up and it will return to here:
+	 */
+
+	func_ptr = (void *)(OMAP1510_SRAM_API_SUSPEND);
+        func_ptr();
+
+	/*
+	 * restore UART and ethernet state, base functionality
+	 */
+
+	/*
+	 * restore ARM state, except idlect1/2 which cpu_suspend did
+	 */
+
+	ARM_RESTORE(ARM_CKCTL);
+	ARM_RESTORE(ARM_EWUPCT);
+	ARM_RESTORE(ARM_RSTCT1);
+	ARM_RESTORE(ARM_RSTCT2);
+
+	/*
+	 * Restore MPUI control registers.
+	 */
+
+	MPUI_RESTORE(MPUI_CTRL_REG);
+	MPUI_RESTORE(MPUI_DSP_BOOT_CONFIG);
+	MPUI_RESTORE(MPUI_DSP_API_CONFIG);
+	MPUI_RESTORE(EMIFF_SDRAM_CONFIG);
+	MPUI_RESTORE(EMIFS_CONFIG_REG);
+	MPUI_RESTORE(IRQ_MIR1);
+	MPUI_RESTORE(IRQ_MIR2);
+
+	sti();
+	stf();
+
+	return;
+}
+
+#ifdef CONFIG_PROC_FS
+static int g_read_completed;
+/*
+ * Writing to /proc/pm puts the CPU in sleep mode
+ */
+static ssize_t
+omap_pm_write_proc(struct file * file, const char * buf, size_t count,
+    loff_t *ppos)
+{
+	int rc;
+	rc = pm_send_all(PM_SUSPEND, (void *)3);
+
+	if (rc == 0) {
+		omap_pm_suspend();
+
+		pm_send_all(PM_RESUME, (void *)0);
+	}
+	return count;
+}     
+
+
+static int omap_pm_read_proc(
+	char *page_buffer,
+	char **my_first_byte,
+	off_t virtual_start,
+	int length,
+	int *eof,
+	void *data)
+{
+	int my_buffer_offset = 0;
+	char * const my_base = page_buffer;
+
+	ARM_SAVE(ARM_CKCTL);
+	ARM_SAVE(ARM_IDLECT1);
+	ARM_SAVE(ARM_IDLECT2);
+	ARM_SAVE(ARM_EWUPCT);
+	ARM_SAVE(ARM_RSTCT1);
+	ARM_SAVE(ARM_RSTCT2);
+	ARM_SAVE(ARM_SYSST);
+
+	ULPD_SAVE(ULPD_IT_STATUS_REG);
+	ULPD_SAVE(ULPD_CLOCK_CTRL_REG);
+	ULPD_SAVE(ULPD_SOFT_REQ_REG);
+	ULPD_SAVE(ULPD_STATUS_REQ_REG);
+	ULPD_SAVE(ULPD_DPLL_CTRL_REG);
+	ULPD_SAVE(ULPD_POWER_CTRL_REG);
+
+	MPUI_SAVE(MPUI_CTRL_REG);
+	MPUI_SAVE(MPUI_DSP_STATUS_REG);
+	MPUI_SAVE(MPUI_DSP_BOOT_CONFIG);
+	MPUI_SAVE(MPUI_DSP_API_CONFIG);
+	MPUI_SAVE(EMIFF_SDRAM_CONFIG);
+	MPUI_SAVE(EMIFS_CONFIG_REG);
+
+	if (virtual_start == 0) {
+		g_read_completed = 0;
+
+		my_buffer_offset += sprintf(my_base + my_buffer_offset,
+		   "ARM_CKCTL:            0x%-4x     (0x%p)\n"
+		   "ARM_IDLECT1:          0x%-4x     (0x%p)\n"
+		   "ARM_IDLECT2:          0x%-4x     (0x%p)\n"
+		   "ARM_EWUPCT:           0x%-4x     (0x%p)\n"
+		   "ARM_RSTCT1:           0x%-4x     (0x%p)\n"
+		   "ARM_RSTCT2:           0x%-4x     (0x%p)\n"
+		   "ARM_SYSST:            0x%-4x     (0x%p)\n"
+		   "ULPD_IT_STATUS_REG:   0x%-4x     (0x%p)\n"
+		   "ULPD_CLOCK_CTRL_REG:  0x%-4x     (0x%p)\n"
+		   "ULPD_SOFT_REQ_REG:    0x%-4x     (0x%p)\n"
+		   "ULPD_DPLL_CTRL_REG:   0x%-4x     (0x%p)\n"
+		   "ULPD_STATUS_REQ_REG:  0x%-4x     (0x%p)\n"
+		   "ULPD_POWER_CTRL_REG:  0x%-4x     (0x%p)\n"
+		   "MPUI_CTRL_REG         0x%-8x (0x%p)\n"
+		   "MPUI_DSP_STATUS_REG:  0x%-8x (0x%p)\n"
+		   "MPUI_DSP_BOOT_CONFIG: 0x%-8x (0x%p)\n"
+		   "MPUI_DSP_API_CONFIG:  0x%-8x (0x%p)\n" 
+		   "MPUI_SDRAM_CONFIG:    0x%-8x (0x%p)\n" 
+		   "MPUI_EMIFS_CONFIG:    0x%-8x (0x%p)\n", 
+		   ARM_SHOW(ARM_CKCTL), ARM_CKCTL, 
+		   ARM_SHOW(ARM_IDLECT1), ARM_IDLECT1, 
+		   ARM_SHOW(ARM_IDLECT2), ARM_IDLECT2, 
+		   ARM_SHOW(ARM_EWUPCT), ARM_EWUPCT, 
+		   ARM_SHOW(ARM_RSTCT1), ARM_RSTCT1, 
+		   ARM_SHOW(ARM_RSTCT2), ARM_RSTCT2,
+		   ARM_SHOW(ARM_SYSST), ARM_SYSST,
+		   ULPD_SHOW(ULPD_IT_STATUS_REG), ULPD_IT_STATUS_REG,
+		   ULPD_SHOW(ULPD_CLOCK_CTRL_REG), ULPD_CLOCK_CTRL_REG,
+		   ULPD_SHOW(ULPD_SOFT_REQ_REG), ULPD_SOFT_REQ_REG,
+		   ULPD_SHOW(ULPD_DPLL_CTRL_REG), ULPD_DPLL_CTRL_REG,
+		   ULPD_SHOW(ULPD_STATUS_REQ_REG), ULPD_STATUS_REQ_REG,
+		   ULPD_SHOW(ULPD_POWER_CTRL_REG), ULPD_POWER_CTRL_REG,
+		   MPUI_SHOW(MPUI_CTRL_REG), MPUI_CTRL_REG,
+		   MPUI_SHOW(MPUI_DSP_STATUS_REG), MPUI_DSP_STATUS_REG,
+		   MPUI_SHOW(MPUI_DSP_BOOT_CONFIG), MPUI_DSP_BOOT_CONFIG,
+		   MPUI_SHOW(MPUI_DSP_API_CONFIG), MPUI_DSP_API_CONFIG,
+		   MPUI_SHOW(EMIFF_SDRAM_CONFIG), EMIFF_SDRAM_CONFIG,
+		   MPUI_SHOW(EMIFS_CONFIG_REG), EMIFS_CONFIG_REG);
+		g_read_completed++;
+	} else if (g_read_completed >= 1) {
+		 *eof = 1;
+		 return 0;
+	}
+	g_read_completed++;
+
+	*my_first_byte = page_buffer;
+	return  my_buffer_offset;
+}
+
+int __init
+omap_pm_init(void)
+{
+	struct proc_dir_entry *entry;
+	int suspend_size = 284;
+
+	printk("Power Management for the OMAP1510 is initialized\n");
+	entry = create_proc_read_entry("pm", S_IWUSR | S_IRUGO, NULL,
+	    omap_pm_read_proc, 0);
+	if (entry) {
+		entry->write_proc = (write_proc_t *)omap_pm_write_proc;
+	}
+
+	/*
+	 * We copy the assembler sleep/wakeup routines to SRAM.
+	 * These routines need to be in SRAM as that's the only
+	 * memory the MPU can see when it wakes up.
+	 */
+
+	memcpy((void *)OMAP1510_SRAM_IDLE_SUSPEND, omap1510_idle_loop_suspend,
+	    suspend_size);
+	memcpy((void *)OMAP1510_SRAM_API_SUSPEND, omap1510_cpu_suspend,
+	    suspend_size);
+	return 0;
+}
+__initcall(omap_pm_init);
+
+#endif /* CONFIG_PROC_FS */
+
+#ifdef CONFIG_SYSCTL
+
+/*
+ * ARGH!  ACPI people defined CTL_ACPI in linux/acpi.h rather than
+ * linux/sysctl.h.
+ */
+
+#define CTL_ACPI 9999   
+#define APM_S1_SLP_TYP 19
+
+/*
+ * Send us to sleep.
+ */
+
+static int sysctl_omap_pm_suspend(void)
+{
+	int retval;
+
+	retval = pm_send_all(PM_SUSPEND, (void *)3);
+
+	if (retval == 0) {
+		omap_pm_suspend();
+
+		pm_send_all(PM_RESUME, (void *)0);
+	}
+
+	return retval;
+}
+
+static struct ctl_table pm_table[] =
+{
+	{APM_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL,
+	    (proc_handler *)&sysctl_omap_pm_suspend},
+
+	{0}
+};
+
+static struct ctl_table pm_dir_table[] =
+{
+	{CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
+	{0}
+};
+
+/*
+ * Initialize power interface
+ */
+static int __init pm_init(void)
+{
+	register_sysctl_table(pm_dir_table, 1);
+	return 0;
+}
+
+__initcall(pm_init);
+
+#endif /* CONFIG_SYSCTL */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/pwt.c linux-2.4.19/arch/arm/mach-omap1510/pwt.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/pwt.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/pwt.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,309 @@
+/*
+ * File: pwt.c
+ *
+ *   Driver for Pulse Width Tone (PWT) control.
+ *
+ * Created 2001, Copyright (C) 2001 RidgeRun, Inc.  All rights reserved.
+ * Author: Steve Johnson, stevej@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+/*
+ * Use versioning if needed
+ */
+#include <linux/config.h>	/* retrieve the CONFIG_* macros */
+#ifdef CONFIG_MODVERSIONS
+#   undef MODVERSIONS		/* it might be defined */
+#   define MODVERSIONS
+#endif
+
+#ifdef MODVERSIONS
+#  include <linux/modversions.h>
+#endif
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/slab.h>
+#include <linux/kmod.h>
+#include <linux/init.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/arch/pwt_ioctl.h>
+
+MODULE_AUTHOR("Copyright 2001 RidgeRun, Inc.");
+MODULE_DESCRIPTION("PWT driver");
+
+#undef PWT_DEBUG
+
+#ifdef PWT_DEBUG
+#define DBG(format, arg...) printk(KERN_DEBUG __FUNCTION__ ": " format "\n" , ##arg)
+#define static
+#else
+#define DBG(x...)
+#endif
+
+#define PWT_BASE_ADDRESS 0xfffb6000
+
+#define FRC (PWT_BASE_ADDRESS + 0x0)
+#define VRC (PWT_BASE_ADDRESS + 0x4)
+#define GCR (PWT_BASE_ADDRESS + 0x8)
+
+typedef struct {
+	devfs_handle_t device;
+} driver_struct_t;
+
+static driver_struct_t pwt;
+
+/*
+  Table of available frequencies.
+*/
+
+#define NUM_OCTAVES 4
+#define NUM_FREQS   12
+static const u16 freq[NUM_OCTAVES][NUM_FREQS] = {
+	{5274, 4978, 4699, 4435, 4186, 3951, 3729, 3520, 3322, 3136, 2960,
+	 2794},
+	{2637, 2489, 2349, 2217, 2093, 1976, 1865, 1760, 1661, 1568, 1480,
+	 1397},
+	{1319, 1245, 1175, 1109, 1047, 988, 932, 880, 831, 784, 740, 698},
+	{659, 622, 587, 554, 523, 494, 466, 440, 415, 392, 370, 349}
+};
+
+static inline void
+orb(unsigned char val, unsigned long reg)
+{
+	outb((inb(reg) | val), reg);
+}
+
+static inline void
+andb(unsigned char val, unsigned long reg)
+{
+	outb((inb(reg) & val), reg);
+}
+
+static int
+pwt_open(struct inode *inode, struct file *filep)
+{
+	filep->private_data = 0;
+	filep->f_pos = 0;
+
+	MOD_INC_USE_COUNT;
+	return 0;
+}
+
+static int
+pwt_release(struct inode *inode, struct file *filep)
+{
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+static int
+pwt_ioctl(struct inode *inode, struct file *filep, unsigned int cmd,
+	  unsigned long arg)
+{
+	int err = 0;
+	u16 value;
+	u8 octave = 0;
+	u8 note = 0;
+	int count;
+
+	DBG("cmd - %x, arg - %ld", cmd, arg);
+
+	/* Range check the IOCTL cmd */
+	if ((_IOC_TYPE(cmd) != PWT_MAGIC_NUMBER) ||
+	    (_IOC_NR(cmd) > PWT_IOC_MAXNR)) {
+		DBG("Bad ioctl value");
+		return -EINVAL;
+	}
+
+	if (_IOC_DIR(cmd) & _IOC_READ) {
+		err = !access_ok(VERIFY_WRITE, (void *) arg, _IOC_SIZE(cmd));
+		if (err) {
+			DBG("access_ok(VERIFY_WRITE) error");
+		}
+	} else if (_IOC_DIR(cmd) & _IOC_WRITE) {
+		err = !access_ok(VERIFY_READ, (void *) arg, _IOC_SIZE(cmd));
+		if (err) {
+			DBG("access_ok(VERIFY_READ) error");
+		}
+	}
+	if (err)
+		return -EFAULT;
+
+	switch (cmd) {
+	case PWT_ENABLE:
+		orb(1, VRC);
+		break;
+	case PWT_DISABLE:
+		andb(~1, VRC);
+		break;
+	case PWT_SET_FREQUENCY:
+
+		copy_from_user(&value, (const void *) arg, sizeof (value));
+		// Simple note/octave setting
+		if (value < 0x30) {
+			outb(value, FRC);
+		} else {
+			// Snap to limits 
+			if (value > freq[0][0])
+				value = freq[0][0];	// max
+			if (value < freq[3][11])
+				value = freq[3][11];	// min
+
+			// Group into buckets
+			if (value < ((freq[3][0] + freq[2][11]) / 2)) {
+				octave = 3;
+			} else if (value < ((freq[2][0] + freq[1][11]) / 2)) {
+				octave = 2;
+			} else if (value < ((freq[1][0] + freq[0][11]) / 2)) {
+				octave = 1;
+			}
+
+			note = PWT_f;	// fall through for lowest value in octave
+			for (count = 0; count < NUM_FREQS; count++) {
+				if (value > freq[octave][count]) {
+					if (count == 0) {
+						note = count;
+					} else {	// split the difference between freqs
+						if (value >
+						    ((freq[octave][count] +
+						      freq[octave][count -
+								   1]) / 2)) {
+							note = count - 1;
+						} else {
+							note = count;
+						}
+					}
+					break;
+
+				}
+			}
+
+			outb(FREQ(note, octave), FRC);
+		}
+		break;
+	case PWT_GET_FREQUENCY:
+		value = inb(FRC);
+		copy_to_user((void *) arg, &value, sizeof (value));
+		break;
+
+		// Volume is set/read as percentages of max
+	case PWT_SET_VOLUME:
+		copy_from_user(&value, (const void *) arg, sizeof (value));
+		value = (value - 1) * 64 / 100;
+		value = (((value & 0x3f) << 1) | (inb(VRC) & 0x1));
+		outb(value, VRC);
+		break;
+	case PWT_GET_VOLUME:
+		value = (inb(VRC) >> 1);
+		value = (value + 1) * 100 / 64;
+		copy_to_user((void *) arg, &value, sizeof (value));
+		break;
+	case PWT_SET_FRC:
+		copy_from_user(&value, (const void *) arg, sizeof (value));
+		if (value > 0x2f)
+			return -EINVAL;
+		outb(value, FRC);
+		break;
+	case PWT_GET_FRC:
+		value = inb(FRC);
+		copy_to_user((void *) arg, &value, sizeof (value));
+		break;
+	case PWT_SET_VRC:
+		copy_from_user(&value, (const void *) arg, sizeof (value));
+		if (value > 0x7f)
+			return -EINVAL;
+		outb(value, VRC);
+		break;
+	case PWT_GET_VRC:
+		value = inb(VRC);
+		copy_to_user((void *) arg, &value, sizeof (value));
+		break;
+	case PWT_SET_GCR:
+		copy_from_user(&value, (const void *) arg, sizeof (value));
+		if (value > 0x3)
+			return -EINVAL;
+		outb(value, GCR);
+		break;
+	case PWT_GET_GCR:
+		value = inb(GCR);
+		copy_to_user((void *) arg, &value, sizeof (value));
+		break;
+	default:
+		return -EINVAL;
+		break;
+	}
+
+	return 0;
+}
+
+struct file_operations pwt_fops = {
+	ioctl:pwt_ioctl,
+	open:pwt_open,
+	release:pwt_release,
+};
+
+int
+omap1510_pwt_init(void)
+{
+	/*
+	   Basic initialization of device nodes.
+	 */
+
+	printk(KERN_INFO "DSPLinux PWT Control (c) 2001 RidgeRun, Inc\n");
+
+	pwt.device = devfs_register(NULL,	// dir
+				    "pwt",	// name
+				    DEVFS_FL_DEFAULT,	//flags
+				    122,	// major
+				    0,	// minor
+				    S_IFCHR | S_IRUGO | S_IWUGO,	// mode
+				    &pwt_fops,	// ops
+				    NULL);	// info (filp->private)
+	if (pwt.device < 0) {
+		printk(KERN_ERR "pwt_control: can't get major number\n");
+		return -EIO;
+	}
+
+	orb(1, GCR);		// Enable PWT clock
+
+	return 0;
+}
+
+void
+omap1510_pwt_exit(void)
+{
+	devfs_unregister(pwt.device);
+}
+
+module_init(omap1510_pwt_init);
+module_exit(omap1510_pwt_exit);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/sleep.S linux-2.4.19/arch/arm/mach-omap1510/sleep.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/sleep.S	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/sleep.S	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,137 @@
+/*
+ * Low-level PXA250/210 sleep/wakeUp support
+ *
+ * Initial SA1110 code:
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * Adapted for PXA by Nicolas Pitre:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/hardware.h>
+#include <asm/arch/pm.h>
+
+		.text
+
+/*
+ * Forces CPU into sleep state
+ *
+ * omap1510_idle_loop_suspend()
+ *
+ * cpu_omap_suspend()'s resume point.
+ *
+ * Note: This code get's copied to SRAM at boot.  When the omap
+ *	wakes up it continues execution at the point it went to sleep.
+ *	It will just start executing here, so we'll restore stuff from the
+ *	stack, reset the ARM_IDLECT1 and ARM_IDLECT2 and return 
+ */
+
+ENTRY(omap1510_idle_loop_suspend)
+
+	stmfd	sp!, {r0 - r12, lr}		@ save registers on stack
+
+	@ turn off clock domains
+	@ get arm_idlect2 into r1
+	ldr	r4, =ARM_ASM_IDLECT2
+	ldrh	r1, [r4]
+	@ ldr	r5, =IDLE_CLOCK_DOMAINS
+	@ strh	r5, [r4]
+
+	@ request ARM idle
+	@ get arm_idlect1 into r1
+	ldr	r4, =ARM_ASM_IDLECT1
+	ldrh	r2, [r4]
+	ldr	r3, =IDLE_LOOP_REQUEST
+	orr	r4, r4, r3
+	strh	r3, [r4]
+
+	mov	r4, #0
+	ldr	r5, =IDLE_WAIT_CYCLES
+loop:
+	add	r4, r4, #1
+	cmp	r4, r5
+	bne	loop
+	nop
+/*
+ * Let's wait for the next clock tick to wake us up.
+ */
+	mcr	p15, 0, r0, c7, c0, 4		@ wait for interrupt
+/*
+ * cpu_omap_suspend()'s resume point.
+ *
+ * Note: This code get's copied to SRAM at boot.  When the omap
+ *	wakes up it continues execution at the point it went to sleep.
+ *	It will just start executing here, so we'll restore stuff from the
+ *	stack, reset the ARM_IDLECT1 and ARM_IDLECT2 and return to
+ *	the address passed in arg0.
+ */
+
+	@ restore ARM_IDLECT1 and ARM_IDLECT2 and return
+	@ r2 has arm_idlect1 and r1 still has arm_idlect2
+	ldr	r4, =ARM_ASM_IDLECT2
+	strh	r1, [r4]
+
+	ldr	r4, =ARM_ASM_IDLECT1
+	strh	r2, [r4]
+
+	ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+	nop
+
+
+ENTRY(omap1510_cpu_suspend)
+
+	stmfd	sp!, {r0 - r12, lr}		@ save registers on stack
+
+	@ prepare to put SDRAM into self-refresh manually
+	ldr	r4, =EMIFF_ASM_SDRAM_CONFIG
+	ldr	r5, [r4]
+	ldr	r3, =SELF_REFRESH_MODE
+	orr	r5, r5, r3
+	str	r5, [r4]
+
+	@ prepare to put EMIFS to Sleep
+	ldr	r4, =EMIFS_ASM_CONFIG_REG
+	ldr	r5, [r4]
+	ldr	r3, =IDLE_EMIFS_REQUEST
+	orr	r5, r5, r3
+	str	r5, [r4]
+
+	@ turn off clock domains
+	ldr	r4, =ARM_ASM_IDLECT2
+	ldrh	r1, [r4]
+	ldr	r5, =IDLE_CLOCK_DOMAINS
+	strh	r5, [r4]
+
+	@ request ARM idle
+	ldr	r4, =ARM_ASM_IDLECT1
+	ldrh	r2, [r4]
+	ldr	r3, =BIG_SLEEP_REQUEST
+	strh	r3, [r4]
+/*
+ * The next UART interrupt will awaken it.
+ */
+	mov	r4, #0
+	ldr	r5, =IDLE_WAIT_CYCLES
+loop2:
+	add	r4, r4, #1
+	cmp	r4, r5
+	bne	loop2
+	nop
+	mcr	p15, 0, r0, c7, c0, 4		@ wait for interrupt
+
+	ldr	r4, =ARM_ASM_IDLECT2
+	strh	r1, [r4]
+
+	ldr	r4, =ARM_ASM_IDLECT1
+	strh	r2, [r4]
+
+	ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+	nop
+
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/time.c linux-2.4.19/arch/arm/mach-omap1510/time.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/time.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/time.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,52 @@
+/*
+ *  linux/arch/arm/mach-ti925/time.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Real time driver
+ *
+ * Copyright (C) 2000 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+
+extern int (*set_rtc) (void);
+#if 0				// never used -GDL
+static int
+ti925_set_rtc(void)
+{
+	return 1;
+}
+
+static int
+ti925_rtc_init(void)
+{
+	return 0;
+}
+
+__initcall(ti925_rtc_init);
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/timer.c linux-2.4.19/arch/arm/mach-omap1510/timer.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/timer.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/timer.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,683 @@
+/*
+ * File: timer.c
+ *
+ * A timer klib driver
+ *
+ * DESCRIPTION                                                                   
+ *    "Kernel library for the timer hardware"
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: <author> <author-email> <date>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+/*****************************************************************************
+         I n c l u d e s                                                      
+ *****************************************************************************/
+#include <asm/arch/timer.h>
+#include <asm/arch/ck.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <asm/errno.h>
+#include <asm/page.h>		/* for BUG (a hack since BUG is meant for mem errors) */
+
+#define __TIMER_INTERNAL__
+#include "arch_timer.h"
+
+/***************************************************************************** 
+         P r i v a t e
+ *****************************************************************************/
+
+typedef struct {
+	struct list_head list;
+	int timer;
+	timer_cb_t cb;
+	void *data;
+} timer_cb_info_t;
+
+static struct list_head __timer_cb_table[TIMER_N];
+
+static int __timer_requested_irq;
+static int __timer_running;
+
+static inline int
+__timer_get_divisor(int timer)
+{
+	volatile __u32 *reg;
+	int ptv, ret = 2;
+
+	reg = TIMER_CNTL_REG(timer);
+
+	if (TIMER_IS_WDG(timer))
+		ptv = (*reg & (7 << 9)) >> 9;
+	else
+		ptv = (*reg & (7 << 2)) >> 2;
+
+	while (ptv--)
+		ret *= 2;
+
+	return ret;
+}
+
+static void
+__timer_isr(int irq, void *data, struct pt_regs *regs)
+{
+	timer_cb_info_t *ptr;
+
+	list_for_each(((struct list_head *) ptr), (struct list_head *) data)
+	    (ptr->cb) (ptr->timer, ptr->data);
+}
+
+/*****************************************************************************
+         D r i v e r    I m p l                                               
+ *****************************************************************************/
+int
+timer_get_num_timers(void)
+{
+	return TIMER_N;
+}
+
+int
+timer_get_features(int timer, int *feats)
+{
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+	return TIMER_FEATS(timer);
+}
+
+int
+timer_get_irq_no(int timer)
+{
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+	return TIMER_IRQ(timer);
+}
+
+int
+timer_start(int timer)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	// If no timer is running, we'll need to enable our clock
+	if (!(__timer_running)) {
+		ck_enable(TIMER_CK(timer));
+	}
+	reg = TIMER_CNTL_REG(timer);
+	*reg |= (TIMER_START_MASK(timer));
+	__timer_running |= (1 << timer);
+
+	return 0;
+}
+
+int
+timer_stop(int timer)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	reg = TIMER_CNTL_REG(timer);
+	*reg &= ~(TIMER_START_MASK(timer));
+
+	// If no timers are running, turn off our clock.
+	__timer_running &= ~(1 << timer);
+	if (!(__timer_running)) {
+		ck_disable(TIMER_CK(timer));
+	}
+
+	return 0;
+}
+
+int
+timer_is_running(int timer)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	reg = TIMER_CNTL_REG(timer);
+	return (((*reg) & TIMER_START_MASK(timer)) == TIMER_START_MASK(timer));
+}
+
+int
+timer_set_mode(int timer, timer_mode_t mode)
+{
+	volatile __u32 *reg;
+	int ret = 0;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	reg = TIMER_CNTL_REG(timer);
+
+	switch (mode) {
+	case timer_mode_oneshot:
+		*reg &= ~TIMER_MODE_MASK(timer);
+		break;
+	case timer_mode_periodic:
+		*reg |= TIMER_MODE_MASK(timer);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	return ret;
+}
+
+int
+timer_get_mode(int timer, timer_mode_t * mode)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	if (!mode)
+		return -EFAULT;
+
+	reg = TIMER_CNTL_REG(timer);
+
+	if (*reg & TIMER_MODE_MASK(timer))
+		*mode = timer_mode_periodic;
+	else
+		*mode = timer_mode_oneshot;
+
+	return 0;
+}
+
+int
+timer_set_action(int timer, timer_action_t action)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	if (TIMER_CAN_RST(timer)) {
+		reg = TIMER_MODE_REG(timer);
+
+		if (action == timer_action_reset) {
+			*reg = (1 << 15);	/* activate reset mode */
+		} else {
+			*reg = 0xf5;	/* activate interrupt mode */
+			*reg = 0xa0;
+		}
+	} else {
+		/* handle non-watchdog timers */
+		if (~(TIMER_CAN_RST(timer))) {
+			if (action == timer_action_interrupt)
+				return 0;
+			else
+				return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+int
+timer_get_action(int timer, timer_action_t * action)
+{
+	volatile __u32 *reg;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	if (!action)
+		return -EFAULT;
+
+	if (TIMER_CAN_RST(timer)) {
+
+		reg = TIMER_CNTL_REG(timer);
+
+		if (*reg & (1 << 15))
+			*action = timer_action_reset;
+		else
+			*action = timer_action_interrupt;
+
+	} else {
+		/* handle non-watchdog timers */
+		if (~(TIMER_CAN_RST(timer))) {
+			*action = timer_action_interrupt;
+			return 0;
+		}
+	}
+	return 0;
+}
+static int
+__timer_set_wdg_period(int timer, unsigned long usecs)
+{
+	volatile __u32 *reg;
+	int div, ptv, clock;
+
+	if (!TIMER_CHECK(timer) || !usecs)
+		return -EINVAL;
+
+	/* First get the ticks per nsec of the current clock. */
+	if ((clock = ck_get_rate(TIMER_CK(timer))) < 0)
+		return -EIO;
+	clock = (clock * 1000) / 14;
+
+	ptv = 0;
+	div = 2;
+
+	/* If we need to increment the ptv... don't forget that our clock
+	   units are in tick/nsec, so muliply the right hand by 1000 to
+	   convert to usecs.
+	 */
+	while ((usecs / div) > (1000 * (TIMER_COUNT_MAX(timer) / clock))) {
+		if (ptv == TIMER_MAX_PTV) {
+			/* Well, this can happen if somebody tries to set the
+			   watchdog timer to too high of a period. Since the
+			   watchdog only has a 16 bit count register we can't
+			   go quite as high as the normal timers with 32 bit
+			   count registers.
+			 */
+			return -ERANGE;
+		}
+		div *= 2;
+		ptv++;
+	}
+
+	reg = TIMER_CNTL_REG(timer);
+
+	/* Set the PTV */
+	if (TIMER_IS_WDG(timer)) {
+		*reg &= ~(7 << 9);
+		*reg |= (ptv << 9);
+	} else {
+		*reg &= ~(7 << 2);
+		*reg |= (ptv << 2);
+	}
+
+	/* If Method #2 will give us an underflow... */
+	if (usecs < div) {
+		/* Method #1: since the max div is 256 we know that usecs is
+		   less than 1000, so this will not overflow 
+		 */
+		usecs = usecs * (clock / div);
+	} else {
+		/* Method #2: since the max usecs is 0xffff (or we would have
+		   detected an error when calculating the ptv above) we know
+		   this will not overflow a 32-bit:
+		 */
+		usecs = (usecs / div) * clock;
+	}
+
+	/* ... and convert from ticks/nsecs to ticks/usecs */
+	usecs /= 1000;
+
+	/* Set the count */
+	reg = TIMER_LOAD_REG(timer);
+	*reg = usecs;
+
+	return 0;
+}
+
+int
+timer_set_period(int timer, unsigned long usecs)
+{
+	volatile __u32 *reg;
+	int div, ptv, clock;
+
+	if (!TIMER_CHECK(timer) || !usecs)
+		return -EINVAL;
+
+	if (TIMER_IS_WDG(timer))
+		return __timer_set_wdg_period(timer, usecs);
+
+	/* The count we must program to give us the desired period is given
+	   by this formula:
+
+	   count = period * clock / (2 ^ ptv)
+
+	   If you manipulate this formula you can make a table like this, which
+	   applies to the omap1510 h/w:
+
+	   clock  range
+	   -----  ------------------
+	   12     167 ns - 10.6 days
+	   15     133 ns - 8.4 days
+	   30     66 ns - 4.24 days
+	   60     33 ns - 2.12 days
+	   120    17 ns - 1.06 days
+
+	   Since we take about 50 nanoseconds per instruction on an omap1510
+	   (based on 50 BogoMIPS) we might as well just use the slow clock for
+	   everything. Incidentally, we could get a more accurate BogoMIPs 
+	   calculation using the fast clock...
+
+	   So now we just need to calculate the ptv.
+
+	   ptv  range
+	   ---  -----
+	   0    167 ns - 715 sec (almost 2 hours)
+	   2    334 ns - 1430 sec
+	   etc...
+
+	   So to prevent overflow we'll need to increment the ptv to meet this
+	   constraint:
+
+	   count <= MAX
+
+	   Which we can rearrange until we can get something we can test for
+	   without having to worry about overflow or integer round-to-zero:
+
+	   period * clock / (2 ^ (ptv + 1)) <= MAX
+	   period * clock / div <= MAX
+	   period * clock <= MAX * div
+	   period / div <= MAX / clock           
+	 */
+
+	/* First get the ticks per usec of the current clock. */
+	if ((clock = ck_get_rate(TIMER_CK(timer))) < 0)
+		return -EIO;
+
+	ptv = 0;
+	div = 2;
+
+	/* If we need to increment the ptv... */
+	while ((usecs / div) > (TIMER_COUNT_MAX(timer) / clock)) {
+		if (ptv == TIMER_MAX_PTV) {
+			/* Well, this can happen if somebody tries to set the
+			   watchdog timer to too high of a period. Since the
+			   watchdog only has a 16 bit count register we can't
+			   go quite as high as the normal timers with 32 bit
+			   count registers.
+			 */
+			return -ERANGE;
+		}
+		div *= 2;
+		ptv++;
+	}
+
+	reg = TIMER_CNTL_REG(timer);
+
+	/* Set the PTV */
+	if (TIMER_IS_WDG(timer)) {
+		*reg &= ~(7 << 9);
+		*reg |= (ptv << 9);
+	} else {
+		*reg &= ~(7 << 2);
+		*reg |= (ptv << 2);
+	}
+
+	/* If we need to avoid underflow... */
+	if (usecs < div)
+		usecs = (usecs * clock) / div;
+	/* ...else avoid overflow... */
+	else
+		usecs = (usecs / div) * clock;
+
+	/* Set the count */
+	reg = TIMER_LOAD_REG(timer);
+	*reg = usecs;
+
+	return 0;
+}
+
+int
+__timer_get_wdg_time(int timer, unsigned long *usecs, volatile __u32 * reg)
+{
+	/* Hack -- use a special routine for the wdt since it's clock is less
+	   than one MHz (< 1 tick per usec). If we ask the clock driver what
+	   the clock is it will return 0, which isn't much good for dividing
+	   the count. So we hardcode knowledge that the wdt clock is CK_CLKIN
+	   divided by 14. *** FIXME ***
+	 */
+	int clock, div;
+	__u32 count;
+
+	if (!usecs)
+		return -EFAULT;
+
+	/* Read the count. */
+	count = *reg;
+
+	/* Get the clock rate in units of ticks per nsecs. */
+	if ((clock = ck_get_rate(TIMER_CK(timer))) < 0)
+		return -EIO;
+	clock = (clock * 1000) / 14;
+
+	if (clock == 0)
+		return -ERANGE;
+
+	/* Get the clock divider. */
+	div = __timer_get_divisor(timer);
+
+	/* If we need to avoid underflow... */
+	if (count < clock)
+		*usecs = ((count * div) / clock);
+
+	/* ...else avoid overflow... */
+	else
+		*usecs = ((count / clock) * div);
+
+	/* ...and convert back to usecs */
+	*usecs *= 1000;
+
+	return 0;
+}
+
+int
+__timer_get_time(int timer, unsigned long *usecs, volatile __u32 * reg)
+{
+	int clock, div;
+	__u32 count;
+
+	if (!usecs)
+		return -EFAULT;
+
+	/* The actual value WRT the units is given by the formula:
+	   period = count * div / clock
+	 */
+
+	/* Read the count. */
+	count = *reg;
+
+	/* Get the clock rate in units of ticks per usecs. */
+	if ((clock = ck_get_rate(TIMER_CK(timer))) < 0)
+		return -EIO;
+
+	if (clock == 0)
+		return -ERANGE;
+
+	/* Get the clock divider. */
+	div = __timer_get_divisor(timer);
+
+	/* If we need to avoid underflow... */
+	if (count < clock)
+		*usecs = ((count * div) / clock);
+
+	/* ...else avoid overflow... */
+	else
+		*usecs = ((count / clock) * div);
+
+	return 0;
+}
+
+int
+timer_get_period(int timer, unsigned long *usecs)
+{
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	/* For the wdt the load register is write-only. */
+	if (TIMER_IS_WDG(timer))
+		return -ENOSYS;
+
+	return __timer_get_time(timer, usecs, TIMER_LOAD_REG(timer));
+}
+
+int
+timer_get_time_remaining(int timer, unsigned long *usecs)
+{
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	if (TIMER_IS_WDG(timer))
+		return __timer_get_wdg_time(timer, usecs,
+					    TIMER_READ_REG(timer));
+
+	return __timer_get_time(timer, usecs, TIMER_READ_REG(timer));
+}
+
+int
+timer_register_cb(int timer, timer_cb_t cb, void *data)
+{
+	timer_cb_info_t *info;
+	struct list_head *head;
+	int ret = 0, flags;
+
+	if (!TIMER_CHECK(timer) || !cb)
+		return -EINVAL;
+
+	if (!(info = kmalloc(sizeof (timer_cb_info_t), GFP_KERNEL)))
+		return -ENOMEM;
+
+	/***************************************************/
+	save_flags_cli(flags);
+
+	head = &__timer_cb_table[timer];
+
+	if (list_empty(head)) {
+		if ((ret = request_irq(TIMER_IRQ(timer), &__timer_isr, 0,
+				       "timer",
+				       &__timer_cb_table[timer])) < 0) {
+			restore_flags(flags);
+			goto abort;
+		}
+		__timer_requested_irq |= (1 << timer);
+	}
+
+	list_add((struct list_head *) info, head);
+
+	restore_flags(flags);
+	/***************************************************/
+
+	info->timer = timer;
+	info->cb = cb;
+	info->data = data;
+
+	goto exit;
+
+      abort:
+	kfree(info);
+
+      exit:
+	return ret;
+}
+
+int
+timer_unregister_cb(int timer, void *data)
+{
+	timer_cb_info_t *ptr;
+	struct list_head *head;
+	int flags;
+
+	if (!TIMER_CHECK(timer))
+		return -EINVAL;
+
+	/***************************************************/
+	save_flags_cli(flags);
+
+	head = &__timer_cb_table[timer];
+
+	list_for_each(((struct list_head *) ptr), head) {
+		if (ptr->data != data)
+			continue;
+		list_del((struct list_head *) ptr);
+		kfree(ptr);
+		break;
+	}
+
+	restore_flags(flags);
+	/***************************************************/
+
+	return 0;
+}
+
+/*****************************************************************************
+         M o d u l e                                                          
+ *****************************************************************************/
+static int __init
+init_omap1510_timer(void)
+{
+	int timer;
+
+	printk("DSPLinux Timer (c) 2001 RidgeRun, Inc.\n");
+
+	for (timer = 0; timer < TIMER_N; timer++)
+		INIT_LIST_HEAD(&__timer_cb_table[timer]);
+
+	return 0;
+}
+
+static void __exit
+exit_omap1510_timer(void)
+{
+	int i;
+
+	for (i = 0; i < TIMER_N; i++) {
+		timer_stop(i);
+		// only free timers if you've requested one.  
+		if (__timer_requested_irq & (1 << i)) {
+			free_irq(TIMER_IRQ(i), &__timer_cb_table[i]);
+		}
+	}
+	if (!(__timer_running)) {
+		ck_disable(TIMER_CK(1));
+	}
+}
+
+module_init(init_omap1510_timer);
+module_exit(exit_omap1510_timer);
+EXPORT_SYMBOL(timer_start);
+EXPORT_SYMBOL(timer_stop);
+EXPORT_SYMBOL(timer_get_mode);
+EXPORT_SYMBOL(timer_set_mode);
+EXPORT_SYMBOL(timer_get_period);
+EXPORT_SYMBOL(timer_get_time_remaining);
+EXPORT_SYMBOL(timer_get_action);
+EXPORT_SYMBOL(timer_is_running);
+
+EXPORT_SYMBOL(timer_get_num_timers);
+EXPORT_SYMBOL(timer_set_period);
+EXPORT_SYMBOL(timer_get_features);
+EXPORT_SYMBOL(timer_register_cb);
+EXPORT_SYMBOL(timer_unregister_cb);
+EXPORT_SYMBOL(timer_set_action);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/timer_proc.c linux-2.4.19/arch/arm/mach-omap1510/timer_proc.c
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mach-omap1510/timer_proc.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mach-omap1510/timer_proc.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,644 @@
+/*
+ * File: timer_proc.c
+ *
+ * /proc/timer
+ *
+ * DESCRIPTION                                                                   
+ *    This provides a proc file interface to the kernel timer API. It creates
+ *    /proc/timer and populates it with one subdirectory per system timer.
+ *    Under each subdirectory it provides the following files:
+ *    
+ *    run -- read/write the timer status to "on" or "off"
+ *    mode -- read/write the timer mode to "oneshot" or "periodic"
+ *    period -- read/write the timer period as "<decimal num> <units>"
+ *    count -- read the count as "<rollovers> <current count>"
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: <author> <author-email> <date>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+/*****************************************************************************
+         I n c l u d e s                                                      
+ *****************************************************************************/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <asm/segment.h>
+#include <asm/uaccess.h>
+#include <asm/arch/timer.h>
+
+typedef struct {
+	struct proc_dir_entry *subdir;
+	unsigned long rollover;
+} timer_proc_info_t;
+
+static timer_proc_info_t *__timer_proc_subdirs;
+
+static void
+__timer_proc_cb(int timer, void *data)
+{
+	timer_proc_info_t *info = (timer_proc_info_t *) data;
+
+	info->rollover++;
+}
+
+/*****************************************************************************
+        r u n
+ *****************************************************************************/
+static int
+__timer_proc_run_read(struct file *file, char *buf, size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16];
+	int ret = 0, timer;
+
+	if ((len < 4) || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde)
+		return -ENOTDIR;
+	timer = (int) pde->data;
+
+	if ((ret = timer_is_running(timer)) < 0)
+		goto exit;
+
+	len = sprintf(kbuf, "%s\n", (ret ? "on" : "off"));
+	copy_to_user(buf, kbuf, len);
+
+	ret = len;
+	file->f_pos += len;
+      exit:
+	return ret;
+}
+static ssize_t
+__timer_proc_run_write(struct file *file, const char *buf,
+		       size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16], *p;
+	int ret = 0, timer;
+
+	if (!len || file->f_pos)
+		return 0;
+
+	if (len < strlen("on"))
+		return -EINVAL;
+
+	if (len > sizeof (kbuf))
+		len = sizeof (kbuf);
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde)
+		return -ENOTDIR;
+	timer = (int) pde->data;
+
+	copy_from_user(kbuf, buf, len);
+	p = kbuf;
+
+	if (strnicmp(kbuf, "on", strlen("on")) == 0) {
+		if ((ret = timer_start(timer)) < 0)
+			return ret;
+		goto done;
+	}
+
+	if (strnicmp(kbuf, "off", strlen("off")) == 0) {
+		if ((ret = timer_stop(timer)) < 0)
+			return ret;
+		goto done;
+	}
+
+	return -EINVAL;
+
+      done:
+	file->f_pos += len;
+	return len;
+}
+static int
+__timer_proc_run_permission(struct inode *inode, int unused)
+{
+	return 0;		/* REVISIT */
+}
+
+static struct file_operations __timer_proc_run_fops = {
+	read:__timer_proc_run_read,
+	write:__timer_proc_run_write
+};
+
+static struct inode_operations __timer_proc_run_iops = {
+	permission:&__timer_proc_run_permission
+};
+
+/*****************************************************************************
+        m o d e
+ *****************************************************************************/
+static int
+__timer_proc_mode_read(struct file *file, char *buf, size_t len,
+		       loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16];
+	int ret = 0, timer;
+	timer_mode_t mode;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if ((ret = timer_get_mode(timer, &mode)) < 0)
+		goto exit;
+
+	switch (mode) {
+	case timer_mode_oneshot:
+		len = sprintf(kbuf, "oneshot\n");
+		break;
+	case timer_mode_periodic:
+		len = sprintf(kbuf, "periodic\n");
+		break;
+	default:
+		len = sprintf(kbuf, "???\n");
+		break;
+	}
+
+	copy_to_user(buf, kbuf, len);
+	file->f_pos += len;
+	ret = len;
+
+      exit:
+	return ret;
+}
+static ssize_t
+__timer_proc_mode_write(struct file *file, const char *buf,
+			size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16];
+	int ret = 0, timer;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if (len > sizeof (kbuf))
+		len = sizeof (kbuf);
+
+	copy_from_user(kbuf, buf, len);
+
+	if (strnicmp(kbuf, "oneshot", strlen("oneshot")) == 0) {
+		if ((ret = timer_set_mode(timer, timer_mode_oneshot)) < 0)
+			goto exit;
+		goto done;
+	}
+
+	if (strnicmp(kbuf, "periodic", strlen("periodic")) == 0) {
+		if ((ret = timer_set_mode(timer, timer_mode_periodic)) < 0)
+			goto exit;
+		goto done;
+	}
+
+	ret = -EINVAL;
+	goto exit;
+      done:
+	file->f_pos += len;
+	ret = len;
+      exit:
+	return ret;
+}
+static struct file_operations __timer_proc_mode_fops = {
+	read:__timer_proc_mode_read,
+	write:__timer_proc_mode_write
+};
+#define __timer_proc_mode_iops __timer_proc_run_iops
+
+/*****************************************************************************
+        p e r i o d
+ *****************************************************************************/
+
+static int
+__timer_proc_period_read(struct file *file, char *buf, size_t len,
+			 loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[32];
+	int ret = 0, timer, klen;
+	unsigned long val;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if ((ret = timer_get_period(timer, &val)) < 0)
+		goto exit;
+
+	klen = sprintf(kbuf, "%ld\n", val);
+
+	if (klen > len)
+		klen = len;
+
+	copy_to_user(buf, kbuf, klen);
+	file->f_pos += klen;
+	ret = klen;
+
+      exit:
+	return ret;
+}
+static ssize_t
+__timer_proc_period_write(struct file *file, const char *buf,
+			  size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16], *p;
+	int ret = 0, left, timer;
+	unsigned long val = 0;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if (len > sizeof (kbuf))
+		len = sizeof (kbuf);
+
+	copy_from_user(kbuf, buf, len);
+	p = kbuf;
+	left = len;
+
+	while (*p && left-- && (*p >= '0') && (*p <= '9')) {
+		val = (val * 10) + (*p - '0');
+		p++;
+	}
+
+	if ((ret = timer_set_period(timer, val)) < 0)
+		goto exit;
+
+	len -= left;
+	file->f_pos += len;
+	ret = len;
+      exit:
+	return ret;
+}
+static struct file_operations __timer_proc_period_fops = {
+	read:__timer_proc_period_read,
+	write:__timer_proc_period_write
+};
+#define __timer_proc_period_iops __timer_proc_run_iops
+
+/*****************************************************************************
+        c o u n t
+ *****************************************************************************/
+static int
+__timer_proc_count_read(struct file *file, char *buf, size_t len,
+			loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[32];
+	int ret = 0, timer, klen;
+	unsigned long val;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	klen = sprintf(kbuf, "%ld:", __timer_proc_subdirs[timer].rollover);
+
+	if ((ret = timer_get_time_remaining(timer, &val)) < 0)
+		goto exit;
+
+	klen += sprintf(kbuf + klen, "%ld\n", val);
+
+	if (klen > len)
+		klen = len;
+
+	copy_to_user(buf, kbuf, klen);
+	file->f_pos += klen;
+	ret = klen;
+
+      exit:
+	return ret;
+}
+static ssize_t
+__timer_proc_count_write(struct file *file, const char *buf,
+			 size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	int ret = 0, timer, flags;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	/* reset the rollover count */
+	local_irq_save(flags);
+	__timer_proc_subdirs[timer].rollover = 0;
+	local_irq_restore(flags);
+
+	file->f_pos += len;
+	ret = len;
+      exit:
+	return ret;
+}
+
+static struct file_operations __timer_proc_count_fops = {
+	read:__timer_proc_count_read,
+	write:__timer_proc_count_write,
+};
+#define __timer_proc_count_iops __timer_proc_run_iops
+/*****************************************************************************
+        a c t i o n
+ *****************************************************************************/
+static int
+__timer_proc_action_read(struct file *file, char *buf, size_t len,
+			 loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16];
+	int ret = 0, timer;
+	timer_action_t action;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if ((ret = timer_get_action(timer, &action)) < 0)
+		goto exit;
+
+	switch (action) {
+	case timer_action_interrupt:
+		len = sprintf(kbuf, "interrupt\n");
+		break;
+	case timer_action_reset:
+		len = sprintf(kbuf, "reset\n");
+		break;
+	default:
+		len = sprintf(kbuf, "???\n");
+		break;
+	}
+
+	copy_to_user(buf, kbuf, len);
+	file->f_pos += len;
+	ret = len;
+
+      exit:
+	return ret;
+}
+static ssize_t
+__timer_proc_action_write(struct file *file, const char *buf,
+			  size_t len, loff_t * offset)
+{
+	struct proc_dir_entry *pde;
+	char kbuf[16];
+	int ret = 0, timer;
+
+	if (!len || file->f_pos)
+		goto exit;
+
+	pde = (struct proc_dir_entry *) file->f_dentry->d_inode->u.generic_ip;
+	if (!pde) {
+		ret = -ENOTDIR;
+		goto exit;
+	}
+	timer = (int) pde->data;
+
+	if (len > sizeof (kbuf))
+		len = sizeof (kbuf);
+
+	copy_from_user(kbuf, buf, len);
+
+	if (strnicmp(kbuf, "interrupt", strlen("interrupt")) == 0) {
+		if ((ret = timer_set_action(timer, timer_action_interrupt)) < 0)
+			goto exit;
+		goto done;
+	}
+
+	if (strnicmp(kbuf, "reset", strlen("reset")) == 0) {
+		if ((ret = timer_set_action(timer, timer_action_reset)) < 0)
+			goto exit;
+		goto done;
+	}
+
+	ret = -EINVAL;
+	goto exit;
+      done:
+	file->f_pos += len;
+	ret = len;
+      exit:
+	return ret;
+}
+static struct file_operations __timer_proc_action_fops = {
+	read:__timer_proc_action_read,
+	write:__timer_proc_action_write
+};
+#define __timer_proc_action_iops __timer_proc_run_iops
+
+/*****************************************************************************
+         D i r e c t o r i e s
+ *****************************************************************************/
+static struct proc_dir_entry *__timer_proc_dir;
+
+static int
+__timer_proc_create_directory(void)
+{
+	__timer_proc_dir = create_proc_entry("timer", S_IFDIR, &proc_root);
+
+	if (!__timer_proc_dir)
+		return -ENOMEM;
+	return 0;
+}
+static int
+__timer_proc_create_entry(int timer, struct proc_dir_entry *p,
+			  char *name, struct inode_operations *iops,
+			  struct file_operations *fops)
+{
+	struct proc_dir_entry *pde;
+
+	pde = create_proc_entry(name, S_IFREG, p);
+
+	if (!pde)
+		return -ENOMEM;
+
+	pde->data = (void *) timer;
+	pde->proc_fops = fops;
+	pde->proc_iops = iops;
+
+	return 0;
+}
+static int
+__timer_proc_create_subdir(int timer)
+{
+	struct proc_dir_entry *pde;
+	char buf[3];
+	int feats;
+
+	sprintf(buf, "%d", timer);
+
+	pde = create_proc_entry(buf, S_IFDIR, __timer_proc_dir);
+	if (!pde)
+		return -ENOMEM;
+
+	__timer_proc_subdirs[timer].subdir = pde;
+
+	pde->data = (void *) timer;
+
+	__timer_proc_create_entry(timer, pde, "run",
+				  &__timer_proc_run_iops,
+				  &__timer_proc_run_fops);
+
+	__timer_proc_create_entry(timer, pde, "mode",
+				  &__timer_proc_mode_iops,
+				  &__timer_proc_mode_fops);
+
+	__timer_proc_create_entry(timer, pde, "period",
+				  &__timer_proc_period_iops,
+				  &__timer_proc_period_fops);
+
+	__timer_proc_create_entry(timer, pde, "count",
+				  &__timer_proc_count_iops,
+				  &__timer_proc_count_fops);
+
+	timer_get_features(timer, &feats);
+	if (feats & TIMERF_RST)
+		__timer_proc_create_entry(timer, pde, "action",
+					  &__timer_proc_action_iops,
+					  &__timer_proc_action_fops);
+
+	return 0;		/* REVISIT -- need to do some error cleanup here */
+}
+static void
+__timer_proc_remove_subdir(int timer)
+{
+	struct proc_dir_entry *pde;
+	char buf[3];
+
+	pde = __timer_proc_subdirs[timer].subdir;
+
+	remove_proc_entry("run", pde);
+	remove_proc_entry("mode", pde);
+	remove_proc_entry("period", pde);
+	remove_proc_entry("count", pde);
+
+	sprintf(buf, "%d", timer);
+	remove_proc_entry(buf, __timer_proc_dir);
+}
+
+/*****************************************************************************
+         M o d u l e                                                          
+ *****************************************************************************/
+int
+init_module(void)
+{
+	int ret = 0, timer, n;
+
+	printk("DSPLinux timer_proc (c) 2001 RidgeRun, Inc\n");
+
+	if ((ret = __timer_proc_create_directory()) < 0)
+		goto exit;
+
+	if ((n = timer_get_num_timers()) <= 0)
+		goto exit;
+
+	__timer_proc_subdirs = kmalloc(n * sizeof (timer_proc_info_t),
+				       GFP_KERNEL);
+	memset(__timer_proc_subdirs, 0, n * sizeof (timer_proc_info_t));
+
+	if (!__timer_proc_subdirs) {
+		ret = -ENOMEM;
+		goto bail;
+	}
+
+	for (timer = 0; timer < n; timer++) {
+		__timer_proc_create_subdir(timer);
+		timer_register_cb(timer, __timer_proc_cb,
+				  (void *) &__timer_proc_subdirs[timer]);
+	}
+
+	goto exit;
+      bail:
+	remove_proc_entry("timer", &proc_root);
+      exit:
+	return ret;
+}
+
+void
+cleanup_module(void)
+{
+	int n, timer;
+
+	if ((n = timer_get_num_timers()) > 0) {
+		for (timer = 0; timer < timer_get_num_timers(); timer++) {
+			timer_unregister_cb(timer,
+					    (void *)
+					    &__timer_proc_subdirs[timer]);
+			__timer_proc_remove_subdir(timer);
+		}
+		kfree(__timer_proc_subdirs);
+	}
+
+	remove_proc_entry("timer", &proc_root);
+}
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/Makefile linux-2.4.19/arch/arm/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -46,6 +46,7 @@
 tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100
@@ -160,6 +161,11 @@
 MACHINE                = omaha
 endif
 
+ifeq ($(CONFIG_ARCH_OMAP1510),y)
+MACHINE                  = omap1510
+INCDIR                   = omap1510
+endif
+
 export	MACHINE PROCESSOR TEXTADDR GZFLAGS CFLAGS_BOOT OBJCOPYFLAGS
 
 # Only set INCDIR if its not already defined above
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mm/Makefile linux-2.4.19/arch/arm/mm/Makefile
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mm/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/mm/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -36,6 +36,7 @@
 p-$(CONFIG_CPU_ARM720T)	+= proc-arm720.o
 p-$(CONFIG_CPU_ARM920T)	+= proc-arm920.o
 p-$(CONFIG_CPU_ARM922T)	+= proc-arm922.o
+p-$(CONFIG_CPU_ARM925T)	+= proc-arm925.o
 p-$(CONFIG_CPU_ARM926T)	+= proc-arm926.o
 p-$(CONFIG_CPU_ARM1020)	+= proc-arm1020.o
 p-$(CONFIG_CPU_ARM1026)	+= proc-arm1026.o
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/mm/proc-arm925.S linux-2.4.19/arch/arm/mm/proc-arm925.S
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/mm/proc-arm925.S	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/arch/arm/mm/proc-arm925.S	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,742 @@
+/*
+ *  linux/arch/arm/mm/arm925.S: MMU functions for ARM925
+ *
+ *  Copyright (C) 1999-2001 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2002 RidgeRun, Inc.
+ *  Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *
+ * These are the low level assembler for performing cache and TLB
+ * functions on the arm925.
+ */
+#include <linux/linkage.h>
+#include <linux/config.h>
+#include <asm/assembler.h>
+#include <asm/constants.h>
+#include <asm/procinfo.h>
+#include <asm/hardware.h>
+
+
+/*
+ * This is the maximum size of an area which will be invalidated
+ * using the single invalidate entry instructions.  Anything larger
+ * than this, and we go for the whole cache.
+ *
+ * This value should be chosen such that we choose the cheapest
+ * alternative.
+ */
+#define MAX_AREA_SIZE	(2 * 1024)
+
+/*
+ * the cache line size of the I and D cache
+ */
+#define DCACHELINESIZE	16
+#define ICACHELINESIZE	16
+
+/*
+ * and the page size
+ */
+#define PAGESIZE	4096
+
+	.text
+
+/*
+ * cpu_arm925_data_abort()
+ *
+ * obtain information about current aborted instruction
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
+ *
+ * Inputs:
+ *  r2 = address of abort
+ *  r3 = cpsr of abort
+ *
+ * Returns:
+ *  r0 = address of abort
+ *  r1 != 0 if writing
+ *  r3 = FSR
+ *  r4 = corrupted
+ */
+	.align	5
+ENTRY(cpu_arm925_data_abort)
+	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	mrc	p15, 0, r4, c5, c0, 0		@ get FSR
+
+	tst	r3, #1<<5			@ Check for Thumb-bit (NE -> found)
+	ldrneh	r1, [r2]			@ Read aborted Thumb instruction
+	tstne	r1, r1, lsr #12 		@ C = bit 11
+
+	ldreq	r1, [r2]			@ Read aborted ARM instruction
+	tsteq	r1, r1, lsr #21 		@ C = bit 20
+
+	sbc	r1, r1, r1			@ r1 = C - 1
+	and	r3, r4, #255
+	mov	pc, lr
+
+/*
+ * cpu_arm925_check_bugs()
+ */
+ENTRY(cpu_arm925_check_bugs)
+	mrs	ip, cpsr
+	bic	ip, ip, #F_BIT
+	msr	cpsr, ip
+	mov	pc, lr
+
+/*
+ * cpu_arm925_proc_init()
+ */
+ENTRY(cpu_arm925_proc_init)
+	mov	pc, lr
+
+/*
+ * cpu_arm925_proc_fin()
+ */
+ENTRY(cpu_arm925_proc_fin)
+	stmfd	sp!, {lr}
+	mov	ip, #F_BIT | I_BIT | SVC_MODE
+	msr	cpsr_c, ip
+	bl	cpu_arm925_cache_clean_invalidate_all
+	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
+	bic	r0, r0, #0x1000			@ ...i............
+	bic	r0, r0, #0x000e			@ ............wca.
+	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
+	ldmfd	sp!, {pc}
+
+/*
+ * cpu_arm925_reset(loc)
+ *
+ * Perform a soft reset of the system.  Put the CPU into the
+ * same state as it would be if it had been reset, and branch
+ * to what would be the reset vector.
+ *
+ * loc: location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_arm925_reset)
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
+	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
+	bic	ip, ip, #0x000f			@ ............wcam
+	bic	ip, ip, #0x1100			@ ...i...s........
+	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
+	mov	pc, r0
+
+/*
+ * cpu_arm925_do_idle()
+ */
+	.align	5
+ENTRY(cpu_arm925_do_idle)
+#if defined(CONFIG_CPU_ARM925_CPU_IDLE)
+	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
+#endif
+	mov	pc, lr
+
+/* ================================= CACHE ================================ */
+
+
+/*
+ * cpu_arm925_cache_clean_invalidate_all()
+ *
+ * clean and invalidate all cache lines
+ *
+ * Note:
+ *  1. we should preserve r0 at all times
+ */
+	.align	5
+ENTRY(cpu_arm925_cache_clean_invalidate_all)
+	mov	r2, #1
+cpu_arm925_cache_clean_invalidate_all_r2:
+	mov	ip, #0
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
+#else
+/*
+ * 'Clean & Invalidate whole DCache'
+ * Re-written to use Index Ops.
+ * NOTE: Requires TI925T Configuration Register C bit <- 0
+ *       for clean and invalidate of both D-Cache sets.
+ */
+	mov	r3, #255 << 4		@ 256 entries/set
+					@ ((NSETS - 1) << (CIR[13-12] + 3))
+2:	mcr	p15, 0, r3, c7, c14, 2	@ clean & invalidate D index
+	subs	r3, r3, #1 << 4
+	bcs	2b			@ entries 255 to 0
+#endif
+	teq	r2, #0
+	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm925_cache_clean_invalidate_range(start, end, flags)
+ *
+ * clean and invalidate all cache lines associated with this area of memory
+ *
+ * This is a little misleading, it is not intended to clean out
+ * the i-cache but to make sure that any data written to the
+ * range is made consistant.  This means that when we execute code
+ * in that region, everything works as we expect.
+ *
+ * This generally means writing back data in the Dcache and
+ * write buffer and flushing the Icache over that region
+ * start: Area start address
+ * end:   Area end address
+ * flags: nonzero for I cache as well
+ */
+		.align	5
+ENTRY(cpu_arm925_cache_clean_invalidate_range)
+	bic	r0, r0, #DCACHELINESIZE - 1	@ && added by PGM
+	bic	r1, r1, #DCACHELINESIZE - 1     @ && added by DHM
+	sub	r3, r1, r0
+	cmp	r3, #MAX_AREA_SIZE
+	bgt	cpu_arm925_cache_clean_invalidate_all_r2
+1:	teq	r2, #0
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+#else
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+#endif
+	cmp	r0, r1
+	blt	1b
+
+	mov	r1, #0
+	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm925_flush_ram_page(page)
+ *
+ * clean and invalidate all cache lines associated with this area of memory
+ *
+ * page: page to clean and invalidate
+ */
+	.align	5
+ENTRY(cpu_arm925_flush_ram_page)
+	mov	r1, #PAGESIZE
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+#else
+1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+#endif
+	subs	r1, r1, #2 * DCACHELINESIZE
+	bne	1b
+	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/* ================================ D-CACHE =============================== */
+
+/*
+ * cpu_arm925_dcache_invalidate_range(start, end)
+ *
+ * throw away all D-cached data in specified region without an obligation
+ * to write them back.  Note however that we must clean the D-cached entries
+ * around the boundaries if the start and/or end address are not cache
+ * aligned.
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ */
+	.align	5
+ENTRY(cpu_arm925_dcache_invalidate_range)
+#ifndef CONFIG_CPU_ARM925_WRITETHROUGH
+	tst	r0, #DCACHELINESIZE - 1
+	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
+	tst	r1, #DCACHELINESIZE - 1
+	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
+#endif
+	bic	r0, r0, #DCACHELINESIZE - 1
+	bic	r1, r1, #DCACHELINESIZE - 1
+1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	cmp	r0, r1
+	blt	1b
+	mov	pc, lr
+
+/*
+ * cpu_arm925_dcache_clean_range(start, end)
+ *
+ * For the specified virtual address range, ensure that all caches contain
+ * clean data, such that peripheral accesses to the physical RAM fetch
+ * correct data.
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ */
+	.align	5
+ENTRY(cpu_arm925_dcache_clean_range)
+	mov	r2, #0
+#ifndef CONFIG_CPU_ARM925_WRITETHROUGH
+	bic	r0, r0, #DCACHELINESIZE - 1
+	sub	r1, r1, r0
+	cmp	r1, #MAX_AREA_SIZE
+	bgt	cpu_arm925_cache_clean_invalidate_all_r2
+
+	bic	r1, r1, #DCACHELINESIZE -1
+	add	r1, r1, #DCACHELINESIZE
+
+1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	subs	r1, r1, #DCACHELINESIZE
+	bpl	1b
+#endif
+	mcr	p15, 0, r2, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm925_dcache_clean_page(page)
+ *
+ * Cleans a single page of dcache so that if we have any future aliased
+ * mappings, they will be consistent at the time that they are created.
+ *
+ * page: virtual address of page to clean from dcache
+ *
+ * Note:
+ *  1. we don't need to flush the write buffer in this case.
+ *  2. we don't invalidate the entries since when we write the page
+ *     out to disk, the entries may get reloaded into the cache.
+ */
+	.align	5
+ENTRY(cpu_arm925_dcache_clean_page)
+#ifndef CONFIG_CPU_ARM925_WRITETHROUGH
+	mov	r1, #PAGESIZE
+1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	subs	r1, r1, #2 * DCACHELINESIZE
+	bne	1b
+#endif
+	mov	pc, lr
+
+/*
+ * cpu_arm925_dcache_clean_entry(addr)
+ *
+ * Clean the specified entry of any caches such that the MMU
+ * translation fetches will obtain correct data.
+ *
+ * addr: cache-unaligned virtual address
+ */
+	.align	5
+ENTRY(cpu_arm925_dcache_clean_entry)
+#ifndef CONFIG_CPU_ARM925_WRITETHROUGH
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+#endif
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/* ================================ I-CACHE =============================== */
+
+/*
+ * cpu_arm925_icache_invalidate_range(start, end)
+ *
+ * invalidate a range of virtual addresses from the Icache
+ *
+ * This is a little misleading, it is not intended to clean out
+ * the i-cache but to make sure that any data written to the
+ * range is made consistant.  This means that when we execute code
+ * in that region, everything works as we expect.
+ *
+ * This generally means writing back data in the Dcache and
+ * write buffer and flushing the Icache over that region
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ *
+ * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to
+ * loop twice, once for i-cache, once for d-cache)
+ */
+	.align	5
+ENTRY(cpu_arm925_icache_invalidate_range)
+	bic	r0, r0, #ICACHELINESIZE - 1	@ Safety check
+	sub	r1, r1, r0
+	cmp	r1, #MAX_AREA_SIZE
+	bgt	cpu_arm925_cache_clean_invalidate_all_r2
+
+	bic	r1, r1, #ICACHELINESIZE - 1
+	add	r1, r1, #ICACHELINESIZE
+
+1:	mcr	p15, 0, r0, c7, c5, 1		@ Clean I entry
+	mcr	p15, 0, r0, c7, c10, 1		@ Clean D entry
+	add	r0, r0, #ICACHELINESIZE
+	subs	r1, r1, #ICACHELINESIZE
+	bne	1b
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+
+ENTRY(cpu_arm925_icache_invalidate_page)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
+        nop
+        nop
+        nop
+        nop
+	mov	pc, lr
+
+/* ================================== TLB ================================= */
+
+/*
+ * cpu_arm925_tlb_invalidate_all()
+ *
+ * Invalidate all TLB entries
+ */
+	.align	5
+ENTRY(cpu_arm925_tlb_invalidate_all)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I & D TLBs
+	mov	pc, lr
+
+/*
+ * cpu_arm925_tlb_invalidate_range(start, end)
+ *
+ * invalidate TLB entries covering the specified range
+ *
+ * start: range start address
+ * end:   range end address
+ */
+	.align	5
+ENTRY(cpu_arm925_tlb_invalidate_range)
+	sub	r3, r1, r0
+	cmp	r3, #256 * PAGESIZE		@ arbitary, should be tuned
+	bhi	cpu_arm925_tlb_invalidate_all
+	
+	mov	r3, #0
+	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
+
+	bic	r0, r0, #(PAGESIZE - 1) & 0x00ff
+	bic	r0, r0, #(PAGESIZE - 1) & 0xff00
+
+1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
+	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
+	add	r0, r0, #PAGESIZE
+	cmp	r0, r1
+	blo	1b
+	mov	pc, lr
+
+/*
+ * cpu_arm925_tlb_invalidate_page(page, flags)
+ *
+ * invalidate the TLB entries for the specified page.
+ *
+ * page:  page to invalidate
+ * flags: non-zero if we include the I TLB
+ */
+	.align	5
+ENTRY(cpu_arm925_tlb_invalidate_page)
+	mov	r3, #0
+	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
+	teq	r1, #0
+	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
+	mcrne	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
+	mov	pc, lr
+
+/* =============================== PageTable ============================== */
+
+/*
+ * cpu_arm925_set_pgd(pgd)
+ *
+ * Set the translation base pointer to be as described by pgd.
+ *
+ * pgd: new page tables
+ */
+	.align	5
+ENTRY(cpu_arm925_set_pgd)
+	mov	ip, #0
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I & D cache
+#else
+/*
+ * 'Clean & Invalidate whole DCache'
+ * Re-written to use Index Ops.
+ * NOTE: Requires TI925T Configuration Register C bit <- 0
+ *       for clean and invalidate of both D-Cache sets.
+ */
+	mov	r3, #255 << 4		@ 256 entries/set
+					@ ((NSETS - 1) << (CIR[13-12] + 3))
+2:	mcr	p15, 0, r3, c7, c14, 2	@ clean & invalidate D index
+	subs	r3, r3, #1 << 4
+	bcs	2b			@ entries 255 to 0
+#endif
+	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
+	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
+	mov	pc, lr
+
+/*
+ * cpu_arm925_set_pmd(pmdp, pmd)
+ *
+ * Set a level 1 translation table entry, and clean it out of
+ * any caches such that the MMUs can load it correctly.
+ *
+ * pmdp: pointer to PMD entry
+ * pmd:  PMD value to store
+ */
+	.align	5
+ENTRY(cpu_arm925_set_pmd)
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+	eor	r2, r1, #0x0a			@ C & Section
+	tst	r2, #0x0b
+	biceq	r1, r1, #4			@ clear bufferable bit
+#endif
+	str	r1, [r0]
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm925_set_pte(ptep, pte)
+ *
+ * Set a PTE and flush it out
+ */
+	.align	5
+ENTRY(cpu_arm925_set_pte)
+	str	r1, [r0], #-1024		@ linux version
+
+	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+
+	bic	r2, r1, #0xff0
+	bic	r2, r2, #3
+	orr	r2, r2, #HPTE_TYPE_SMALL
+
+	tst	r1, #LPTE_USER | LPTE_EXEC	@ User or Exec?
+	orrne	r2, r2, #HPTE_AP_READ
+
+	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #HPTE_AP_WRITE
+
+	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	movne	r2, #0
+
+#ifdef CONFIG_CPU_ARM925_WRITETHROUGH
+	eor	r3, r2, #0x0a			@ C & small page?
+	tst	r3, #0x0b
+	biceq	r2, r2, #4
+#endif
+	str	r2, [r0]			@ hardware version
+	mov	r0, r0
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+@	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I & D TLBs
+	mov	pc, lr
+
+
+cpu_manu_name:
+	.asciz	"ARM/TI925"
+ENTRY(cpu_arm925_name)
+	.ascii	"Arm925T"
+#if defined(CONFIG_CPU_ARM925_CPU_IDLE)
+	.ascii	"s"
+#endif
+#if defined(CONFIG_CPU_ARM925_I_CACHE_ON)
+	.ascii	"i"
+#endif
+#if defined(CONFIG_CPU_ARM925_D_CACHE_ON)
+	.ascii	"d"
+#if defined(CONFIG_CPU_ARM925_WRITETHROUGH)
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+
+ENTRY(cpu_arm915_name)
+	.ascii	"Arm915T"
+#if defined(CONFIG_CPU_ARM925_CPU_IDLE)
+	.ascii	"s"
+#endif
+#if defined(CONFIG_CPU_ARM925_I_CACHE_ON)
+	.ascii	"i"
+#endif
+#if defined(CONFIG_CPU_ARM925_D_CACHE_ON)
+	.ascii	"d"
+#if defined(CONFIG_CPU_ARM925_WRITETHROUGH)
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+__arm925_setup:
+	mov	r0, #0
+#if defined(CONFIG_CPU_ARM925_NON_STREAMING_ON)
+        orr     r0,r0,#0x80
+#endif
+#if defined(CONFIG_CPU_ARM925_TRANSPARENT_ON)
+        orr     r0,r0,#0x2
+#endif
+	mcr	p15, 0, r0, c15, c1, 0		@ write TI config register
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
+	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
+	mcr	p15, 0, r4, c2, c0		@ load page table pointer
+	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
+	mov	r0, #0x1f			@ Domains 0, 1 = client
+	mcr	p15, 0, r0, c3, c0		@ load domain access register
+	mrc	p15, 0, r0, c1, c0		@ get control register v4
+/*
+ * Clear out 'unwanted' bits (then put them in if we need them)
+ */
+						@   VI ZFRS BLDP WCAM
+	bic	r0, r0, #0x0e00
+	bic	r0, r0, #0x0002
+	bic	r0, r0, #0x000c
+	bic	r0, r0, #0x1000			@ ...0 000. .... 000.
+/*
+ * Turn on what we want
+ */
+	orr	r0, r0, #0x0031
+	orr	r0, r0, #0x2100			@ ..1. ...1 ..11 ...1
+
+#ifdef CONFIG_CPU_ARM925_WRITEBUFFER_ON
+	orr	r0, r0, #0x0008			@ .... .... .... 1...
+#endif
+#ifdef CONFIG_CPU_ARM925_D_CACHE_ON
+	orr	r0, r0, #0x0004			@ .... .... .... .1..
+#endif
+#ifdef CONFIG_CPU_ARM925_I_CACHE_ON
+	orr	r0, r0, #0x1000			@ ...1 .... .... ....
+#endif
+	mov	pc, lr
+
+	.text
+
+/*
+ * Purpose : Function pointers used to access above functions - all calls
+ *	     come through these
+ */
+	.type	arm925_processor_functions, #object
+arm925_processor_functions:
+	.word	cpu_arm925_data_abort
+	.word	cpu_arm925_check_bugs
+	.word	cpu_arm925_proc_init
+	.word	cpu_arm925_proc_fin
+	.word	cpu_arm925_reset
+	.word   cpu_arm925_do_idle
+
+	/* cache */
+	.word	cpu_arm925_cache_clean_invalidate_all
+	.word	cpu_arm925_cache_clean_invalidate_range
+	.word	cpu_arm925_flush_ram_page
+
+	/* dcache */
+	.word	cpu_arm925_dcache_invalidate_range
+	.word	cpu_arm925_dcache_clean_range
+	.word	cpu_arm925_dcache_clean_page
+	.word	cpu_arm925_dcache_clean_entry
+
+	/* icache */
+	.word	cpu_arm925_icache_invalidate_range
+	.word	cpu_arm925_icache_invalidate_page
+
+	/* tlb */
+	.word	cpu_arm925_tlb_invalidate_all
+	.word	cpu_arm925_tlb_invalidate_range
+	.word	cpu_arm925_tlb_invalidate_page
+
+	/* pgtable */
+	.word	cpu_arm925_set_pgd
+	.word	cpu_arm925_set_pmd
+	.word	cpu_arm925_set_pte
+	.size	arm925_processor_functions, . - arm925_processor_functions
+
+	.type	cpu_arm925_info, #object
+cpu_arm925_info:
+	.long	cpu_manu_name
+	.long	cpu_arm925_name
+	.size	cpu_arm925_info, . - cpu_arm925_info
+
+	.type	cpu_arm915_info, #object
+cpu_arm915_info:
+	.long	cpu_manu_name
+	.long	cpu_arm915_name
+	.size	cpu_arm915_info, . - cpu_arm915_info
+
+	.type	cpu_arch_name, #object
+cpu_arch_name:
+	.asciz	"armv4"
+	.size	cpu_arch_name, . - cpu_arch_name
+
+	.type	cpu_elf_name, #object
+cpu_elf_name:
+	.asciz	"v4"
+	.size	cpu_elf_name, . - cpu_elf_name
+	.align
+
+#if	defined(CONFIG_CPU_ARM925_WRITETHROUGH)
+#  define	MMU_FLAGS	0x00000c1a
+#else
+#  define	MMU_FLAGS	0x00000c1e
+#endif
+	.section ".proc.info", #alloc, #execinstr
+
+	.type	__arm925_proc_info,#object
+__arm925_proc_info:
+	.long	0x54029252
+	.long	0xffffffff
+	.long	MMU_FLAGS
+	b	__arm925_setup
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
+	.long	cpu_arm925_info
+	.long	arm925_processor_functions
+	.size	__arm925_proc_info, . - __arm925_proc_info
+
+	.type	__arm915_proc_info,#object
+__arm915_proc_info:
+	.long	0x54029152
+	.long	0xffffffff
+	.long	MMU_FLAGS
+	b	__arm925_setup
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
+	.long	cpu_arm915_info
+	.long	arm925_processor_functions
+	.size	__arm925_proc_info, . - __arm925_proc_info
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/arch/arm/tools/mach-types linux-2.4.19/arch/arm/tools/mach-types
--- ../linux-2.4.19-rmk4-vanilla/arch/arm/tools/mach-types	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/arch/arm/tools/mach-types	2003-01-09 19:49:04.000000000 +0200
@@ -249,3 +249,5 @@
 pxa_eagle250		ARCH_PXA_EAGLE250	PXA_EAGLE250		238
 pdb			ARCH_PDB		PDB			239
 blue_2g			SA1100_BLUE_2G		BLUE_2G			240
+innovator		OMAP_INNOVATOR		INNOVATOR		254
+perseus			OMAP_PERSEUS		PERSEUS			255
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/Config.in linux-2.4.19/drivers/char/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/Config.in	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/char/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -112,6 +112,17 @@
    bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
 fi
 
+if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+   dep_tristate 'OMAP710 Keypad' CONFIG_OMAP710_KEYPAD $CONFIG_ARCH_OMAP710
+   dep_tristate 'OMAP1510 Keypad' CONFIG_OMAP1510_KEYPAD $CONFIG_ARCH_OMAP1510
+   dep_tristate 'OMAP1510 Touchscreen support' CONFIG_OMAP1510_TOUCHSCREEN $CONFIG_ARCH_OMAP1510
+   dep_tristate 'OMAP1510 HID' CONFIG_OMAP1510_HID $CONFIG_ARCH_OMAP1510
+#   if [ "$CONFIG_OMAP1510_HID" = "y" -o "$CONFIG_OMAP1510_HID" = "m" ]; then
+#      dep_tristate 'OMAP1510 Keyboard support' CONFIG_OMAP1510_KEYBOARD $CONFIG_OMAP1510_HID $CONFIG_ARCH_OMAP1510
+#      dep_tristate 'OMAP1510 Mouse support' CONFIG_OMAP1510_MOUSE $CONFIG_OMAP1510_HID $CONFIG_ARCH_OMAP1510
+#   fi
+fi
+
 source drivers/serial/Config.in
 
 if [ "$CONFIG_ARCH_ANAKIN" = "y" ]; then
@@ -130,6 +141,10 @@
    dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
 fi
 
+if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+   dep_tristate 'OMAP1510 Hardware Error IRQ' CONFIG_OMAP1510_HWERROR $CONFIG_ARCH_OMAP1510
+fi
+
 source drivers/i2c/Config.in
 
 if [ "$CONFIG_I2C" != "n" ]; then
@@ -188,6 +203,7 @@
       dep_tristate '  NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG $CONFIG_ARCH_NETWINDER
       dep_tristate '  SA1100 watchdog' CONFIG_SA1100_WATCHDOG $CONFIG_ARCH_SA1100
       dep_tristate '  Omaha watchdog' CONFIG_OMAHA_WATCHDOG $CONFIG_ARCH_OMAHA
+      dep_tristate '  OMAP1510 Watchdog driver' CONFIG_OMAP1510_WATCHDOG $CONFIG_ARCH_OMAP1510
    fi
    tristate '  Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
    tristate '  IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
@@ -242,6 +258,9 @@
 if [ "$CONFIG_ARCH_OMAHA" = "y" ]; then
    tristate 'Omaha Real Time Clock' CONFIG_OMAHA_RTC
 fi
+if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+        dep_tristate 'OMAP710 RTC' CONFIG_OMAP710_RTC $CONFIG_ARCH_OMAP710
+fi
 
 tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
 tristate 'Siemens R3964 line discipline' CONFIG_R3964
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/Makefile linux-2.4.19/drivers/char/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/char/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -103,6 +103,15 @@
   ifeq ($(CONFIG_ARCH_FORTUNET),y)
     KEYMAP   := defkeymap.o
   endif
+  ifeq ($(CONFIG_ARCH_OMAP1510),y)
+    list-multi	+= keypad.o
+    keypad_objs	:= omap1510_keypad.o
+    obj-$(CONFIG_OMAP1510_KEYPAD)	+= keypad.o
+    list-multi	+= juno_hid.o
+    juno_objs 	:= omap1510_hid.o omap1510_ps2.o omap1510_spi.o
+    obj-$(CONFIG_OMAP1510_HID)	+= juno_hid.o
+    obj-$(CONFIG_OMAP1510_TOUCHSCREEN)	+= omap1510_tsdev.o
+  endif
 endif
 
 ifeq ($(ARCH),sh)
@@ -230,6 +239,7 @@
 obj-$(CONFIG_EFI_RTC) += efirtc.o
 obj-$(CONFIG_SA1100_RTC) += sa1100-rtc.o
 obj-$(CONFIG_OMAHA_RTC) += omaha-rtc.o
+obj-$(CONFIG_OMAP710_RTC) += omap710_rtc.o
 ifeq ($(CONFIG_PPC),)
   obj-$(CONFIG_NVRAM) += nvram.o
 endif
@@ -290,6 +300,7 @@
 obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
 obj-$(CONFIG_OMAHA_WATCHDOG) += omaha_wdt.o
 obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
+obj-$(CONFIG_OMAP1510_WATCHDOG) += omap1510_wdt.o
 
 # I2C char devices
 obj-$(CONFIG_I2C_DS1307) += ds1307.o
@@ -305,6 +316,8 @@
 obj-y		+= ../acorn/char/acorn-char.o
 endif
 
+obj-$(CONFIG_OMAP1510_HWERROR) += omap1510_hwerror.o
+
 include $(TOPDIR)/Rules.make
 
 fastdep:
@@ -324,3 +337,12 @@
 
 qtronixmap.c: qtronixmap.map
 	set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
+
+# OMAP HID support:
+juno_hid.o: $(juno_objs)
+	$(LD) -r -o $@ $(juno_objs)
+
+keypad.c: keypad.o
+
+keypad.o: $(keypad_objs)
+	$(LD) -r -o $@ $(keypad_objs)
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hid.c linux-2.4.19/drivers/char/omap1510_hid.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hid.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_hid.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,438 @@
+/*
+ * File: omap1510_hid.c
+ *
+ * The USAR driver layer for the HID (Human Input Device) controller 
+ *   for the TI P1.
+ *  
+ * This layer sends and recvs commands to the JUNO part and provides 
+ *   JUNO Layer error checking.  The caller must parse the command.
+ *
+ * REFERENCES
+ *   Technical Reference Manual USAR Juno: UR8HC007-001 Jupiter class 
+ *   HID & Power Management Control
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Alex McMains <aam@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include "omap1510_hid.h"
+
+#undef DEBUG
+#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...) ;
+#  define ENTRY() ;
+#endif
+
+extern void spi_snd_packet(u8 *databyte, u8 num_bytes);
+extern void spi_rcv_packet(u8 *buffer, u8 *num_bytes);
+
+// calculate the longitudinal Redundancy Check
+static u8 calculate_LRC(char *buffer, int size)
+{
+        char LRC;
+        int index;
+
+        // Init the LRC using the first two message u8s
+        LRC = buffer[0] ^ buffer[1];
+  
+        // Update the LRC using the remainder of the bufffer
+        for ( index = 2; index < size; index++ )
+                LRC ^= buffer[index];
+
+        // If the MSB is set then clear the MSB and change the next most 
+        // significant bit
+        if ( LRC & 0x80 )
+                LRC ^= 0xC0;
+
+        return LRC;
+}
+
+// calculate the longitudinal Redundancy Check
+static u8 calculate_block_LRC(char *buffer, char *block, u8 size)
+{
+        char LRC;
+        int index;
+
+        // Init the LRC using the first two message u8s
+        LRC = buffer[0] ^ buffer[1];
+        LRC ^= buffer[2];
+  
+        // Update the LRC using the block
+        for ( index = 0; index < size; index++ )
+                LRC ^= block[index];
+  
+        // If the MSB is set then clear the MSB and change the next most 
+        // significant bit
+        if ( LRC & 0x80 )
+                LRC ^= 0xC0;
+
+        return LRC;
+}
+
+// host commands 
+static int hcmd_simple(st_simple *simple, u8 cmd_code)
+{
+        simple->header   = SIMPLE;
+        simple->cmd_code = cmd_code;
+        simple->LRC      = calculate_LRC((char*)simple, 2);
+
+        return 0;
+}
+ 
+static int hcmd_write_register_bit(st_write_register_bit *write_bit, 
+                                   u8 reg_offset, u8 bit, u8 value)
+{
+        u8 value_bit = 0;
+  
+        write_bit->header     = WRITE_REGISTER_BIT;
+        write_bit->reg_offset = reg_offset;
+
+        value_bit = bit;
+        value_bit <<= 1;
+
+        if ( value )
+                value_bit |= 0x1;
+
+        write_bit->value_bit  = value_bit;
+        write_bit->LRC        = calculate_LRC((char*)write_bit, 3);
+
+        return 0;
+}
+
+static int hcmd_read_register_bit(st_read_register_bit *read_bit, 
+                                  u8 reg_offset, u8 bit)
+{
+        read_bit->header     = READ_REGISTER_BIT;
+        read_bit->reg_offset = reg_offset;
+        read_bit->bit        = bit;
+        read_bit->LRC        = calculate_LRC((char*)read_bit, 3);
+
+        return 0;
+}
+
+static int hcmd_write_register(st_write_register *write_reg, u8 reg_offset,
+                               u8 value)
+{
+        write_reg->header     = WRITE_REGISTER;
+        write_reg->reg_offset = reg_offset;
+        write_reg->value      = value;
+        write_reg->LRC        = calculate_LRC((char*)write_reg, 3);
+
+        return 0;
+}
+
+static int hcmd_read_register(st_read_register *read_reg, u8 reg_offset)
+{
+        read_reg->header     = READ_REGISTER;
+        read_reg->reg_offset = reg_offset;
+        read_reg->LRC        = calculate_LRC((char*)read_reg, 2);
+
+        return 0;
+}
+
+static int hcmd_write_block(st_write_block *write_block, u8 reg_offset, 
+                            u8 block_length, u8 *block)
+{
+        int i;
+
+        write_block->header       = WRITE_BLOCK;
+        write_block->reg_offset   = reg_offset;
+        write_block->block_length = block_length;
+
+        for ( i = 0; i < block_length; i++ )
+                write_block->block[i] = block[i];
+
+        if ( block_length == 32 )
+                write_block->LRC = calculate_block_LRC((char*)write_block, 
+                                                       block, block_length);
+        else
+                write_block->block[block_length] = 
+                        calculate_block_LRC((char*)write_block, block, 
+                                            block_length);
+
+        return 0;
+}
+
+// NOTE: untested
+static int hcmd_read_block(st_read_block *read_block, u8 reg_offset, 
+                           u8 block_length, u8 *block)
+{
+        int i;
+
+        read_block->header       = READ_BLOCK;
+        read_block->reg_offset   = reg_offset;
+        read_block->block_length = block_length;
+
+        for ( i = 0; i < block_length; i++ )
+                read_block->block[i] = block[i];
+
+        if ( block_length == 32 )
+                read_block->LRC = calculate_block_LRC((char*)read_block, 
+                                                      block, block_length);
+        else
+                read_block->block[block_length] = 
+                        calculate_block_LRC((char*)read_block, block, 
+                                            block_length);
+
+
+        return 0;
+}
+
+// controller responses
+static int cres_simple(st_simple *simple, u8 nbytes)
+{
+        u8 LRC;
+
+        if ( nbytes == 0 )
+                return -E_ZERO_BYTES;
+
+        if ( simple->header != SIMPLE )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_LRC((char*)simple, 2);
+
+        if ( LRC != simple->LRC )
+                return -E_BAD_LRC;
+
+        return 0;
+}
+
+static int cres_report_register_bit(st_report_register_bit *report_bit, 
+                                    u8 nbytes, u8 data)
+{
+        u8 LRC;
+ 
+        if ( nbytes == 0 )
+                return -E_ZERO_BYTES;
+
+        if ( report_bit->header != REPORT_REGISTER_BIT )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_LRC((char*)report_bit, 3);
+
+        if ( LRC != report_bit->LRC )
+                return -E_BAD_LRC;
+
+        if ( report_bit->value_bit != data )
+                return -E_BAD_VALUE;
+
+        return 0;
+}
+
+static int cres_report_register(st_report_register *report_reg, u8 nbytes, 
+                                u8 data)
+{
+        u8 LRC;
+
+        if ( nbytes == 0 )
+                return -E_ZERO_BYTES;
+
+        if ( report_reg->header != REPORT_REGISTER )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_LRC((char*)report_reg, 3);
+
+        if ( LRC != report_reg->LRC )
+                return -E_BAD_LRC;
+
+        if ( report_reg->value != data )
+                return -E_BAD_VALUE;
+
+        return 0;
+}
+
+static int cres_report_block(st_report_block *report_block, u8 nbytes)
+{
+        u8 LRC;
+
+        if ( nbytes == 0 )
+                return -E_ZERO_BYTES;
+
+        if ( report_block->header != REPORT_BLOCK )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_block_LRC((char*)report_block, report_block->block, 
+                                  report_block->block_length);
+
+        if ( report_block->block_length == 32 )
+        {
+                if ( LRC != report_block->LRC )
+                        return -E_BAD_LRC;
+                else if ( LRC != 
+                          report_block->block[report_block->block_length] )
+                        return -E_BAD_LRC;
+        }
+
+        return 0;
+}
+
+static int cres_pointing_report(st_pointing_report *pointing, u8 nbytes)
+{
+        u8 LRC;
+
+        if ( pointing->header != POINTING_REPORT )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_LRC((char*)pointing, 5);
+
+        if ( LRC != pointing->LRC )
+                return -E_BAD_LRC;
+
+        return POINTING_REPORT;
+}
+
+static int cres_keyboard_report(st_keyboard_report *keyboard) 
+{
+        u8 LRC;
+
+        if ( keyboard->header != KEYBOARD_REPORT )
+                return -E_BAD_HEADER;
+
+        LRC = calculate_LRC((char*)keyboard, 2);
+
+        if ( LRC != keyboard->LRC )
+                return -E_BAD_LRC;
+
+        return KEYBOARD_REPORT;
+}
+
+static int report_type(u8 *type)
+{
+        // check the header to find out what kind of report it is
+        if ( (*type) == KEYBOARD_REPORT )
+                return KEYBOARD_REPORT;
+        else if ( (*type) == POINTING_REPORT )
+                return POINTING_REPORT;
+        else return -E_BAD_HEADER;
+}
+
+void send_juno_command(u8 type, u8 reg_offset, u8 data1, u8 data2,
+                       int length, u8 *block)
+{
+        st_simple simple;
+        st_write_register_bit write_bit;
+        st_read_register_bit read_bit;
+        st_write_register write_reg;
+        st_read_register read_reg;
+        st_write_block write_block;
+        st_read_block read_block;
+
+        switch ( type )
+        {
+        case SIMPLE:
+                hcmd_simple(&simple, data1);
+                spi_snd_packet((u8 *)&simple, SIZE_SIMPLE);
+                break;
+        case WRITE_REGISTER_BIT:
+                hcmd_write_register_bit(&write_bit, reg_offset, data1, data2);
+                spi_snd_packet((u8 *)&write_bit, SIZE_WRITE_BIT);
+                break;
+        case READ_REGISTER_BIT:
+                hcmd_read_register_bit(&read_bit, reg_offset, data1);
+                spi_snd_packet((u8 *)&read_bit, SIZE_READ_BIT);
+                break;
+        case WRITE_REGISTER:
+                hcmd_write_register(&write_reg, reg_offset, data1);
+                spi_snd_packet((u8 *)&write_reg, SIZE_WRITE_REGISTER);
+                break;
+        case READ_REGISTER:
+                hcmd_read_register(&read_reg, reg_offset);
+                spi_snd_packet((u8 *)&read_reg, SIZE_READ_REGISTER);
+                break;
+        case WRITE_BLOCK:
+                hcmd_write_block(&write_block, reg_offset, length, block);
+                spi_snd_packet((u8 *)&write_block, 
+                               length + SIZE_WRITE_BLOCK);
+                break;
+        case READ_BLOCK:
+                hcmd_read_block(&read_block, reg_offset, length, block);
+                spi_snd_packet((u8 *)&read_block, length + SIZE_READ_BLOCK);
+                break;
+        default:
+                printk("Unrecognized command: %d\n", type);
+        }
+}
+
+int receive_juno_response(u8 type, u8 *buffer, u8 *nbytes, u8 data)
+{
+        int ret = 0;
+
+        switch ( type )
+        {
+        case SIMPLE:
+                spi_rcv_packet(buffer, nbytes);
+                ret = cres_simple((st_simple *)buffer, *nbytes);
+                break;
+        case REPORT_REGISTER_BIT:
+                spi_rcv_packet(buffer, nbytes);
+                ret = cres_report_register_bit(
+                        (st_report_register_bit *)buffer, *nbytes, data);
+                break;
+        case REPORT_REGISTER:
+                spi_rcv_packet(buffer, nbytes);
+                ret = cres_report_register((st_report_register *)buffer, 
+                                           *nbytes, data);
+                break;
+        case REPORT_BLOCK:
+                spi_rcv_packet(buffer, nbytes);
+                ret = cres_report_block((st_report_block *)buffer, *nbytes);
+                break;        
+        case ASYNC_REPORT:
+                spi_rcv_packet(buffer, nbytes);
+
+                if ( report_type(buffer) == POINTING_REPORT )
+                        ret = cres_pointing_report((st_pointing_report *)buffer, 
+                                                   *nbytes);
+                else if ( report_type(buffer) == KEYBOARD_REPORT )
+                        ret = cres_keyboard_report((st_keyboard_report *)buffer);
+                else 
+                        ret = -1;
+
+                break;
+
+        default:
+                printk("Unrecognized command: %d\n", type);
+        }
+
+        return ret;
+}
+
+/*
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hid.h linux-2.4.19/drivers/char/omap1510_hid.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hid.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_hid.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,221 @@
+/*
+ * File: omap1510_hid.h
+ *
+ * The USAR driver layer for the HID (Human Input Device) controller 
+ *   for the TI P1
+ *
+ * REFERENCES
+ *   Technical Reference Manual USAR Juno: UR8HC007-001 Jupiter class 
+ *   HID & Power Management Control
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Alex McMains <aam@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ *  key: RRGPLCR (do not remove)
+ *
+ */
+
+/* 
+   The registers are divided into two pages where each page contains 255 
+   registers:
+       Page 0: Configuration Control and Status
+       Page 1: Scanned Matrix and Alternate Layout Keys
+*/
+
+#ifndef __HID_H__
+#define __HID_H__
+
+#include <linux/types.h>
+
+// struct sizes since they are being padded
+#define SIZE_SIMPLE         3
+#define SIZE_WRITE_BIT      4
+#define SIZE_READ_BIT       4
+#define SIZE_WRITE_REGISTER 4
+#define SIZE_READ_REGISTER  3
+#define SIZE_WRITE_BLOCK    4
+#define SIZE_READ_BLOCK     4
+
+// Shared protocol header
+#define SIMPLE              0x80
+
+// Protocol Headers for HOST issued commands
+#define WRITE_REGISTER_BIT  0x81
+#define READ_REGISTER_BIT   0x82
+#define WRITE_REGISTER      0x83
+#define READ_REGISTER       0x84
+#define WRITE_BLOCK         0x85
+#define READ_BLOCK          0x86
+
+// Protocol Headers for CONTROLLER issued responses
+#define REPORT_REGISTER_BIT 0x81
+#define REPORT_REGISTER     0x83
+#define REPORT_BLOCK        0x85
+#define POINTING_REPORT     0x87
+#define KEYBOARD_REPORT     0x88
+#define ASYNC_REPORT        0x99 // this is not a valid Juno HID protocol header
+
+// Simple Commands
+#define INITIALIZE              0x00
+#define INITIALIZATION_COMPLETE 0x01
+#define RESEND_REQUEST          0x05
+
+#define PAGE_NUMBER 0xFF // changes pages, accepts 0 or 1
+
+// Errors 
+#define E_BAD_HEADER    1
+#define E_BAD_LRC       2
+#define E_ZERO_BYTES    3
+#define E_BAD_VALUE     4
+#define E_BAD_MODE      5
+#define E_REPORT_MODE   6
+#define E_BAD_ACK       7
+#define E_BAD_DEVICE_ID 8
+
+// Registers
+#define GPE_STATUS_0_REGISTER              20
+#define PS2_DEVICE_DIRECT_CONTROL_REGISTER 22
+#define CONTROL_REGISTER                   128
+#define HOST_TRANSMIT_REGISTER             129
+
+// Values
+#define IP_CON            0x04 // internal PS/2 device connect
+#define REP_MODE          0x80 // report mode turned on
+#define PS2_DEVICE_ENABLE 0x01
+#define SET_SAMPLING_RATE 0xf3
+#define REPORS_60         0x3c
+#define REPORS_80         0x50
+#define REPORS_100        0x64
+#define READ_DEVICE_TYPE  0xf2
+#define VALID_DEVICE_ID   0x10
+#define MODE_ACK          0xfa
+
+typedef struct _st_simple
+{
+  u8 header;
+  u8 cmd_code;
+  u8 LRC; 
+} st_simple __attribute__ ((packed));
+
+// host command structures
+typedef struct _st_write_register_bit
+{
+  u8 header;
+  u8 reg_offset;
+  u8 value_bit;
+  u8 LRC;
+} st_write_register_bit __attribute__ ((packed));
+ 
+typedef struct _st_read_register_bit
+{
+  u8 header;
+  u8 reg_offset;
+  u8 bit;
+  u8 LRC;
+} st_read_register_bit __attribute__ ((packed));
+
+typedef struct _st_write_register
+{
+  u8 header;
+  u8 reg_offset;
+  u8 value;
+  u8 LRC;
+} st_write_register __attribute__ ((packed));
+
+typedef struct _st_read_register
+{
+  u8 header;
+  u8 reg_offset;
+  u8 LRC;
+} st_read_register __attribute__ ((packed));
+
+typedef struct _st_write_block
+{
+  u8 header;
+  u8 reg_offset;
+  u8 block_length;
+  u8 block[32];
+  u8 LRC;
+} st_write_block __attribute__ ((packed));
+
+typedef struct _st_read_block
+{
+  u8 header;
+  u8 reg_offset;
+  u8 block_length;
+  u8 block[32];
+  u8 LRC;
+} st_read_block __attribute__ ((packed));
+
+// controller command structures
+typedef struct _st_report_register_bit
+{
+  u8 header;
+  u8 reg_offset;
+  u8 value_bit;
+  u8 LRC;
+} st_report_register_bit __attribute__ ((packed));
+ 
+typedef struct _st_report_register
+{
+  u8 header;
+  u8 reg_offset;
+  u8 value;
+  u8 LRC;
+} st_report_register __attribute__ ((packed));
+
+typedef struct _st_report_block
+{
+  u8 header;
+  u8 reg_offset;
+  u8 block_length;
+  u8 block[32];
+  u8 LRC;
+} st_report_block __attribute__ ((packed));
+
+typedef struct _st_pointing_report
+{
+  u8 header;
+  u8 buttons;
+  u8 Xdisplacement;
+  u8 Ydisplacement;
+  u8 Zdisplacement;
+  u8 LRC;
+} st_pointing_report __attribute__ ((packed));
+
+typedef struct _st_keyboard_report
+{
+  u8 header;
+  u8 keynum; // up > 0x80, down < 0x7E, all keys up 0x00
+  u8 LRC;
+} st_keyboard_report __attribute__ ((packed));
+
+#endif
+
+/*---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hwerror.c linux-2.4.19/drivers/char/omap1510_hwerror.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_hwerror.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_hwerror.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,74 @@
+/*
+ * File: hwerror.c
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon glonnon@ridgerun.com 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/ptrace.h>
+#include <linux/interrupt.h>
+//#include <linux/irq.h>
+#include <asm/irq.h>
+
+static int hw_error_count;
+static void hw_error_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+        hw_error_count++;
+        if(hw_error_count % 10)
+                printk(__FUNCTION__ ":entry");
+}
+void install_hw_error_irq(void) {
+        request_irq(INT_HW_ERRORS, hw_error_interrupt,
+                    0, "hw error",
+                    NULL);
+}
+static int __init omap1510_hwerror_init(void) {
+        printk(KERN_INFO "DSPLinux hw error monitor (c) 2001 RidgeRun, Inc.\n");
+        install_hw_error_irq();
+        hw_error_count = 0;
+        return 0;
+}
+static void __exit omap1510_hwerror_exit(void) {
+
+}
+module_init(omap1510_hwerror_init);
+module_exit(omap1510_hwerror_exit);
+
+MODULE_AUTHOR("Greg Lonnon <glonnon@rigderun.com>");
+MODULE_DESCRIPTION("DSPLinux HW Error IRQ");
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_keypad.c linux-2.4.19/drivers/char/omap1510_keypad.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_keypad.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_keypad.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,295 @@
+/*
+ * File: keypad.c
+ *
+ * omap1510 keypad driver
+ * 
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...)
+#  define ENTRY()
+#endif
+
+#define ARMIO_KBD_DCR     OMAP1510_ARMIO_BASE + 0x10
+#define ARMIO_KBD_DOR     OMAP1510_ARMIO_BASE + 0x8
+#define ARMIO_KBD_IMR     OMAP1510_ARMIO_BASE + 0x20
+#define ARMIO_KBD_ICR     OMAP1510_ARMIO_BASE + 0x18
+
+#define ARMIO_KBD_MASKIT  (OMAP1510_ARMIO_BASE + 0x28)
+#define ARMIO_KBD_LATCH   (OMAP1510_ARMIO_BASE + 0x10)  
+#define ARMIO_KBD_ROW     ARMIO_KBD_LATCH
+#define ARMIO_KBD_REG     (OMAP1510_ARMIO_BASE + 0x14) 
+#define ARMIO_KBD_COL     ARMIO_KBD_REG
+#define GPIO_DEBOUNCING_REG  OMAP1510_ARMIO_BASE + 0x30
+
+static struct timer_list timer;
+
+#define KP_ROWS	5
+#define KP_COLS	6
+
+#define KEYPAD_DEBOUNCE_TIME 25
+
+/*
+const char keypad_map[KP_ROWS * KP_COLS] =
+{                             // Electrical & physical
+  'c','-',' ','^',' ',' ',    // row 0 (highest)
+  '1','2','*','3',' ',' ',    // row 1
+  '7','8','0','9',' ',' ',    // row 2
+  '4','5','#','6',' ',' ',    // row 3
+  '<','>',' ','v',' ',' ',    // row 4 (lowest)
+};
+*/
+
+/* Notes on the following table:
+ * The numbers correspond to the correct scan codes.  
+ *
+ * The * and # are handled the following way: 
+ *  a * is considered to be shift+8 and a # is shift+3.
+ *  The shift scancodes are 2a (left) and 36 (right).
+ *  Since we only have two of these anomalies to deal with
+ *  now, i return a left shift for * and a right shift for #.
+ *
+ * The arrow keys are also double coded.  They are all prefaced
+ *  by sending e0.  We just return the code sans e0.
+ */
+const char keypad_map[KP_ROWS * KP_COLS] =
+{                          // Electrical & physical
+        0x0e,0x0c,0x00,0x48,0x00,0x00, // row 0 (highest)
+        0x02,0x03,0x2a,0x04,0x00,0x00, // row 1
+        0x08,0x09,0x0b,0x0a,0x00,0x00, // row 2
+        0x05,0x06,0x36,0x07,0x00,0x00, // row 3
+        0x4b,0x4d,0x00,0x50,0x00,0x00, // row 4 (lowest)
+};
+
+static void do_omap1510_keypad_tasklet(unsigned long);
+
+DECLARE_TASKLET(omap1510_keypad_tasklet,do_omap1510_keypad_tasklet,0);
+
+void handle_scancode(unsigned char scancode, int down);
+
+#define ALL_COL_AT_ONE  (0xF << KP_ROWS)
+#define ALL_COL_AT_ZERO (~(0xF << KP_ROWS))
+
+static int omap1510_keypad_read(void)
+{
+        int row = 0;
+        int col = -1;
+        int ret;
+        int row_number;
+        int col_number;
+        int save_row=0x1F;
+        int read_row=0x1F;
+
+        save_row = inw(ARMIO_KBD_ROW) & 0x1F;
+
+        for (row_number=0 ; row_number<KP_ROWS ; row_number++) {
+                if ((inw(ARMIO_KBD_ROW) & (1<< row_number)) == 0) {
+                        row = row_number;
+                }
+        }
+        
+        for (col_number=0 ; col_number<KP_COLS ; col_number++) {
+                int loop_wait;
+                outw((1 << col_number) & 0x3f, ARMIO_KBD_COL);
+                // Wait for stable status
+                
+                udelay(1);
+                
+                read_row = inw(ARMIO_KBD_ROW) & 0x1F;  
+                DBG("save row %x read_row %x\n",save_row,read_row);
+                if (read_row != save_row) {  
+                        col = col_number;
+                }
+        }
+
+        if(row > KP_ROWS)
+                return -EINVAL;
+
+        if(col > KP_COLS)
+                return -EINVAL;
+
+        if ( col == -1 )
+                return -EINVAL;
+
+        ret = keypad_map[row * KP_ROWS + row + col];
+        
+        DBG("row %d col %d\n", row, col);
+
+        return ret;
+}
+
+static void handle_star(void)
+{
+        handle_scancode(0x2a, 1);
+        handle_scancode(0x09, 1);
+        handle_scancode(0x2a, 0);
+        handle_scancode(0x09, 0);
+}
+
+static void handle_sharp(void)
+{
+        handle_scancode(0x36, 1);
+        handle_scancode(0x04, 1);
+        handle_scancode(0x36, 0);
+        handle_scancode(0x04, 0);
+}
+
+static void handle_arrow(unsigned char key)
+{
+        handle_scancode(0xe0, 1);
+        handle_scancode(key, 1);
+        handle_scancode(0xe0, 0);
+        handle_scancode(key, 0);
+}
+
+static void do_omap1510_keypad_tasklet(unsigned long data)
+{ 
+        unsigned char key;
+        int ret;
+
+        ENTRY();
+        omap1510_keypad_tasklet.data = 1;
+
+        if ( data == 0 ) 
+        {  // this is an interrupt
+                ret = omap1510_keypad_read();
+                if ( ret < 0 )
+                        goto reset_timer;
+
+                key = (unsigned char) ret;
+                timer.data = (unsigned long) key;          
+                
+                if ( key == 0x2a )
+                        handle_star();
+                else if ( key == 0x36 )
+                        handle_sharp();
+                else if ( key >= 0x48 )
+                        handle_arrow(key);
+                else
+                {
+                        handle_scancode(key, 1);
+                        handle_scancode(key, 0);
+                }
+
+                DBG("key %c\n", key);
+        } 
+        else 
+        {  // this is a timer
+                data = timer.data;
+                key = omap1510_keypad_read();
+                if ( key == data ) 
+                {
+                        DBG("same key is still down, reset timer and go\n");
+                }
+                else 
+                {
+                        DBG("different key is down, turn on int\n");
+                        outw(0x0,ARMIO_KBD_MASKIT);                
+                        return;
+                }
+        }
+
+ reset_timer:
+        mod_timer(&timer, jiffies + KEYPAD_DEBOUNCE_TIME);
+        return;
+
+}
+static void omap1510_timer(unsigned long null) 
+{
+        ENTRY();
+        omap1510_keypad_tasklet.data = 1;
+        tasklet_schedule(&omap1510_keypad_tasklet);
+}
+static void omap1510_keypad_interrupt(int irq, void *dev_id, 
+                                      struct pt_regs *regs) 
+{
+        ENTRY();
+        outw(1,ARMIO_KBD_MASKIT);
+        omap1510_keypad_tasklet.data = 0;
+        tasklet_schedule(&omap1510_keypad_tasklet);
+}
+
+static int __init omap1510_keypad_init(void)
+{
+        ENTRY();
+        printk(KERN_INFO "DSPLinux keypad driver (c) 2001 RidgeRun, Inc.\n");
+
+        outw(0xff,GPIO_DEBOUNCING_REG);        
+        outw(0x1f,ARMIO_KBD_DCR);
+        outw(ALL_COL_AT_ONE, ARMIO_KBD_DOR);
+        outw(0xe0,ARMIO_KBD_IMR);
+        outw(0x1f,ARMIO_KBD_ICR);
+
+        timer.data = 0;
+        timer.function = omap1510_timer;
+
+        if ( request_irq(INT_KEYBOARD, omap1510_keypad_interrupt, 
+                         0, "keypad", 0) < 0 )
+		return -EINVAL;
+
+        return 0;
+}
+
+static void __exit omap1510_keypad_exit(void)
+{
+        ENTRY();
+
+        free_irq(INT_KEYBOARD, 0);
+
+        return;
+}
+
+module_init(omap1510_keypad_init);
+module_exit(omap1510_keypad_exit);
+
+MODULE_AUTHOR("Greg Lonnon <glonnon@rigderun.com>");
+MODULE_DESCRIPTION("DSPLinux OMAP1510 Keypad driver");
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_ps2.c linux-2.4.19/drivers/char/omap1510_ps2.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_ps2.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_ps2.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,921 @@
+/*
+ * File: omap1510_ps2.c
+ *
+ * The USAR driver layer for the HID (Human Input Device) controller 
+ *   for the TI P1
+ *
+ * REFERENCES
+ *   Technical Reference Manual USAR Juno UR8HC007-001: doc8-007-001-tr-072
+ *   Extended Protocol for PS/2 Pointing Devices: doc7-tsd-001-tr-080
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Alex McMains <aam@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <asm/arch/irqs.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include "omap1510_hid.h"
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...) ;
+#  define ENTRY() ;
+#endif
+
+extern void spi_snd_packet(u8 *databyte, u8 num_bytes);
+extern void spi_rcv_packet(u8 *buffer, u8 *num_bytes);
+extern int spi_init(void);
+extern unsigned long atn_high(void);
+extern void send_juno_command(u8 type, u8 reg_offset, u8 data1, u8 data2, 
+                              int length, u8 *block);
+extern int receive_juno_response(u8 type, u8 *buffer, u8 *nbytes, u8 data);
+
+// module_parm support values
+static int mouse = 0;
+static int kbd   = 0;
+static int ts    = 0;
+
+// used to handle e0 codes (except usar 100 & 101) 
+// i divided these codes arbitrarly to fit within two 32 bit numbers (AAM)
+static unsigned long int e0_codes1 = 0x030003ff;
+static unsigned long int e0_codes2 = 0x038e0a00;
+
+// i made this table using usar doc8-007-001-TR0-072 Appendix A
+// it converts usar numbers to XT PS2 scancodes (AAM)
+static unsigned char usar2scancode[128] =
+{
+	0x00, 0x29, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	0x18, 0x19, 0x1a, 0x1b, 0x2b, 0x1e, 0x1f, 0x20,
+	0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28,
+	0x1c, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32,
+	0x33, 0x34, 0x35, 0x39, 0x01, 0x52, 0x53, 0x4b,
+	0x47, 0x4f, 0x48, 0x50, 0x49, 0x51, 0x4d, 0x37,
+	0x4e, 0x4f, 0x50, 0x51, 0x4b, 0x4c, 0x4d, 0x47,	
+	0x48, 0x49, 0x52, 0x53, 0x4a, 0x1c, 0x35, 0x3b,
+	0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43,
+	0x44, 0x57, 0x58, 0x2a, 0x36, 0x38, 0x38, 0x1d,
+	0x1d, 0x3a, 0x45, 0x46, 0x2a, 0x1d, 0x5b, 0x5c,
+	0x5d, 0xff, 0x00, 0x00, 0x5e, 0x5f, 0x63, 0x70,
+	0x7b, 0x79, 0x7d, 0x73, 0x5b, 0x5c, 0x5d, 0x63, 
+	0x65, 0x66, 0x68, 0x69, 0x6b, 0x56, 0x54, 0x00
+};
+
+// from drivers/input/ps2serkbd.c
+static unsigned char ps2_kbd_keycode[512] = {
+    0, 67, 65, 63, 61, 59, 60, 88, 0, 68, 66, 64, 62, 15, 41, 85,
+    0, 56, 42, 0, 29, 16, 2, 89, 0, 0, 44, 31, 30, 17, 3, 90,
+    0, 46, 45, 32, 18, 5, 4, 91, 0, 57, 47, 33, 20, 19, 6, 0,
+    0, 49, 48, 35, 34, 21, 7, 0, 0, 0, 50, 36, 22, 8, 9, 0,
+    0, 51, 37, 23, 24, 11, 10, 0, 0, 52, 53, 38, 39, 25, 12, 0,
+    122, 89, 40,120, 26, 13, 0, 0, 58, 54, 28, 27, 0, 43, 0, 0,
+    85, 86, 90, 91, 92, 93, 14, 94, 95, 79, 0, 75, 71,121, 0,123,
+    82, 83, 80, 76, 77, 72, 1, 69, 87, 78, 81, 74, 55, 73, 70, 99,
+    252, 0, 0, 65, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,251, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    252,253, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,255,
+    0, 0, 92, 90, 85, 0,137, 0, 0, 0, 0, 91, 89,144,115, 0,
+    136,100,255, 0, 97,149,164, 0,156, 0, 0,140,115, 0, 0,125,
+    0,150, 0,154,152,163,151,126,112,166, 0,140, 0,147, 0,127,
+    159,167,139,160,163, 0, 0,116,158, 0,150,165, 0, 0, 0,142,
+    157, 0,114,166,168, 0, 0, 0,155, 0, 98,113, 0,148, 0,138,
+    0, 0, 0, 0, 0, 0,153,140, 0, 0, 96, 0, 0, 0,143, 0,
+    133, 0,116, 0,143, 0,174,133, 0,107, 0,105,102, 0, 0,112,
+    110,111,108,112,106,103, 0,119, 0,118,109, 0, 99,104,119
+};
+
+#undef BLOCK_SIZE
+#define BLOCK_SIZE     32
+#define BUFFER_SIZE    50
+#define CHIP_WAIT_TIME 1000000
+
+static int check_device_return(u8 *buffer)
+{
+        int ret;
+        u8 nbytes;
+
+        if ( (ret = receive_juno_response(REPORT_BLOCK, buffer, &nbytes, 0)) 
+             != 0 )
+        {
+                DBG(KERN_WARNING __FUNCTION__ " Error: Bad Juno return value: %d\n",ret);
+                return ret;
+        }
+        else
+        {
+                if ( buffer[4] != MODE_ACK )
+                {
+                        DBG(KERN_WARNING "hid device returned error: %x, %x, %x, %x, 
+                               %x, %x\n", buffer[0], buffer[1], buffer[2], 
+                               buffer[3], buffer[4], buffer[5]);   
+
+                        return -E_BAD_ACK;
+                }
+                else
+                        DBG("Device Return Successful!\n");
+        }
+
+	return 0;
+}
+
+int mode_switch_to_absolute(void)
+{
+        u8 buffer[BUFFER_SIZE];
+        u8 block[BLOCK_SIZE];
+        u8 nbytes;
+        int ret;
+        int i   = 0;
+        int err = 0;
+
+        DBG("Touchscreen: waiting for internal ps/2 chip.");
+        // Make sure the GPE register has gotten an internal ps/2 connect 
+        // (IP_CON)
+        while ( i < CHIP_WAIT_TIME ) // Give the chip time to come up
+        {
+                send_juno_command(READ_REGISTER, GPE_STATUS_0_REGISTER, 0, 0, 
+                                  0, NULL);
+  
+                if ( (ret = receive_juno_response(REPORT_REGISTER, 
+                                                  (u8 *)&buffer, &nbytes, 
+                                                  IP_CON) != 0) )
+                        i++;
+                else
+                        break;
+        }
+        DBG("\n");
+
+        if ( i >= CHIP_WAIT_TIME ) 
+        {
+                printk(KERN_DEBUG "Internal pointing device not detected\n");
+                return -1;
+        }
+        else 
+                DBG("Touchscreen: Internal PS/2 connection established\n");
+
+        // Turn on report mode
+        send_juno_command(WRITE_REGISTER, PS2_DEVICE_DIRECT_CONTROL_REGISTER, 
+                          REP_MODE, 0, 0, NULL);
+        send_juno_command(READ_REGISTER, PS2_DEVICE_DIRECT_CONTROL_REGISTER, 
+                          0, 0, 0, NULL);
+        if ( (ret = receive_juno_response(REPORT_REGISTER, (u8 *)&buffer, 
+                                          &nbytes, REP_MODE) != 0) )
+        {
+                printk(KERN_DEBUG __FUNCTION__ "Error: Bad Juno return value: %d\n", ret);
+        }
+
+        // Indicate that the Control Register (Direct Port) should be enabled 
+        // Send first "Set Sampling Rate (0xF3) via block write.
+        DBG("ENABLE PS/2\n");        
+        block[0] = PS2_DEVICE_ENABLE;
+        block[1] = SET_SAMPLING_RATE;
+        send_juno_command(WRITE_BLOCK, CONTROL_REGISTER, 0, 0, 2, 
+                          (u8 *)&block);
+        err += check_device_return(buffer);
+
+        // Write 80 Repors/Second
+        DBG("80 Repors/Second\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, REPORS_80, 
+                          0, 0, NULL);
+        err += check_device_return(buffer);
+
+        // Write Set Sampling Rate
+        DBG("Set Sampling Rate\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, 
+                          SET_SAMPLING_RATE, 0, 0, NULL);
+        err += check_device_return(buffer);
+
+        // Write 60 Repors/Second
+        DBG("60 Repors/Second\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, REPORS_60, 
+                          0, 0, NULL);
+        err += check_device_return(buffer);
+
+        // Write Set Sampling Rate
+        DBG("Set Sampling Rate\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, 
+                          SET_SAMPLING_RATE, 0, 0, NULL);
+        err += check_device_return(buffer);
+
+        // Write 100 Repors/Second
+        DBG("100 Repors/Second\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, REPORS_100, 
+                          0, 0, NULL);
+        err += check_device_return(buffer);
+
+        // Write new command block for capturing the device ID
+        // block[0] = 0x3; AAM - is it 2 or 3
+        DBG("Device ID\n");
+        block[0] = 0x3;
+        block[1] = READ_DEVICE_TYPE;
+        send_juno_command(WRITE_BLOCK, CONTROL_REGISTER, 0, 0, 2, 
+                          (u8 *)&block);
+        if ( (ret = check_device_return(buffer) != 0) )
+        {
+                printk(KERN_DEBUG "Error: Invalid device ID\n");
+                err += -E_BAD_ACK;
+        }
+        else
+        {
+                if ( buffer[5] != VALID_DEVICE_ID )
+                {
+                        printk(KERN_DEBUG "Error: device ID: %x, %x, %x, %x, %x, %x\r\n", 
+                               buffer[0], buffer[1], buffer[2], buffer[3], 
+                               buffer[4], buffer[5]);
+
+                        err += -E_BAD_DEVICE_ID;
+                }
+                else
+                {
+                        DBG("Touchscreen: Juno device ID successfully 
+                                retrieved\n");
+                }
+        }
+
+        // Set Sampling Rate 100 this time for real!  The block command also 
+        // sets the length back to 1
+        DBG("Set Sampling Rate\n");
+        block[0] = PS2_DEVICE_ENABLE;
+        block[1] = SET_SAMPLING_RATE;
+        send_juno_command(WRITE_BLOCK, CONTROL_REGISTER, 0, 0, 2, 
+                          (u8 *)&block);
+        err += check_device_return(buffer);
+  
+        // Write xmit data 
+        DBG("Set 0x64\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, 0x64, 0, 0, 
+                          NULL);
+        err += check_device_return(buffer);
+
+        // Set Stream Mode 
+        DBG("0xea\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, 0xea, 0, 0, 
+                          NULL);
+        err += check_device_return(buffer);
+  
+        // Enable Device 
+        DBG("0xf4\n");
+        send_juno_command(WRITE_REGISTER, HOST_TRANSMIT_REGISTER, 0xf4, 0, 0, 
+                          NULL);
+        err += check_device_return(buffer);
+
+         // Set Byte Length to three
+        DBG("0x3\n");
+        send_juno_command(WRITE_REGISTER, CONTROL_REGISTER, 3, 0, 0, NULL);
+        send_juno_command(READ_REGISTER, CONTROL_REGISTER, 0, 0, 0, NULL);
+        //check_device_return(buffer);
+        if ( (ret = receive_juno_response(REPORT_REGISTER, (u8 *)&buffer, 
+                                          &nbytes, 3) != 0) )
+        {
+                printk(KERN_DEBUG __FUNCTION__ " Error: Bad Juno return"
+                        " value: %d\n", ret);
+                err += -E_BAD_VALUE;
+        }
+
+        if ( err == 0 )
+                printk(KERN_DEBUG "Touchscreen: Switched to absolute mode\n");
+        else
+                printk(KERN_DEBUG "Touchscreen: Error could not switch to 
+                                   absolute mode!\n");
+        
+        send_juno_command(WRITE_REGISTER, PS2_DEVICE_DIRECT_CONTROL_REGISTER, 
+                          0, 0, 0, NULL);
+        send_juno_command(READ_REGISTER, PS2_DEVICE_DIRECT_CONTROL_REGISTER, 
+                          0, 0, 0, NULL);
+        if ( (ret = receive_juno_response(REPORT_REGISTER, (u8 *)&buffer, 
+                                          &nbytes, 0) != 0) )
+        {
+                printk(KERN_DEBUG __FUNCTION__ " Error: Bad Juno return value: %d\n", 
+                       ret);
+        }
+        return 0;
+} 
+
+struct omap1510_hid_dev 
+{
+        struct input_dev mouse;
+        struct input_dev kbd;
+        int open;
+        int abs_mode;
+};
+
+static void process_async_report(struct omap1510_hid_dev *);
+static void do_hid_tasklet(unsigned long);
+DECLARE_TASKLET(hid_tasklet,do_hid_tasklet,0);
+
+static struct omap1510_hid_dev *hid;
+
+static int omap1510_hid_interrupt(int irq, void *dev_id, 
+                                  struct pt_regs *regs) 
+{
+        hid = (struct omap1510_hid_dev *) dev_id;
+        if ( !atn_high() ) 
+        {
+                disable_irq(INT_FPGA_ATN);
+                tasklet_schedule(&hid_tasklet);
+        }
+
+        return 0;
+}
+
+static void do_hid_tasklet(unsigned long unused) 
+{
+        process_async_report(hid);
+        enable_irq(INT_FPGA_ATN);
+}
+
+static int omap1510_hid_open(struct input_dev *dev)
+{
+        extern int spi_init(void);
+        ENTRY();
+
+        if ( hid->open++ )
+                return 0;
+
+        if ( ! hid->abs_mode ) 
+        { 
+
+                if ( spi_init() < 0 ) 
+                {
+                        printk(KERN_WARNING "DSPLinux: unable to initialize 
+                                             spi\n");
+                        return -EINVAL;
+                }
+      
+                if ( mode_switch_to_absolute() < 0 )
+                        return -EINVAL;
+        }
+
+        hid->abs_mode = 1;
+
+        if ( request_irq(INT_FPGA_ATN, (void *)omap1510_hid_interrupt,
+                         SA_INTERRUPT, "hid", hid) < 0 )
+                return -EINVAL;
+
+        return 0;
+} 
+
+static void omap1510_hid_close(struct input_dev *dev) 
+{
+        if ( hid->open-- ) 
+                return;
+
+        if ( hid == NULL )
+                return;
+
+        kfree(hid);
+}
+
+static int  __init omap1510_ps2_init(void) 
+{
+        int i;
+
+        ENTRY();
+        printk(KERN_INFO "DSPLinux HID Driver (c) 2001 RidgeRun, Inc.\n");
+
+#if CONFIG_DSPLINUX_OMAP1510_TOUCHSCREEN
+        ts = 1;
+#endif
+#if CONFIG_DSPLINUX_OMAP1510_MOUSE
+        mouse = 1;
+#endif
+#if CONFIG_DSPLINUX_OMAP1510_KEYBOARD
+        kbd = 1;
+#endif
+        DBG("HID: ts %d mouse %d kbd %d\n",ts,mouse,kbd);
+
+        if ( mouse && ts ) 
+        {
+                printk(KERN_WARNING "concurrent mouse and touchscreen not supported\n");
+                return -EINVAL;
+        }
+
+        hid = kmalloc(sizeof(*hid),GFP_KERNEL);
+
+        if ( hid == NULL ) 
+        {
+                printk(KERN_WARNING "unable to allocate space for HID device\n");
+                return -ENOMEM;
+        }
+
+        memset(hid,0,sizeof(*hid));
+        hid->open = 0;
+        hid->abs_mode = 0;
+
+        // setup the pen and mouse
+        if ( ts ) 
+        {
+                hid->mouse.evbit[0] = BIT(EV_KEY) | BIT(EV_ABS);
+                hid->mouse.keybit[LONG(BTN_MOUSE)] = BIT(BTN_LEFT) | 
+                        BIT(BTN_RIGHT) | BIT(BTN_MIDDLE) | BIT(BTN_TOUCH);
+                hid->mouse.absbit[0] = BIT(ABS_X) | BIT(ABS_Y);
+                hid->mouse.absmax[ABS_X] = 1000;
+                hid->mouse.absmin[ABS_X] = 1;
+                hid->mouse.absmax[ABS_Y] = 1000;
+                hid->mouse.absmin[ABS_Y] = 1;
+                hid->mouse.absflat[0] = 1;
+                hid->mouse.absfuzz[0] = 4;
+        } 
+        else if ( mouse ) 
+        {
+
+                hid->mouse.evbit[0] = BIT(EV_KEY) | BIT(EV_REL);
+                hid->mouse.keybit[LONG(BTN_MOUSE)] = BIT(BTN_LEFT) | 
+                        BIT(BTN_RIGHT) | BIT(BTN_MIDDLE) | BIT(BTN_TOUCH);
+                hid->mouse.relbit[0] = BIT(REL_X) | BIT(REL_Y);
+        }
+
+        hid->mouse.private = hid;
+        hid->mouse.open = omap1510_hid_open;
+        hid->mouse.close = omap1510_hid_close;
+        hid->mouse.name = "omap1510_mouse";
+        hid->mouse.idbus = 0;
+        hid->mouse.idvendor = 0;
+        hid->mouse.idproduct = 0;
+        hid->mouse.idversion = 0;
+
+        input_register_device(&hid->mouse);
+        
+        if ( kbd ) 
+        {
+                // setup the keyboard
+                hid->kbd.evbit[0] = BIT(EV_KEY);
+                for (i = 0; i < 511; i++)
+                        set_bit(ps2_kbd_keycode[i], hid->kbd.keybit);
+                clear_bit(0, hid->kbd.keybit);
+                hid->kbd.private = hid;
+                hid->kbd.open = omap1510_hid_open;
+                hid->kbd.close = omap1510_hid_close;
+                hid->kbd.name = "omap1510_kbd";
+                hid->kbd.idbus = 0;
+                hid->kbd.idvendor = 0;
+                hid->kbd.idproduct = 0;
+                hid->kbd.idversion = 0;
+       
+                input_register_device(&hid->kbd);
+        }
+        omap1510_hid_open(&hid->mouse);
+
+        return 0;
+}
+
+static void __exit omap1510_ps2_exit(void) 
+{
+        ENTRY();
+
+        free_irq(INT_FPGA_ATN, hid);
+
+        if ( hid != NULL )
+                kfree(hid);
+
+        return;
+}
+
+#define FUNCTION_BIT_0 (1<<0)
+#define FUNCTION_BIT_1 (1<<1)
+#define FUNCTION_BIT_2 (1<<2)
+#define FUNCTION_MASK  (FUNCTION_BIT_0 | FUNCTION_BIT_1 | FUNCTION_BIT_2)
+#define X_MSB_SHIFT    (8-4)
+#define X_MSB_MASK     (3<<4)
+#define Y_MSB_SHIFT    (8-6)
+#define Y_MSB_MASK     (3<<6)
+
+static void process_pointing_report(struct omap1510_hid_dev *hid, 
+                                    u8 *buffer)
+{
+        int x;
+        int y;
+        int btn;
+        int prev_x;
+        int prev_y;
+        int prev_btn;
+        int functions;
+
+        functions = buffer[1] & FUNCTION_MASK;
+
+        if ( buffer[1] & (1<<3) )
+        { // relative device
+                if ( ts )
+                {
+                        DBG(KERN_WARNING "HID: relative packet, configured for" 
+                               " absolute\n");
+                        return;
+                }
+
+                x = buffer[2];
+                y = buffer[3];
+
+                // check the sign and convert from 2's complement if negative
+                if ( buffer[1] & 0x10 )
+                        x = ~(-x) - 255;
+              
+                // input driver wants -y
+                if ( buffer[1] & 0x20 )
+                        y = -(~(-y) - 255);
+                else
+                        y = -y;
+
+                input_report_key(&hid->mouse, BTN_LEFT, 
+                                 buffer[1] & FUNCTION_BIT_0);
+                input_report_rel(&hid->mouse, REL_X, x);
+                input_report_rel(&hid->mouse, REL_Y, y);
+        }
+        else
+        { // absolute device
+                if ( mouse )
+					 {
+                        DBG(KERN_WARNING "HID: absolute packet, configured for" 
+                               " relative\n");
+								return;
+					 }
+
+                x   = buffer[2] + ((buffer[1] & X_MSB_MASK) << X_MSB_SHIFT);
+                y   = buffer[3] + ((buffer[1] & Y_MSB_MASK) << Y_MSB_SHIFT);
+                btn = buffer[1] & FUNCTION_BIT_0;
+ 
+                if ( (prev_x == x) && (prev_y == y) && (prev_btn == btn) )
+                        return;
+ 
+                input_report_key(&hid->mouse, BTN_LEFT, btn);
+                input_report_abs(&hid->mouse, ABS_X, x);
+                input_report_abs(&hid->mouse, ABS_Y, y);
+
+                prev_x   = x; 
+                prev_y   = y;
+                prev_btn = btn;
+        }
+
+        DBG("HID X: %d Y: %d Functions: %x\n", x, y, functions);
+}
+
+/* NOTE: this function is taken verbatim from the standard kernel file:
+ * drivers/char/pc_keyb.c.
+ */
+
+/*
+ * Translation of escaped scancodes to keycodes.
+ * This is now user-settable.
+ * The keycodes 1-88,96-111,119 are fairly standard, and
+ * should probably not be changed - changing might confuse X.
+ * X also interprets scancode 0x5d (KEY_Begin).
+ *
+ * For 1-88 keycode equals scancode.
+ */
+
+#define E0_KPENTER 96
+#define E0_RCTRL   97
+#define E0_KPSLASH 98
+#define E0_PRSCR   99
+#define E0_RALT    100
+#define E0_BREAK   101  /* (control-pause) */
+#define E0_HOME    102
+#define E0_UP      103
+#define E0_PGUP    104
+#define E0_LEFT    105
+#define E0_RIGHT   106
+#define E0_END     107
+#define E0_DOWN    108
+#define E0_PGDN    109
+#define E0_INS     110
+#define E0_DEL     111
+
+#define E1_PAUSE   119
+
+/*
+ * The keycodes below are randomly located in 89-95,112-118,120-127.
+ * They could be thrown away (and all occurrences below replaced by 0),
+ * but that would force many users to use the `setkeycodes' utility, where
+ * they needed not before. It does not matter that there are duplicates, as
+ * long as no duplication occurs for any single keyboard.
+ */
+#define SC_LIM 89
+
+#define FOCUS_PF1 85           /* actual code! */
+#define FOCUS_PF2 89
+#define FOCUS_PF3 90
+#define FOCUS_PF4 91
+#define FOCUS_PF5 92
+#define FOCUS_PF6 93
+#define FOCUS_PF7 94
+#define FOCUS_PF8 95
+#define FOCUS_PF9 120
+#define FOCUS_PF10 121
+#define FOCUS_PF11 122
+#define FOCUS_PF12 123
+
+#define JAP_86     124
+/* tfj@olivia.ping.dk:
+ * The four keys are located over the numeric keypad, and are
+ * labelled A1-A4. It's an rc930 keyboard, from
+ * Regnecentralen/RC International, Now ICL.
+ * Scancodes: 59, 5a, 5b, 5c.
+ */
+#define RGN1 124
+#define RGN2 125
+#define RGN3 126
+#define RGN4 127
+
+static unsigned char high_keys[128 - SC_LIM] = {
+  RGN1, RGN2, RGN3, RGN4, 0, 0, 0,                   /* 0x59-0x5f */
+  0, 0, 0, 0, 0, 0, 0, 0,                            /* 0x60-0x67 */
+  0, 0, 0, 0, 0, FOCUS_PF11, 0, FOCUS_PF12,          /* 0x68-0x6f */
+  0, 0, 0, FOCUS_PF2, FOCUS_PF9, 0, 0, FOCUS_PF3,    /* 0x70-0x77 */
+  FOCUS_PF4, FOCUS_PF5, FOCUS_PF6, FOCUS_PF7,        /* 0x78-0x7b */
+  FOCUS_PF8, JAP_86, FOCUS_PF10, 0                   /* 0x7c-0x7f */
+};
+
+/* BTC */
+#define E0_MACRO   112
+/* LK450 */
+#define E0_F13     113
+#define E0_F14     114
+#define E0_HELP    115
+#define E0_DO      116
+#define E0_F17     117
+#define E0_KPMINPLUS 118
+/*
+ * My OmniKey generates e0 4c for  the "OMNI" key and the
+ * right alt key does nada. [kkoller@nyx10.cs.du.edu]
+ */
+#define E0_OK  124
+/*
+ * New microsoft keyboard is rumoured to have
+ * e0 5b (left window button), e0 5c (right window button),
+ * e0 5d (menu button). [or: LBANNER, RBANNER, RMENU]
+ * [or: Windows_L, Windows_R, TaskMan]
+ */
+#define E0_MSLW   125
+#define E0_MSRW   126
+#define E0_MSTM   127
+
+static unsigned char e0_keys[128] = {
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x00-0x07 */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x08-0x0f */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x10-0x17 */
+  0, 0, 0, 0, E0_KPENTER, E0_RCTRL, 0, 0,	      /* 0x18-0x1f */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x20-0x27 */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x28-0x2f */
+  0, 0, 0, 0, 0, E0_KPSLASH, 0, E0_PRSCR,	      /* 0x30-0x37 */
+  E0_RALT, 0, 0, 0, 0, E0_F13, E0_F14, E0_HELP,	      /* 0x38-0x3f */
+  E0_DO, E0_F17, 0, 0, 0, 0, E0_BREAK, E0_HOME,	      /* 0x40-0x47 */
+  E0_UP, E0_PGUP, 0, E0_LEFT, E0_OK, E0_RIGHT, E0_KPMINPLUS, E0_END,/* 0x48-0x4f */
+  E0_DOWN, E0_PGDN, E0_INS, E0_DEL, 0, 0, 0, 0,	      /* 0x50-0x57 */
+  0, 0, 0, E0_MSLW, E0_MSRW, E0_MSTM, 0, 0,	      /* 0x58-0x5f */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x60-0x67 */
+  0, 0, 0, 0, 0, 0, 0, E0_MACRO,		      /* 0x68-0x6f */
+  0, 0, 0, 0, 0, 0, 0, 0,			      /* 0x70-0x77 */
+  0, 0, 0, 0, 0, 0, 0, 0			      /* 0x78-0x7f */
+};
+
+static int pckbd_translate(unsigned char scancode, unsigned char *keycode,
+		    char raw_mode)
+{
+	static int prev_scancode;
+
+	/* special prefix scancodes.. */
+	if (scancode == 0xe0 || scancode == 0xe1) {
+		prev_scancode = scancode;
+		return 0;
+	}
+
+	/* 0xFF is sent by a few keyboards, ignore it. 0x00 is error */
+	if (scancode == 0x00 || scancode == 0xff) {
+		prev_scancode = 0;
+		return 0;
+	}
+
+	scancode &= 0x7f;
+
+	if (prev_scancode) {
+	  /*
+	   * usually it will be 0xe0, but a Pause key generates
+	   * e1 1d 45 e1 9d c5 when pressed, and nothing when released
+	   */
+	  if (prev_scancode != 0xe0) {
+	      if (prev_scancode == 0xe1 && scancode == 0x1d) {
+		  prev_scancode = 0x100;
+		  return 0;
+	      } else if (prev_scancode == 0x100 && scancode == 0x45) {
+		  *keycode = E1_PAUSE;
+		  prev_scancode = 0;
+	      } else {
+#ifdef KBD_REPORT_UNKN
+		  if (!raw_mode)
+		    printk(KERN_INFO "keyboard: unknown e1 escape sequence\n");
+#endif
+		  prev_scancode = 0;
+		  return 0;
+	      }
+	  } else {
+	      prev_scancode = 0;
+	      /*
+	       *  The keyboard maintains its own internal caps lock and
+	       *  num lock statuses. In caps lock mode E0 AA precedes make
+	       *  code and E0 2A follows break code. In num lock mode,
+	       *  E0 2A precedes make code and E0 AA follows break code.
+	       *  We do our own book-keeping, so we will just ignore these.
+	       */
+	      /*
+	       *  For my keyboard there is no caps lock mode, but there are
+	       *  both Shift-L and Shift-R modes. The former mode generates
+	       *  E0 2A / E0 AA pairs, the latter E0 B6 / E0 36 pairs.
+	       *  So, we should also ignore the latter. - aeb@cwi.nl
+	       */
+	      if (scancode == 0x2a || scancode == 0x36)
+		return 0;
+
+	      if (e0_keys[scancode])
+		*keycode = e0_keys[scancode];
+	      else {
+#ifdef KBD_REPORT_UNKN
+		  if (!raw_mode)
+		    printk(KERN_INFO "keyboard: unknown scancode e0 %02x\n",
+			   scancode);
+#endif
+		  return 0;
+	      }
+	  }
+	} else if (scancode >= SC_LIM) {
+	    /* This happens with the FOCUS 9000 keyboard
+	       Its keys PF1..PF12 are reported to generate
+	       55 73 77 78 79 7a 7b 7c 74 7e 6d 6f
+	       Moreover, unless repeated, they do not generate
+	       key-down events, so we have to zero up_flag below */
+	    /* Also, Japanese 86/106 keyboards are reported to
+	       generate 0x73 and 0x7d for \ - and \ | respectively. */
+	    /* Also, some Brazilian keyboard is reported to produce
+	       0x73 and 0x7e for \ ? and KP-dot, respectively. */
+
+	  *keycode = high_keys[scancode - SC_LIM];
+
+	  if (!*keycode) {
+	      if (!raw_mode) {
+#ifdef KBD_REPORT_UNKN
+		  printk(KERN_INFO "keyboard: unrecognized scancode (%02x)"
+			 " - ignored\n", scancode);
+#endif
+	      }
+	      return 0;
+	  }
+ 	} else
+	  *keycode = scancode;
+ 	return 1;
+}
+
+static unsigned char handle_print_scr(struct omap1510_hid_dev *hid, 
+                                      u8 *buffer,int up)
+{
+        unsigned char keycode; 
+
+        if ( up )
+        {
+                pckbd_translate(0xe0, &keycode, 0);
+                pckbd_translate(0xb7, &keycode, 0);  
+                pckbd_translate(0xe0, &keycode, 0);
+                pckbd_translate(0xaa, &keycode, 0);  
+        }
+        else
+        {
+                pckbd_translate(0xe0, &keycode, 0);
+                pckbd_translate(0x2a, &keycode, 0);
+                pckbd_translate(0xe0, &keycode, 0);
+                pckbd_translate(0x37, &keycode, 0);
+        }                
+
+        return keycode;
+}
+ 
+static unsigned char handle_pause(struct omap1510_hid_dev *hid, u8 *buffer)
+{
+        unsigned char keycode;
+
+        pckbd_translate(0xe1, &keycode, 0);
+        pckbd_translate(0x1d, &keycode, 0);
+        pckbd_translate(0x45, &keycode, 0);
+        pckbd_translate(0xe1, &keycode, 0);
+        pckbd_translate(0x9d, &keycode, 0);
+        pckbd_translate(0xc5, &keycode, 0);
+
+        return keycode;
+}
+
+static void process_keyboard_report(struct omap1510_hid_dev *hid, 
+                                    u8 *buffer)
+{
+        unsigned char ch      = buffer[1] & 0x7f;
+        int is_e0             = 0;
+        unsigned char keycode = 0;
+
+        if ( (ch == 106) || (ch == 107) )
+                return; // no code
+
+        if ( ch == 100 )
+                keycode = handle_print_scr(hid, buffer,  buffer[1] & 0x80);
+        
+        if ( ch == 101 )
+                keycode = handle_pause(hid, buffer);
+
+        // first block of e0 codes
+        if ( (ch >= 53) && (ch <= 84) )
+                is_e0 = e0_codes1 & (1 << (ch - 53));
+
+        // second block of e0 codes
+        if ( (ch >= 85) && (ch <= 116) )
+                is_e0 = e0_codes2 & (1 << (ch - 85));
+
+        if ( is_e0 )
+                pckbd_translate(0xe0, &keycode, 0);
+
+        if ( !keycode )
+                pckbd_translate(usar2scancode[ch], &keycode, 0);
+
+        input_report_key(&hid->kbd, keycode, 
+                         buffer[1] & 0x80 ? 0 : 1);
+
+        DBG("HID: key: %d, state: %s\n", buffer[1] & 0x7f, 
+            buffer[1] & 0x80 ? "up" : "down"); 
+}
+
+static void process_async_report(struct omap1510_hid_dev *hid)
+{
+        u8 buffer[BUFFER_SIZE];
+        u8 nbytes;
+        int ret;
+        
+        if ( (ret = receive_juno_response(ASYNC_REPORT, (u8 *)&buffer, 
+                                          &nbytes, REP_MODE)) == -1 )
+        {
+                DBG(__FUNCTION__ " Error: Bad Juno return value: %d\n", 
+                       ret);
+        }
+
+        if ( ret == KEYBOARD_REPORT )
+                process_keyboard_report(hid, buffer);
+        else if ( ret == POINTING_REPORT )
+                process_pointing_report(hid, buffer);
+        else
+                DBG(KERN_INFO "ERROR: bad report\n");
+}
+
+module_init(omap1510_ps2_init);
+module_exit(omap1510_ps2_exit);
+
+MODULE_PARM(mouse,"i");
+MODULE_PARM_DESC(mouse,"mouse support for DSPLinux HID controller");
+MODULE_PARM(ts,"i");
+MODULE_PARM_DESC(ts,"touchscreen support for DSPLinux HID controller");
+MODULE_PARM(kbd,"i");
+MODULE_PARM_DESC(kbd,"keyboard support for DSPLinux HID controller");
+
+MODULE_AUTHOR("Alex McMains <aam@rigderun.com>");
+MODULE_DESCRIPTION("DSPLinux HID Driver");
+
+/*
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_spi.c linux-2.4.19/drivers/char/omap1510_spi.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_spi.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_spi.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,409 @@
+/*
+ * File: omap1510_spi.c  
+ *
+ * OMAP1510 SPI interface for the HID controller
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Alex McMains <aam@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include "omap1510_hid.h"
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...) ;
+#  define ENTRY() ;
+#endif
+#if defined(CONFIG_ARCH_TI925)
+#define OMAP_FPGA_BASE IO_ADDRESS(0x11000000)
+#define OMAP_FPGA_HID_SPI 0x08
+#elif defined(CONFIG_OMAP_1510P1) || defined(CONFIG_OMAP_INNOVATOR)
+#define OMAP_FPGA_BASE 0xE8000000
+#define OMAP_FPGA_HID_SPI 0x4
+#else
+#error "not supported Architecture"
+#endif
+
+extern void send_juno_command(u8 type, u8 reg_offset, u8 data1, u8 data2, 
+                              int length, u8 *block);
+extern int receive_juno_response(u8 type, u8 *buffer, u8 *nbytes, u8 data);
+
+#define SPI_WRITE_REG (OMAP_FPGA_BASE + OMAP_FPGA_HID_SPI)
+#define SPI_READ_REG  SPI_WRITE_REG
+
+// FPGA HID Register Bit Patterns
+#define MOSI_CLK_HI      0x03
+#define HID_HOST_ACTIVE  0x80
+#define _SS_LOW          0x04
+#define _SS_HIGH         0xfb
+#define CLK_LOW          0xfe
+#define CLK_HIGH         0x01
+#define MOSI_LOW         0xfd
+#define MOSI_HI          0x02
+#define MISO_BIT         0x10
+#define ATN              0x20
+
+static inline void spi_write(unsigned long val) 
+{
+        outb(val,SPI_WRITE_REG);
+}
+
+static inline unsigned long spi_read(void) 
+{
+        return inb(SPI_READ_REG);
+}
+
+static inline void spi_reset(void) 
+{
+        spi_read();
+        spi_write(MOSI_CLK_HI);
+        spi_write(HID_HOST_ACTIVE | MOSI_CLK_HI);
+}
+
+unsigned long atn_high(void) 
+{
+        return !(spi_read() & ATN);
+}
+
+// timings
+#define TMAC 100    
+#define TSLOW 2    
+#define TMIB 150  
+#define TSNEXT 120
+#define TSSC 100
+#define TSNA 100
+
+void spi_snd_packet(u8 *databyte, u8 num_bytes);
+void spi_rcv_packet(u8 *buffer, u8 *num_bytes);
+int spi_init(void);
+unsigned long atn_high(void);
+
+extern unsigned long jiffies;
+
+/*****************************************************************************
+ USAR doc8-007-001-tr-0721.pdf
+
+ (1) The Host asserts _SS to wake up the slave (USAR UR8HC007) device and 
+     prepare it for a data transfer 
+ (2) The slave asserts _ATN to indicate that it is ready to receive data and 
+     prepares the output register (MISO line) to output FFh whenever clocks 
+     are provided by the host. 
+ (3) The host starts placing the clock signals and data on the SCLK and the 
+     MOSI lines respectively (8 pulses for 8 data bits).
+ (4) After the completion of one byte transfer the host continues with the 
+     remaining bytes of the packet until the packet transfer is complete. 
+     The _SS line is kept low to indicate to the slave that more bytes are 
+     following. At least 150ms must elapse between the beginning of one byte 
+     transfer and the beginning of the next byte transfer so the slave has 
+     time to process each byte. 
+ (5) The whole packet is transmitted. 
+ (6) After the last byte of the packet is transferred the host de-asserts the 
+     _SS line to indicate that the transfer has been completed. 
+ (7) The slave releases the _ATN line indicating it is busy. 
+ (8) If the host has another packet to send it can only assert _SS after _ATN 
+     has been de-asserted for at least 120ms. This is necessary in order to 
+     provide the USAR Juno TM with sufficient time to process the received 
+     packet and assert _ATN associated with a Resend request if the packet was
+     received in error
+ *****************************************************************************/
+
+void spi_snd_packet(u8 *databyte, u8 num_bytes)
+{
+        u8 *next_byte;
+        u8 reg_val;
+        u8 bit_val;
+        u8 nbytes;
+        u8 next_bit;
+        static unsigned long timeout;
+
+        next_byte = databyte;
+        nbytes    = num_bytes;
+                
+        // (1) The Host asserts _SS to wake up the slave (USAR UR8HC007) 
+        //     device and prepare it for a data transfer
+        reg_val = spi_read();
+        spi_write(reg_val | _SS_LOW);
+
+        // (2) The slave asserts _ATN to indicate that it is ready to receive 
+        //     data and prepares the output register (MISO line) to output 
+        //     FFh whenever clocks are provided by the host. 
+
+        // wait for ATN to be ASSERTED (i.e. LOW - bit 5 == 1)
+        timeout = jiffies + 10;
+        while ( atn_high() )
+        {
+                if ( jiffies > timeout )
+                        panic("DSPLinux: Hid SPI send timeout (1)");
+        }
+                
+        udelay(TMAC);
+
+
+        // (3) The host starts placing the clock signals and data on the SCLK 
+        //     and the MOSI lines respectively (8 pulses for 8 data bits).
+        // (4) After the completion of one byte transfer the host continues 
+        //     with the remaining bytes of the packet until the packet 
+        //     transfer is complete. The _SS line is kept low to indicate to 
+        //     the slave that more bytes are following. At least 150ms must 
+        //     elapse between the beginning of one byte transfer and the 
+        //     beginning of the next byte transfer so the slave has time to 
+        //     process each byte. 
+        // (5) The whole packet is transmitted. 
+        while ( nbytes > 0 )
+        {
+                DBG("byte: 0x%x\n", *next_byte);
+
+                next_bit = 8;
+                
+                while ( next_bit > 0 )
+                {
+                     bit_val = (*next_byte >> (next_bit - 1)) & 1;
+
+                     reg_val = spi_read();
+
+                     if ( bit_val )
+                             reg_val |= MOSI_HI;
+                     else
+                             reg_val &= MOSI_LOW;
+
+                     // clock low
+                     spi_write(reg_val & CLK_LOW);
+                     udelay(TSLOW);
+
+                     // clock high
+                     spi_write(reg_val | CLK_HIGH);
+                     udelay(TSLOW);
+                     
+                     next_bit--;
+                }  
+       
+                next_byte++;
+                nbytes--;
+
+                // wait TMIB between bytes
+                udelay(TMIB);
+        }
+
+        // (6) After the last byte of the packet is transferred the host 
+        //     de-asserts the _SS line to indicate that the transfer has been 
+        //     completed. 
+ 
+        spi_write(reg_val & _SS_HIGH);
+
+        // (7) The slave releases the _ATN line indicating it is busy. 
+
+        // wait for ATN to be DE-ASSERTED (i.e. HIGH - bit 5 == 0)
+        timeout = jiffies + 10;
+        while ( !atn_high() )
+        {
+                if ( jiffies > timeout )
+                        panic("DSPLinux: Hid SPI send timeout (2)");
+        }
+
+        // (8) If the host has another packet to send it can only assert _SS 
+        //     after _ATN has been de-asserted for at least 120ms. This is 
+        //     necessary in order to provide the USAR Juno TM with sufficient 
+        //     time to process the received packet and assert _ATN associated 
+        //     with a Resend request if the packet was received in error
+        
+        udelay(TSNEXT);
+}
+
+/*****************************************************************************
+ USAR doc8-007-001-tr-0721.pdf
+
+ (1) The slave asserts the _ATN signal to alert the host that data are ready 
+     for transfer and waits for a _SS signal for a maximum of 5 ms
+ (2) Host asserts _SS to select the slave and indicate that clock pulses will 
+     be issued. The slave prepares the output register (MISO) with the first 
+     byte to be transferred.
+ (3) The host starts producing clock pulses. The slave s outputs each bit at 
+     the falling edge of each clock pulse.
+ (4) The host receives one byte. If the _ATN signal is still low the host 
+     starts providing clocks in order to read subsequent bytes. At least 150ms
+     must elapse between the beginning of one byte transfer and the beginning 
+     of the next byte transfer. 
+ (5) (6) When all the packet data have been transferred the slave de-asserts 
+     the _ATN signal to indicate that no more data are available. 
+ (7) The host de-asserts the _SS line to release the bus. 
+ (8) The slave may start a new transfer after the _SS has been de-asserted for
+     at least 120ms.
+ *****************************************************************************/
+
+void spi_rcv_packet(u8 *buffer, u8 *num_bytes)
+{
+        u8 reg_val;
+        u8 *next_byte;
+        u8 next_bit;
+        u8 reg_out;
+        static unsigned long timeout;
+
+        next_byte = buffer;
+
+        // (1) The slave asserts the _ATN signal to alert the host that data 
+        //     are ready for transfer and waits fora _SS signal for a maximum 
+        //     of 5 ms
+
+        // wait for ATN to be ASSERTED (i.e. LOW - bit 5 == 1)
+        timeout = jiffies + 10;
+        while ( atn_high() )
+        {
+                if ( jiffies > timeout )
+                        panic("DSPLinux: Hid SPI receive timeout");
+        }
+        
+        // (2) Host asserts _SS to select the slave and indicate that clock 
+        //     pulses will be issued. The slave prepares the output register 
+        //     (MISO) with the first byte to be transferred.
+
+        reg_val = spi_read();
+        spi_write(reg_val | _SS_LOW);
+
+        // wait TMAC before reading first byte
+        udelay(TMAC);
+
+        // (3) The host starts producing clock pulses. The slave s outputs 
+        //     each bit at the falling edge of each clock pulse.
+        // (4) The host receives one byte. If the _ATN signal is still low the
+        //     host starts providing clocks in order to read subsequent bytes.
+        //     At least 150ms must elapse between the beginning of one byte 
+        //     transfer and the beginning of the next byte transfer. 
+        // (5) (6) When all the packet data have been transferred the slave 
+        //     de-asserts the _ATN signal to indicate that no more data are 
+        //     available. 
+
+        reg_val = spi_read();
+
+        while ( !atn_high() )
+        {
+                next_bit = 8;
+                reg_out  = 0;
+
+                while ( next_bit > 0 )
+                {
+                        spi_write(reg_val & CLK_LOW);
+                        udelay(TSLOW);
+
+                        spi_write(reg_val | CLK_HIGH);
+                        udelay(TSLOW);
+
+                        // receive bit
+                        reg_val = spi_read();
+                        udelay(TSLOW);
+        
+                        reg_out <<= 1;
+
+                        if ( reg_val & MISO_BIT )                
+                                reg_out |= 1;
+ 
+                        next_bit--;
+                        udelay(TSNA);
+                }
+                udelay(TMIB);
+
+                DBG("reg_out: 0x%x\n", reg_out);
+
+                *next_byte++  = reg_out;
+                (*num_bytes)++;
+        }
+
+        // (7) The host de-asserts the _SS line to release the bus. 
+        spi_write(reg_val & _SS_HIGH);
+
+        // (8) The slave may start a new transfer after the _SS has been 
+        //     de-asserted for at least 120ms. 
+        udelay(TSNEXT);
+}
+
+static int verify_init(u8 *buffer)
+{
+        st_simple *simple = (st_simple *) buffer;
+
+        if ( simple->cmd_code != 0x01 )
+                return -1;
+
+        return 0;
+}
+        
+int spi_init(void)
+{
+        u8 buffer[50];
+        int nbytes;
+        int ret;
+        static unsigned long timeout;
+
+        spi_reset();
+        
+        // wait for ATN to be DE-ASSERTED coming out of reset
+        timeout = jiffies + 10;
+        while ( !atn_high() )
+        {
+                if ( jiffies > timeout )
+                {
+                        printk("DSPLinux: spi timeout\n");
+                        return -1;        
+                }
+        }
+
+        // wait for ATN release to SS re-assertion = 120 microseconds
+        udelay(150);
+
+        send_juno_command(SIMPLE, 0, 0, 0, 0, NULL);
+
+        if ( (ret = receive_juno_response(SIMPLE, (u8 *)&buffer, 
+                                          (u8 *)&nbytes, 0) != 0) )
+        {
+                DBG(__FUNCTION__ " Error: Bad Juno return value: %d\n", 
+                       ret);
+                printk("DSPLinux: spi init failed\n");
+                return -1;
+        }
+       
+        if ( (ret = verify_init((u8 *)&buffer) != 0) )
+        {
+                printk("DSPLinux: spi init verify failed\n");
+                printk("DSPLinux: spi init failed\n");
+                return -1;
+        }
+        return 0;
+}
+
+/*---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_tsdev.c linux-2.4.19/drivers/char/omap1510_tsdev.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_tsdev.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_tsdev.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,335 @@
+/*
+ * File: tsdev.c
+ *
+ * touchscreen input driver
+ *
+ * Created 2001, Copyright (C) 2001 RidgeRun, Inc.  All rights reserved.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#define MOUSEDEV_MINOR_BASE 	32
+#define MOUSEDEV_MINORS		32
+#define MOUSEDEV_MIX		31
+
+#include <linux/poll.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/config.h>
+#include <linux/smp_lock.h>
+#include <linux/random.h>
+#include <linux/slab.h>
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...)
+#define ENTRY()
+#endif
+
+#define RR_BUT_LEFT      (1<<0)
+
+struct mouse_packet {
+	int x;
+	int y;
+	int buttons;
+};
+
+struct mousedev {
+	int exist;
+	int open;
+	int ready;
+	wait_queue_head_t wait;
+	struct input_handle handle;
+	struct fasync_struct *fasync;
+	struct mouse_packet packet;
+	devfs_handle_t devfs;
+	int bufsize;
+	int x;
+	int y;
+	int but_left;
+        int ts_x;
+        int ts_y;
+        int fb_x;
+        int fb_y;
+};
+
+static void mousedev_packet(void);
+
+static struct mousedev mouse;
+
+static void mousedev_event(struct input_handle *handle, unsigned int type, 
+                           unsigned int code, int value)
+{
+	struct mousedev *mouse =  handle->private;
+
+	ENTRY();
+	add_mouse_randomness((type << 4) ^ code ^ (code >> 4) ^ value);
+
+	switch(type) {
+	case EV_ABS:
+		switch(code) {
+		case ABS_X:
+			mouse->x = value * mouse->fb_x/ mouse->ts_x;
+			break;
+		case ABS_Y:
+			mouse->y = value * mouse->fb_y/mouse->ts_y;
+			break;
+			
+		default:
+			printk(__FUNCTION__ " wrong code for EV_ABS\n");
+			break;
+		}
+		break;
+	case EV_KEY:
+		switch(code) {
+		case BTN_LEFT:   mouse->but_left = value; break;
+		default: printk(__FUNCTION__ " wrong code for EV_KEY\n");
+		}
+		break;
+
+	default:
+		printk(__FUNCTION__ " wrong type for mousedev %d\n",code);
+	}
+	mouse->ready = 1;
+	kill_fasync(&mouse->fasync, SIGIO, POLL_IN);
+	wake_up_interruptible(&(mouse->wait));
+}
+
+static int mousedev_fasync(int fd, struct file *file, int on)
+{
+	int retval;
+	struct mousedev *mouse = file->private_data;
+
+	ENTRY();
+	retval = fasync_helper(fd, file, on, &mouse->fasync);
+	return retval < 0 ? retval : 0;
+}
+
+static int mousedev_release(struct inode * inode, struct file * file)
+{
+	struct mousedev *mouse = file->private_data;
+	ENTRY();
+	lock_kernel();
+
+	mousedev_fasync(-1, file, 0);
+
+	if (!--mouse->open) {
+		input_close_device(&mouse->handle);
+	}
+	unlock_kernel();
+
+	return 0;
+}
+
+static int mousedev_open(struct inode * inode, struct file * file)
+{
+	file->private_data = &mouse;
+	ENTRY();
+	if (!mouse.open++) {
+		struct input_handle *handle = &mouse.handle;
+		input_open_device(handle);
+	}
+	return 0;
+}
+
+static void mousedev_packet(void)
+{
+	int old_buttons;
+
+	ENTRY();
+	old_buttons = mouse.packet.buttons;
+
+        mouse.packet.buttons = 
+		(mouse.but_left ? RR_BUT_LEFT : 0);
+
+	if((mouse.x == mouse.packet.x) && (mouse.y == mouse.packet.y) && 
+	   (old_buttons == mouse.packet.buttons))
+		mouse.ready = 0;
+	mouse.packet.x = mouse.x;
+	mouse.packet.y = mouse.y;
+        DBG("x %d y %d buttons %x\n",mouse.x,mouse.y,mouse.packet.buttons);
+	mouse.bufsize = sizeof(mouse.packet);
+}
+
+static ssize_t mousedev_write(struct file * file, const char * buffer, 
+                              size_t count, loff_t *ppos)
+{
+	ENTRY();
+	printk(__FUNCTION__ "write not supported\n");
+	return 0;
+}
+
+static ssize_t mousedev_read(struct file *file, char * buffer, size_t count, 
+                             loff_t *ppos)
+{
+	DECLARE_WAITQUEUE(wait, current);
+	struct mousedev *mouse = file->private_data;
+	int retval = 0;
+
+	ENTRY();
+	if (!mouse->ready && !mouse->bufsize) {
+
+		add_wait_queue(&mouse->wait, &wait);
+		current->state = TASK_INTERRUPTIBLE;
+
+		while (!mouse->ready) {
+
+			if (file->f_flags & O_NONBLOCK) {
+				retval = -EAGAIN;
+				break;
+			}
+			if (signal_pending(current)) {
+				retval = -ERESTARTSYS;
+				break;
+			}
+
+			schedule();
+		}
+
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&mouse->wait, &wait);
+	}
+
+	if (retval)
+		return retval;
+
+	mousedev_packet();
+	if(count > mouse->bufsize)
+		count = mouse->bufsize;
+
+	if (copy_to_user(buffer, &mouse->packet, count))
+		return -EFAULT;
+	mouse->bufsize -= count;
+	return count;	
+}
+
+/* No kernel lock - fine */
+static unsigned int mousedev_poll(struct file *file, poll_table *wait)
+{
+	struct mousedev *mouse = file->private_data;
+
+	poll_wait(file, &mouse->wait, wait);
+	if (mouse->ready || mouse->bufsize)
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+static struct file_operations mousedev_fops = {
+	owner:		THIS_MODULE,
+	read:		mousedev_read,
+	write:		mousedev_write,
+	poll:		mousedev_poll,
+	open:		mousedev_open,
+	release:	mousedev_release,
+	fasync:		mousedev_fasync,
+};
+
+static struct input_handle *mousedev_connect(struct input_handler *handler, 
+                                             struct input_dev *dev)
+{
+	ENTRY();
+	if (!test_bit(EV_KEY, dev->evbit) ||
+	   (!test_bit(BTN_LEFT, dev->keybit) && !test_bit(BTN_TOUCH, dev->keybit)))
+		return NULL;
+
+	if ((!test_bit(EV_ABS, dev->evbit) || !test_bit(ABS_Y, dev->absbit)) &&
+	    (!test_bit(EV_ABS, dev->evbit) || !test_bit(ABS_X, dev->absbit)))
+		return NULL;
+
+	DBG("mouse connected handler %p dev %s\n",handler,dev->name);
+	mouse.handle.dev = dev;
+	mouse.handle.handler = handler;
+	mouse.handle.private = &mouse;
+	mouse.devfs = input_register_minor("rrts%d", 0, MOUSEDEV_MINOR_BASE);
+	DBG("handler %p\n",handler);
+	input_open_device(&mouse.handle);
+	DBG("exit");
+	return &mouse.handle;
+}
+
+static void mousedev_disconnect(struct input_handle *handle)
+{
+	struct mousedev *mousedev = handle->private;
+
+	ENTRY();
+	mousedev->exist = 0;
+
+	if (mousedev->open) {
+		input_close_device(handle);
+	} 
+}
+	
+static struct input_handler mouse_handler = {
+	event:		mousedev_event,
+	connect:	mousedev_connect,
+	disconnect:	mousedev_disconnect,
+	fops:		&mousedev_fops,
+	minor:		MOUSEDEV_MINOR_BASE,
+};
+
+static int mousedev_installed = 0;
+static int __init mousedev_init(void)
+{
+	ENTRY();
+	if(mousedev_installed++)
+		return 0;
+	memset(&mouse, 0, sizeof(struct mousedev));
+        mouse.ts_x = mouse.ts_y = 1000;
+        mouse.fb_x = 320;
+        mouse.fb_y = 240;
+	DBG("handler %p %d\n",mouse.handle,sizeof(struct mousedev));
+	input_register_handler(&mouse_handler);
+	init_waitqueue_head(&mouse.wait);
+	input_register_minor("mice", MOUSEDEV_MIX, MOUSEDEV_MINOR_BASE);
+	printk("mice: DSPLinux mouse device\n");
+
+	return 0;
+}
+
+static void __exit mousedev_exit(void)
+{
+	ENTRY();
+	if(!mousedev_installed--)
+		input_unregister_handler(&mouse_handler);
+}
+
+module_init(mousedev_init);
+module_exit(mousedev_exit);
+
+MODULE_AUTHOR("Greg Lonnon <glonnon@rigderun.com>");
+MODULE_DESCRIPTION("DSPLinux simulator mouse driver");
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_wdt.c linux-2.4.19/drivers/char/omap1510_wdt.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/omap1510_wdt.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/char/omap1510_wdt.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,348 @@
+/*
+ *	Industrial Computer Source WDT500/501 driver for Linux 2.1.x
+ *
+ *      (c) Copyright 2001 RidgeRun, Inc <www.ridgerun.com>
+ *	(c) Copyright 1996-1997 Alan Cox <alan@redhat.com>, All Rights Reserved.
+ *				http://www.redhat.com
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ *	
+ *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 
+ *	warranty for any of this software. This material is provided 
+ *	"AS-IS" and at no charge.	
+ *
+ *	(c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
+ *
+ *	Release 0.08.
+ *
+ *	Fixes
+ *		Dave Gregorich	:	Modularisation and minor bugs
+ *		Alan Cox	:	Added the watchdog ioctl() stuff
+ *		Alan Cox	:	Fixed the reboot problem (as noted by
+ *					Matt Crocker).
+ *		Alan Cox	:	Added wdt= boot option
+ *		Alan Cox	:	Cleaned up copy/user stuff
+ *		Tim Hockin	:	Added insmod parameters, comment cleanup
+ *					Parameterized timeout
+ *		Tigran Aivazian	:	Restructured wdt_init() to handle failures
+ *              Gordon McNutt   :       Leveraged for TI watchdog timers
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/smp_lock.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/malloc.h>
+#include <linux/ioport.h>
+#include <linux/fcntl.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+
+#include <asm/arch/timer.h>
+#include <asm/arch/ck.h>
+
+static int wdt_is_open;
+static int timer;
+
+#ifndef MODULE
+
+/**
+ *	wdt_setup:
+ *	@str: command line string
+ *
+ *	Setup options. N/A.
+ */
+ 
+static int __init wdt_setup(char *str)
+{
+	return 1;
+}
+
+__setup("wdt=", wdt_setup);
+
+#endif /* !MODULE */
+
+/**
+ *	wdt_interrupt:
+ *	@timer:		Timer number
+ *	@dev_id:	Unused as we don't allow multiple devices.
+ *
+ *	Handle an interrupt from the timer. This only happens when the timer
+ *      is configured in 'interrupt' instead of 'reset' mode (which is never
+ *      by this driver). I include this here as an example of how we could
+ *      do something else besides h/w reset (Dan mentioned some realtime
+ *      applications that might want to shutdown equipment or something 
+ *      instead of just blindly resetting the MPU).
+ */
+ 
+void wdt_cb(int timer, void *dev_id)
+{
+	printk(KERN_CRIT "WDT expired!\n");
+	
+#ifdef SOFTWARE_REBOOT
+#ifdef ONLY_TESTING
+		printk(KERN_CRIT "Would Reboot.\n");
+#else		
+		printk(KERN_CRIT "Initiating system reboot.\n");
+		machine_restart(NULL);
+#endif		
+#else
+		printk(KERN_CRIT "But since the WDT is configued in interrupt "\
+                       "mode -- without software reboot -- nothing will happen\n");
+#endif		
+}
+
+
+static long long wdt_llseek(struct file *file, long long offset, int origin)
+{
+	return -ESPIPE;
+}
+
+/**
+ *	wdt_ping:
+ *
+ *	Reset the counter. Each time we program the counter we have to program
+ *      a different value than the last time (see the OMAP1510 spec if you
+ *      don't believe me, but it's true). The counter always starts at about
+ *      19 seconds (max value).
+ */
+
+static int timeout = 19000000; /* 19 seconds */
+static void wdt_ping(void)
+{
+        if (timeout == 19000000) timeout = 18000000;
+        else timeout = 19000000;
+        timer_set_period(timer, timeout);
+}
+
+
+/**
+ *	wdt_write:
+ *	@file: file handle to the watchdog
+ *	@buf: buffer to write (unused as data does not matter here 
+ *	@count: count of bytes
+ *	@ppos: pointer to the position to write. No seeks allowed
+ *
+ *	A write to a watchdog device is defined as a keepalive signal. Any
+ *	write of data will do, as we we don't define content meaning.
+ */
+ 
+static ssize_t wdt_write(struct file *file, const char *buf, size_t count, 
+                         loff_t *ppos)
+{
+	/*  Can't seek (pwrite) on this device  */
+	if (ppos != &file->f_pos)
+		return -ESPIPE;
+
+	if(count)
+	{
+		wdt_ping();
+		return 1;
+	}
+	return 0;
+}
+
+/**
+ *	wdt_ioctl:
+ *	@inode: inode of the device
+ *	@file: file handle to the device
+ *	@cmd: watchdog command
+ *	@arg: argument pointer
+ *
+ *	The watchdog API defines a common set of functions for all watchdogs
+ *	according to their available features. We only actually usefully support
+ *	querying capabilities and current status. 
+ */
+ 
+static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+	unsigned long arg)
+{
+	static struct watchdog_info ident=
+	{
+                options: 0,
+		firmware_version: 0,
+		identity: "OMAP1510 WDT"
+	};
+	
+	switch(cmd)
+	{
+        default:
+                return -ENOIOCTLCMD;
+        case WDIOC_GETSUPPORT:
+                return copy_to_user((struct watchdog_info *)arg, &ident, 
+                                    sizeof(ident))?-EFAULT:0;
+                
+        case WDIOC_GETSTATUS:
+                return put_user(0, (int *)arg);
+        case WDIOC_GETBOOTSTATUS:
+                return put_user(0, (int *)arg);
+        case WDIOC_KEEPALIVE:
+                wdt_ping();
+                return 0;
+        }
+}
+
+/**
+ *	wdt_open:
+ *	@inode: inode of device
+ *	@file: file handle to device
+ *
+ *	Our misc device has been opened. It's single open and on open we load
+ *      the counter and start the countdown.
+ */
+ 
+static int wdt_open(struct inode *inode, struct file *file)
+{
+        int ret;
+
+	switch(MINOR(inode->i_rdev))
+	{
+		case WATCHDOG_MINOR:
+			if(wdt_is_open)
+				return -EBUSY;
+			/*
+			 *	Activate 
+			 */
+	 
+			wdt_is_open=1;
+                        /* This will automatically load the timer with its max
+                           count and start it running.
+                        */
+                        if ((ret = timer_set_action(timer,
+                                                    timer_action_reset)))
+                                goto fail;
+                        ck_enable(mpuwd_ck);
+			return 0;
+		case TEMP_MINOR:
+			return 0;
+		default:
+			return -ENODEV;
+	}
+ fail:
+        wdt_is_open = 0;
+        return ret;
+}
+
+/**
+ *	wdt_close:
+ *	@inode: inode to board
+ *	@file: file handle to board
+ *
+ *	The watchdog has a configurable API. There is a religious dispute 
+ *	between people who want their watchdog to be able to shut down and 
+ *	those who want to be sure if the watchdog manager dies the machine
+ *	reboots. In the former case we disable the counters, in the latter
+ *	case you have to open it again very soon.
+ */
+ 
+static int wdt_release(struct inode *inode, struct file *file)
+{
+	lock_kernel();
+	if(MINOR(inode->i_rdev)==WATCHDOG_MINOR)
+	{
+#ifndef CONFIG_WATCHDOG_NOWAYOUT	
+                ck_disable(mpuwd_ck);
+                timer_set_action(timer, timer_action_interrupt); /* reset off */
+#endif		
+		wdt_is_open=0;
+	}
+	unlock_kernel();
+	return 0;
+}
+
+/*
+ *	Kernel Interfaces
+ */
+ 
+ 
+static struct file_operations wdt_fops = {
+	owner:		THIS_MODULE,
+	llseek:		wdt_llseek,
+	write:		wdt_write,
+	ioctl:		wdt_ioctl,
+	open:		wdt_open,
+	release:	wdt_release,
+};
+
+static struct miscdevice wdt_miscdev=
+{
+	WATCHDOG_MINOR,
+	"watchdog",
+	&wdt_fops
+};
+
+/**
+ *	cleanup_module:
+ *
+ *	Unload the watchdog. You cannot do this with any file handles open.
+ *	If your watchdog is set to continue ticking on close and you unload
+ *	it, well it keeps ticking. We won't get the interrupt but the board
+ *	will not touch PC memory so all is fine. You just have to load a new
+ *	module in 19 seconds or reboot.
+ */
+ 
+void __exit wdt_exit(void)
+{
+	misc_deregister(&wdt_miscdev);
+	timer_unregister_cb(timer, &wdt_miscdev);
+}
+
+/**
+ * 	wdt_init:
+ *
+ *	Set up the WDT watchdog board. All we have to do is grab the
+ *	resources we require and bitch if anyone beat us to them.
+ *	The open() function will actually kick the board off.
+ *
+ */
+ 
+int __init wdt_init(void)
+{
+	int ret, feats;
+
+	ret = misc_register(&wdt_miscdev);
+	if (ret) {
+		printk(KERN_ERR "wdt: can't misc_register on minor=%d\n", 
+                       WATCHDOG_MINOR);
+		goto out;
+	}
+        for (timer = 0; timer < timer_get_num_timers(); timer++) {
+                timer_get_features(timer, &feats);
+                if (feats & TIMERF_RST)
+                        break;
+        }
+        if (timer == timer_get_num_timers()) {
+                printk(KERN_ERR "wdt: couldn't find the watchdog timer\n");
+                goto outmisc;
+        }
+	ret = timer_register_cb(timer, wdt_cb, &wdt_miscdev);
+	if(ret) {
+		printk(KERN_ERR "wdt: watchdog timer (%d) is not free.\n", timer);
+		goto outmisc;
+	}
+
+	ret = 0;
+	printk(KERN_INFO "DSPLinux Watchdog Driver (c) 2001 RidgeRun, Inc.\n");
+out:
+	return ret;
+outmisc:
+	misc_deregister(&wdt_miscdev);
+	goto out;
+}
+
+module_init(wdt_init);
+module_exit(wdt_exit);
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/char/serial.c linux-2.4.19/drivers/char/serial.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/char/serial.c	2002-08-03 03:39:43.000000000 +0300
+++ linux-2.4.19/drivers/char/serial.c	2003-01-09 19:49:04.000000000 +0200
@@ -311,6 +311,8 @@
 	{ "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO |
 		  UART_STARTECH },
 	{ "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }, 
+	{ "OMAP UART", 64, UART_CLEAR_FIFO | UART_USE_FIFO | 
+		  UART_STARTECH },
 	{ 0, 0}
 };
 
@@ -705,6 +707,11 @@
 		info->state->icount.tx++;
 		if (info->xmit.head == info->xmit.tail)
 			break;
+
+#ifdef CONFIG_ARCH_OMAP
+		// FIXME: Horrible hack to fix console corruption, is fifo on?
+		udelay(100);
+#endif
 	} while (--count > 0);
 	
 	if (CIRC_CNT(info->xmit.head,
@@ -842,6 +849,7 @@
 		if (status & UART_LSR_DR)
 			receive_chars(info, &status, regs);
 		check_modem_status(info);
+
 		if ((status & UART_LSR_THRE) ||
 			/* for buggy ELAN processors */
 			((iir & UART_IIR_ID) == UART_IIR_THRI))
@@ -914,7 +922,7 @@
 		    ((iir & UART_IIR_ID) == UART_IIR_THRI))
 			transmit_chars(info, 0);
 		if (pass_counter++ > RS_ISR_PASS_LIMIT) {
-#if SERIAL_DEBUG_INTR
+#ifdef SERIAL_DEBUG_INTR
 			printk("rs_single loop break.\n");
 #endif
 			break;
@@ -1235,6 +1243,28 @@
 	printk("starting up ttys%d (irq %d)...", info->line, state->irq);
 #endif
 
+#ifdef CONFIG_ARCH_OMAP
+	if (state->type == PORT_OMAP) {
+                serial_outp(info, UART_OMAP_MDR1, 0x07); /* disable UART */
+                serial_outp(info, UART_LCR, 0xBF);	/* select EFR */
+                serial_outp(info, UART_EFR, UART_EFR_ECB);
+                serial_outp(info, UART_LCR, UART_LCR_DLAB); /* set DLAB */
+                serial_outp(info, UART_DLL, 0x00);
+                serial_outp(info, UART_DLM, 0x00);
+                serial_outp(info, UART_LCR, 0x00);	/* reset DLAB */
+                serial_outp(info, UART_OMAP_SCR, 0x00);
+                serial_outp(info, UART_FCR, 0x00);
+                serial_outp(info, UART_MCR, 0x40);	/* enable TCR/TLR */
+                serial_outp(info, UART_OMAP_TCR, 0x0F);
+                serial_outp(info, UART_OMAP_TLR, 0x00);
+                serial_outp(info, UART_MCR, 0x00);
+                serial_outp(info, UART_LCR, 0xBF);	/* select EFR */
+                serial_outp(info, UART_EFR, 0x00);
+                serial_outp(info, UART_LCR, 0x00);	/* reset DLAB */
+                serial_outp(info, UART_OMAP_MDR1, 0x00); /* enable UART */
+        }
+#endif
+
 	if (uart_config[state->type].flags & UART_STARTECH) {
 		/* Wake up UART */
 		serial_outp(info, UART_LCR, 0xBF);
@@ -1789,6 +1819,16 @@
 		serial_outp(info, UART_EFR,
 			    (cflag & CRTSCTS) ? UART_EFR_CTS : 0);
 	}
+#ifdef CONFIG_ARCH_OMAP
+	if (info->state->type == PORT_OMAP) {
+		serial_outp(info, UART_LCR, cval);	/* reset DLAB */
+		if (baud ==115200) {
+			quot = 1;
+			serial_outp(info, UART_OMAP_OSC_12M_SEL, 1);
+		} else
+			serial_outp(info, UART_OMAP_OSC_12M_SEL, 0);
+	}
+#endif
 	serial_outp(info, UART_LCR, cval | UART_LCR_DLAB);	/* set DLAB */
 	serial_outp(info, UART_DLL, quot & 0xff);	/* LS of divisor */
 	serial_outp(info, UART_DLM, quot >> 8);		/* MS of divisor */
@@ -5488,7 +5528,11 @@
 	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
 		state->magic = SSTATE_MAGIC;
 		state->line = i;
+#ifdef CONFIG_ARCH_OMAP
+		state->type = PORT_OMAP;
+#else
 		state->type = PORT_UNKNOWN;
+#endif
 		state->custom_divisor = 0;
 		state->close_delay = 5*HZ/10;
 		state->closing_wait = 30*HZ;
@@ -5975,6 +6019,35 @@
 	 *	Disable UART interrupts, set DTR and RTS high
 	 *	and set speed.
 	 */
+#ifdef CONFIG_ARCH_OMAP
+	if (info->state->type == PORT_OMAP) {
+		serial_out(info, UART_OMAP_MDR1, 0x07);	/* disable UART */
+		serial_out(info, UART_LCR, 0xBF);	/* select EFR */
+		serial_out(info, UART_EFR, UART_EFR_ECB);
+		serial_out(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
+		serial_out(info, UART_DLL, 0x00);
+		serial_out(info, UART_DLM, 0x00);
+		serial_out(info, UART_LCR, cval);	/* reset DLAB */
+		serial_out(info, UART_OMAP_SCR, 0x00);
+		serial_out(info, UART_IER, 0x00);
+		serial_out(info, UART_FCR, UART_FCR_ENABLE_FIFO |
+					   UART_FCR_CLEAR_RCVR |
+					   UART_FCR_CLEAR_XMIT);
+		serial_out(info, UART_MCR, 0x40);	/* enable TCR/TLR */
+		serial_out(info, UART_OMAP_TCR, 0x0F);
+		serial_out(info, UART_OMAP_TLR, 0x00);
+		serial_out(info, UART_MCR, 0x00);
+		serial_out(info, UART_LCR, 0xBF);	/* select EFR */
+		serial_out(info, UART_EFR, 0x00);
+		serial_out(info, UART_LCR, cval);	/* reset DLAB */
+		serial_out(info, UART_OMAP_MDR1, 0x00);	/* enable UART */
+		if (baud == 115200) {
+			quot = 1;
+			serial_out(info, UART_OMAP_OSC_12M_SEL, 1);
+		} else
+			serial_out(info, UART_OMAP_OSC_12M_SEL, 0);
+	}
+#endif
 	serial_out(info, UART_LCR, cval | UART_LCR_DLAB);	/* set DLAB */
 	serial_out(info, UART_DLL, quot & 0xff);	/* LS of divisor */
 	serial_out(info, UART_DLM, quot >> 8);		/* MS of divisor */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/Config.in linux-2.4.19/drivers/i2c/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/Config.in	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/i2c/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -50,6 +50,10 @@
       dep_tristate 'Keywest I2C interface in Apple Core99 machines' CONFIG_I2C_KEYWEST $CONFIG_I2C
    fi
 
+   if [ "$CONFIG_ARCH_OMAP" = "y" ] ; then
+      dep_tristate '  OMAP I2C GPIO adapter' CONFIG_I2C_BIT_OMAP_GPIO $CONFIG_I2C
+   fi
+
 # This is needed for automatic patch generation: sensors code starts here
 # This is needed for automatic patch generation: sensors code ends here
 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-adap-omap1510.c linux-2.4.19/drivers/i2c/i2c-adap-omap1510.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-adap-omap1510.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/i2c/i2c-adap-omap1510.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,204 @@
+/*
+ * i2c-omap1510.c
+ *
+ * Simple bit algo I2C test driver for the TI OMAP1510.
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/parport.h>
+#include <linux/rtc.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include "i2c-omap1510.h"
+
+#undef	DEBUG
+#if	defined(DEBUG)
+#	define	DPRINTK(fmt, args...)	printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
+#else
+#	define	DPRINTK(fmt, args...)
+#endif
+
+
+static int iic_acquired;
+static int iic_data_out;
+static int iic_clock_out;
+
+
+/*
+ * Grab control of the I2C pins
+ */
+static inline void iic_acquirepins(void)
+{
+	I2C_SYSTEST |= SCL_O;
+	I2C_SYSTEST &= ~SDA_O;
+	iic_acquired = 1;
+	iic_clock_out = 1;
+	iic_data_out = 0;
+}
+
+/*
+ * Release control of the I2C pins
+ */
+static inline void iic_releasepins(void)
+{
+	I2C_SYSTEST |= SCL_O | SDA_O;
+	iic_acquired = 0;
+}
+
+/*
+ * Initialize the interface
+ */
+static void iic_init(void)
+{
+	I2C_SYSTEST = ST_EN | FREE | (3 << TMODE_SHIFT);
+	iic_releasepins();
+}
+
+
+/* --------- */
+
+static void bit_omap1510_setscl(void *data, int state)
+{
+	if (!iic_acquired)
+		iic_acquirepins();
+	if (!iic_clock_out) {
+		iic_clock_out = 1;
+	}
+	if (state) {
+		I2C_SYSTEST |= SCL_O;
+	} else {
+		I2C_SYSTEST &= ~SCL_O;
+	}
+}
+
+static void bit_omap1510_setsda(void *data, int state)
+{
+	if (!iic_acquired)
+		iic_acquirepins();
+	if (state) {
+		I2C_SYSTEST |= SDA_O;
+	} else {
+		I2C_SYSTEST &= ~SDA_O;
+	}
+} 
+
+static int bit_omap1510_getscl(void *data)
+{
+	if (!iic_acquired)
+		iic_acquirepins();
+
+	return (I2C_SYSTEST & SCL_I) ? 1 : 0;
+}
+
+static int bit_omap1510_getsda(void *data)
+{
+	if (!iic_acquired)
+		iic_acquirepins();
+	if (iic_data_out) {
+		iic_data_out = 0;
+	}
+	return (I2C_SYSTEST & SDA_I) ? 1 : 0;
+}
+
+/* ---------- */
+
+static int bit_omap1510_reg(struct i2c_client *client)
+{
+	return 0;
+}
+
+static int bit_omap1510_unreg(struct i2c_client *client)
+{
+	return 0;
+}
+
+static void bit_omap1510_inc_use(struct i2c_adapter *adap)
+{
+#ifdef MODULE
+	MOD_INC_USE_COUNT;
+#endif
+	iic_acquirepins();
+}
+
+static void bit_omap1510_dec_use(struct i2c_adapter *adap)
+{
+	iic_releasepins();
+#ifdef MODULE
+	MOD_DEC_USE_COUNT;
+#endif
+}
+
+static struct i2c_algo_bit_data bit_omap1510_data = {
+	data:		NULL,
+	setsda:		bit_omap1510_setsda,
+	setscl:		bit_omap1510_setscl,
+	getsda:		bit_omap1510_getsda,
+	getscl:		bit_omap1510_getscl,
+	udelay:		10,
+	mdelay:		10,
+	timeout:	100,
+};
+
+static struct i2c_adapter bit_omap1510_ops = {
+	name:			"OMAP1510",
+	id:			I2C_HW_B_IOC,
+	algo:			NULL,
+	algo_data:		&bit_omap1510_data,
+	inc_use:		bit_omap1510_inc_use,
+	dec_use:		bit_omap1510_dec_use,
+	client_register:	bit_omap1510_reg,
+	client_unregister:	bit_omap1510_unreg,
+};
+
+int __init i2c_omap1510_init(void)
+{
+	printk("i2c-omap1510.o: i2c OMAP1510 module\n");
+	/* reset hardware to sane state */
+	iic_init();
+	if (i2c_bit_add_bus(&bit_omap1510_ops) < 0) {
+		printk("i2c-omap1510: Unable to register with I2C\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+void __exit i2c_omap1510_exit(void)
+{
+	i2c_bit_del_bus(&bit_omap1510_ops);
+}
+
+
+#ifdef MODULE
+MODULE_AUTHOR("George G. Davis <davis_g@mvista.com>");
+MODULE_DESCRIPTION("I2C-Bus bit algo test driver for TI OMAP1510");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("GPL");
+#endif
+
+int init_module(void)
+{
+	return i2c_omap1510_init();
+}
+
+void cleanup_module(void)
+{
+        i2c_omap1510_exit();
+}
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-algo-omap1510.c linux-2.4.19/drivers/i2c/i2c-algo-omap1510.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-algo-omap1510.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/i2c/i2c-algo-omap1510.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,885 @@
+/*
+   -------------------------------------------------------------------------
+   i2c-algo-omap1510.c i2c driver algorithms for OMAP support
+   
+   Steve Johnson, RidgeRun, Inc.
+
+   Copyright 2002 RidgeRun, Inc.
+
+   ---------------------------------------------------------------------------
+   This file was highly leveraged from i2c-algo-ite.c, which was created
+   by Hai-Pao Fan:
+
+   Hai-Pao Fan, MontaVista Software, Inc.
+   hpfan@mvista.com or source@mvista.com
+
+   Copyright 2000 MontaVista Software Inc.
+
+   ---------------------------------------------------------------------------
+   This file was highly leveraged from i2c-algo-pcf.c, which was created
+   by Simon G. Vogl and Hans Berglund:
+
+
+     Copyright (C) 1995-1997 Simon G. Vogl
+                   1998-2000 Hans Berglund
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.		     */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and 
+   Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
+   <mbailey@littlefeet-inc.com> */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <asm/uaccess.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include "i2c-algo-omap1510.h"
+#include "i2c-omap1510.h"
+
+/* ----- global defines ----------------------------------------------- */
+#define DEB(x) if (i2c_debug>=1) x
+#define DEB2(x) if (i2c_debug>=2) x
+#define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
+#define DEBPROTO(x) if (i2c_debug>=9) x;
+ 	/* debug the protocol by showing transferred bits */
+#define DEF_TIMEOUT 16
+
+
+/* ----- global variables ---------------------------------------------	*/
+
+#ifdef SLO_IO
+	int jif;
+#endif
+
+/* module parameters:
+ */
+static int i2c_debug;
+static int omap1510_test;	/* see if the line-setting functions work	*/
+static int omap1510_scan;	/* have a look at what's hanging 'round		*/
+
+/* --- setting states on the bus with the right timing: ---------------	*/
+
+#define get_clock(adap) adap->getclock(adap->data)
+#define omap1510_outw(adap, reg, val) adap->setomap1510(adap->data, reg, val)
+#define omap1510_inw(adap, reg) adap->getomap1510(adap->data, reg)
+
+
+/* --- other auxiliary functions --------------------------------------	*/
+static inline int try_address(struct i2c_algo_omap1510_data *adap,
+                              unsigned int addr, int retries);
+
+
+static void omap1510_start(struct i2c_algo_omap1510_data *adap)
+{
+	omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_START_WRITE);
+}
+
+static void omap1510_start_clock(struct i2c_algo_omap1510_data *adap)
+{
+	omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_EN_CLK);
+}
+
+static void omap1510_stop(struct i2c_algo_omap1510_data *adap)
+{
+	omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) & ~I2C_START_WRITE);
+}
+
+static void omap1510_reset(struct i2c_algo_omap1510_data *adap)
+{
+	omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_SOFT_RESET);
+        udelay(100);
+	omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) & ~I2C_SOFT_RESET);
+}
+
+/*
+  Waiting on Bus Busy
+*/
+static int wait_for_bb(struct i2c_algo_omap1510_data *adap)
+{
+	int timeout = DEF_TIMEOUT;
+	short status;
+
+	status = omap1510_inw(adap, I2C_STATUS_ACTIVITY_REG);
+#ifndef STUB_I2C
+	while (timeout-- && (status & I2C_NOT_IDLE)) {
+		udelay(1000); /* How much is this? */
+		status = omap1510_inw(adap, I2C_STATUS_ACTIVITY_REG);
+	}
+#endif
+	if (timeout<=0) {
+		printk(KERN_ERR "Timeout, host is busy\n");
+		omap1510_reset(adap);
+	}
+	return(timeout<=0);
+}
+
+/*
+ * Puts this process to sleep for a period equal to timeout 
+ */
+static inline void omap1510_sleep(unsigned long timeout)
+{
+	schedule_timeout( timeout * HZ);
+}
+
+/* After we issue a transaction on the OMAP1510 bus, this function
+ * is called.  It puts this process to sleep until we get an interrupt from
+ * the controller telling us that the transaction we requested in complete.
+ * pin = Pending Interrupt Not
+ */
+static int wait_for_pin(struct i2c_algo_omap1510_data *adap, u16 *status) 
+{
+
+	int timeout = DEF_TIMEOUT * 3;
+	
+	*status = omap1510_inw(adap, I2C_STATUS_ACTIVITY_REG);
+//        DEB2(printk(__FUNCTION__ ": status 0x%x, status-and %x\n", *status, (*status & I2C_INTERRUPT)));
+#ifndef STUB_I2C
+	while (timeout-- && 
+//               ((*status & I2C_ERROR) == 0) &&
+//               ((*status & I2C_INTERRUPT) != I2C_INTERRUPT) &&
+               ((*status & I2C_NOT_IDLE) == I2C_NOT_IDLE)) {
+                adap->waitforpin();
+                *status = omap1510_inw(adap, I2C_STATUS_ACTIVITY_REG);
+//                DEB2(printk(__FUNCTION__ ": status 0x%x, status-and %x\n", *status, (*status & I2C_INTERRUPT)));
+	}
+#endif
+	if (timeout <= 0) {
+                DEB2(printk(__FUNCTION__ ": status 0x%x\n", *status));
+		return(-1);
+        }
+	else
+		return(0);
+}
+
+/*
+  FIFO Empty
+*/
+static int wait_for_fe(struct i2c_algo_omap1510_data *adap, u16 *status)
+{
+	int timeout = DEF_TIMEOUT;
+
+	*status = omap1510_inw(adap, I2C_STATUS_FIFO_REG);
+#ifndef STUB_I2C 
+	while (timeout-- && !(*status & I2C_FIFO_EMPTY)) {
+		udelay(1000);
+		omap1510_inw(adap, I2C_STATUS_FIFO_REG);
+	}
+#endif
+	if (timeout <= 0) 
+		return(-1);
+	else
+		return(0);
+}
+
+static int omap1510_init (struct i2c_algo_omap1510_data *adap)
+{
+        u16 command_register;
+        u16 clock;
+
+        // Initialize OMAP1510 I2C hardware       
+
+        // Disable i2c clock
+        command_register = omap1510_inw(adap, I2C_CMD_REG);
+        command_register &= ~I2C_EN_CLK;
+        omap1510_outw(adap, I2C_CMD_REG, command_register);
+
+        // Set clocks for standard 100kHz transmission mode
+        // set div2 = 9 ext_frq/(div1/div2 + 1)
+        clock = get_clock(adap);
+        omap1510_outw(adap, I2C_CONF_CLK_REF_REG, (clock & 0xff));
+        // set spike filter 2 ( = 3 master clocks), div1 2 ( = 4 )
+        omap1510_outw(adap, I2C_CONF_CLK_REG, ((clock & 0xff00) >> 8));
+
+        // Enable i2c clock & interrupts
+        command_register |= (I2C_EN_CLK | I2C_IRQ_EN);
+        omap1510_outw(adap, I2C_CMD_REG, command_register);
+
+        // Reset FIFO
+        command_register |= I2C_SOFT_RESET;
+        omap1510_outw(adap, I2C_CMD_REG, command_register);
+        command_register &= ~I2C_SOFT_RESET;
+        omap1510_outw(adap, I2C_CMD_REG, command_register);
+
+        // Set FIFO to 0 ( = 1 byte )
+        omap1510_outw(adap, I2C_CONF_FIFO_REG, 0xf0);
+
+	DEB2(printk("omap1510_init: Initialized OMAP1510 I2C Status 0x%x\n",
+                    omap1510_inw(adap, I2C_STATUS_ACTIVITY_REG)));
+	return 0;
+}
+
+
+/*
+ * Sanity check for the adapter hardware - check the reaction of
+ * the bus lines only if it seems to be idle.
+ */
+static int test_bus(struct i2c_algo_omap1510_data *adap, char *name) 
+{
+#if 0
+	int scl,sda;
+	sda=getsda(adap);
+	if (adap->getscl==NULL) {
+		printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n");
+		return 0;		
+	}
+	scl=getscl(adap);
+	printk("test_bus: Adapter: %s scl: %d  sda: %d -- testing...\n",
+               name,getscl(adap),getsda(adap));
+	if (!scl || !sda ) {
+		printk("test_bus: %s seems to be busy.\n",adap->name);
+		goto bailout;
+	}
+	sdalo(adap);
+	printk("test_bus:1 scl: %d  sda: %d \n",getscl(adap),
+	       getsda(adap));
+	if ( 0 != getsda(adap) ) {
+		printk("test_bus: %s SDA stuck high!\n",name);
+		sdahi(adap);
+		goto bailout;
+	}
+	if ( 0 == getscl(adap) ) {
+		printk("test_bus: %s SCL unexpected low while pulling SDA low!\n",
+                       name);
+		goto bailout;
+	}		
+	sdahi(adap);
+	printk("test_bus:2 scl: %d  sda: %d \n",getscl(adap),
+	       getsda(adap));
+	if ( 0 == getsda(adap) ) {
+		printk("test_bus: %s SDA stuck low!\n",name);
+		sdahi(adap);
+		goto bailout;
+	}
+	if ( 0 == getscl(adap) ) {
+		printk("test_bus: %s SCL unexpected low while SDA high!\n",
+		       adap->name);
+                goto bailout;
+	}
+	scllo(adap);
+	printk("test_bus:3 scl: %d  sda: %d \n",getscl(adap),
+	       getsda(adap));
+	if ( 0 != getscl(adap) ) {
+
+		sclhi(adap);
+		goto bailout;
+	}
+	if ( 0 == getsda(adap) ) {
+		printk("test_bus: %s SDA unexpected low while pulling SCL low!\n",
+                       name);
+		goto bailout;
+	}
+	sclhi(adap);
+	printk("test_bus:4 scl: %d  sda: %d \n",getscl(adap),
+	       getsda(adap));
+	if ( 0 == getscl(adap) ) {
+		printk("test_bus: %s SCL stuck low!\n",name);
+		sclhi(adap);
+		goto bailout;
+	}
+	if ( 0 == getsda(adap) ) {
+		printk("test_bus: %s SDA unexpected low while SCL high!\n",
+                       name);
+		goto bailout;
+	}
+	printk("test_bus: %s passed test.\n",name);
+	return 0;
+ bailout:
+	sdahi(adap);
+	sclhi(adap);
+	return -ENODEV;
+#endif
+	return (0);
+}
+
+/* ----- Utility functions
+ */
+
+
+/* Verify the device we want to talk to on the OMAP1510 bus really exists. */
+static inline int try_address(struct i2c_algo_omap1510_data *adap,
+                              unsigned int addr, int retries)
+{
+	int i = 0, ret = -1;
+	short status;
+
+	for (i=0;i<retries;i++) {
+		omap1510_start(adap);
+		if (wait_for_pin(adap, &status) == 0) {
+			if ((status & I2C_ERROR_DEVICE) == 0) { 
+//				omap1510_stop(adap);
+                                omap1510_reset(adap);   // flush FIFO
+				ret=1;
+				break;	/* success! */
+			}
+		}
+                DEB2(printk(__FUNCTION__ ": status 0x%x\n", status));
+		omap1510_stop(adap);
+		udelay(adap->udelay);
+	}
+
+	DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i,
+	                   addr));
+	return ret;
+}
+
+
+static int omap1510_sendbytes(struct i2c_adapter *i2c_adap,
+                              const char *buf, int count)
+{
+	struct i2c_algo_omap1510_data *adap = i2c_adap->algo_data;
+	int wrcount=0, timeout;
+	short status;
+	int loops, remainder, i, j;
+   
+	omap1510_outw(adap, I2C_ADDRESS_REG, (unsigned short)buf[wrcount++]);
+	count--;
+	if (count == 0)
+		return -EIO;
+
+	loops =  count / I2C_FIFO_MAX;		/* 16-byte FIFO */
+	remainder = count % I2C_FIFO_MAX;
+
+	if(loops) {
+		for(i=0; i<loops; i++) {
+
+			omap1510_outw(adap, I2C_CONF_FIFO_REG, I2C_FIFO_MASK);
+			for(j=0; j<I2C_FIFO_MAX; j++) {
+				omap1510_outw(adap, I2C_DATA_WRITE_REG, buf[wrcount++]); 
+			}
+
+                        if (!(omap1510_inw(adap, I2C_STATUS_FIFO_REG) & I2C_FIFO_FULL)) {
+                                DEB(printk(__FUNCTION__ ": FIFO not full when it should be\n"));
+                        }
+ 
+                        /* Issue WRITE command */
+                        omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_START_WRITE);
+
+			/* Wait for transmission to complete */
+			timeout = wait_for_pin(adap, &status);
+			if(timeout) {
+				omap1510_stop(adap);
+				printk(__FUNCTION__ ": %s write timeout.\n", i2c_adap->name);
+				return -EREMOTEIO; /* got a better one ?? */
+                        }
+			if (status & I2C_ERROR) {
+				omap1510_stop(adap);
+				printk(__FUNCTION__ ": %s write error - no ack.\n", i2c_adap->name);
+				return -EREMOTEIO; /* got a better one ?? */
+			}
+		}
+	}
+	if(remainder) {
+		omap1510_outw(adap, I2C_CONF_FIFO_REG, (remainder - 1));  // 0 based register
+		for(i=0; i < remainder; i++) {
+			omap1510_outw(adap, I2C_DATA_WRITE_REG, buf[wrcount++]);
+		}
+
+                if (!(omap1510_inw(adap, I2C_STATUS_FIFO_REG) & I2C_FIFO_FULL)) {
+                        DEB(printk(__FUNCTION__ ": FIFO not full when it should be\n"));
+                }
+ 
+                /* Issue WRITE command */
+                omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_START_WRITE);
+
+		timeout = wait_for_pin(adap, &status);
+		if(timeout) {
+			omap1510_stop(adap);
+			printk(__FUNCTION__ ": %s write timeout.\n", i2c_adap->name);
+			return -EREMOTEIO; /* got a better one ?? */
+		}
+#ifndef STUB_I2C
+		if (status & I2C_ERROR) { 
+			omap1510_stop(adap);
+			printk(__FUNCTION__ ": %s write error - no ack.\n", i2c_adap->name);
+			return -EREMOTEIO; /* got a better one ?? */
+		}
+#endif
+	}
+	omap1510_stop(adap);
+	return wrcount;
+}
+
+
+static int omap1510_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
+{
+	int rdcount=0, i, timeout;
+	short status;
+	struct i2c_algo_omap1510_data *adap = i2c_adap->algo_data;
+	int loops, remainder, j, bytes_read;
+		
+	loops = count / I2C_FIFO_MAX;				/* 16-byte FIFO */
+	remainder = count % I2C_FIFO_MAX;
+
+	if(loops) {
+		for(i=0; i<loops; i++) {
+
+			omap1510_outw(adap, I2C_CONF_FIFO_REG, I2C_FIFO_MASK);
+
+                        /* Issue READ command */
+                        omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_START_READ);
+
+			timeout = wait_for_pin(adap, &status);
+			if(timeout) {
+				omap1510_stop(adap);
+				printk(__FUNCTION__ ":  %s read timeout.\n", i2c_adap->name);
+				return (-1);
+			}
+#ifndef STUB_I2C
+			if (status & I2C_ERROR) {
+				omap1510_stop(adap);
+				printk(__FUNCTION__ ": %s read error - no ack.\n", i2c_adap->name);
+				return (-1);
+			}
+#endif
+
+			timeout = wait_for_fe(adap, &status);
+			if(timeout) {
+				omap1510_stop(adap);
+				printk(__FUNCTION__ ":  %s FIFO is empty\n", i2c_adap->name);
+				return (-1); 
+			}
+                        bytes_read = ((status >> I2C_READ_CPT_SHIFT) & 0xf);
+                        if (bytes_read != I2C_FIFO_MAX) {
+                                printk(__FUNCTION__ ": returned %d bytes instead of 16\n", bytes_read);
+                        }
+			for(j=0; j < bytes_read; j++) {
+				buf[rdcount++] = (omap1510_inw(adap, I2C_READ) & 0xf);
+			}
+		}
+	}
+
+
+	if(remainder) {
+                omap1510_outw(adap, I2C_CONF_FIFO_REG, remainder);
+
+                /* Issue READ command */
+                omap1510_outw(adap, I2C_CMD_REG, omap1510_inw(adap, I2C_CMD_REG) | I2C_START_READ);
+
+		timeout = wait_for_pin(adap, &status);
+		if(timeout) {
+			omap1510_stop(adap);
+			printk(__FUNCTION__ ":  %s read timeout.\n", i2c_adap->name);
+			return (-1);
+		}
+#ifndef STUB_I2C
+		if (status & I2C_ERROR) {
+			omap1510_stop(adap);
+			printk(__FUNCTION__ ": %s read error - no ack.\n", i2c_adap->name);
+			return (-1);
+		}
+#endif
+		timeout = wait_for_fe(adap, &status);
+		if(timeout) {
+			omap1510_stop(adap);
+			printk(__FUNCTION__ ":  %s FIFO is empty\n", i2c_adap->name);
+			return (-1);
+		}         
+
+                bytes_read = ((status >> I2C_READ_CPT_SHIFT) & 0xf);
+                if (bytes_read != I2C_FIFO_MAX) {
+                        printk(__FUNCTION__ ": returned %d bytes instead of 16\n", bytes_read);
+                }
+		for(i=0; i < bytes_read; i++) {
+                        buf[rdcount++] = (omap1510_inw(adap, I2C_READ) & 0xf);
+                }
+
+	}
+
+	omap1510_stop(adap);
+	return rdcount;
+}
+
+
+/* This function implements combined transactions.  Combined
+ * transactions consist of combinations of reading and writing blocks of data.
+ * Each transfer (i.e. a read or a write) is separated by a repeated start
+ * condition.
+ */
+#if 0
+static int omap1510_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 
+{
+        int i;
+        struct i2c_msg *pmsg;
+        int ret;
+
+        DEB2(printk("Beginning combined transaction\n"));
+
+        for(i=0; i<(num-1); i++) {
+                pmsg = &msgs[i];
+                if(pmsg->flags & I2C_M_RD) {
+                        DEB2(printk("  This one is a read\n"));
+                        ret = omap1510_readbytes(i2c_adap, pmsg->buf, pmsg->len, OMAP1510_COMBINED_XFER);
+                }
+                else if(!(pmsg->flags & I2C_M_RD)) {
+                        DEB2(printk("This one is a write\n"));
+                        ret = omap1510_sendbytes(i2c_adap, pmsg->buf, pmsg->len, OMAP1510_COMBINED_XFER);
+                }
+        }
+        /* Last read or write segment needs to be terminated with a stop */
+        pmsg = &msgs[i];
+
+        if(pmsg->flags & I2C_M_RD) {
+                DEB2(printk("Doing the last read\n"));
+                ret = omap1510_readbytes(i2c_adap, pmsg->buf, pmsg->len, OMAP1510_SINGLE_XFER);
+        }
+        else if(!(pmsg->flags & I2C_M_RD)) {
+                DEB2(printk("Doing the last write\n"));
+                ret = omap1510_sendbytes(i2c_adap, pmsg->buf, pmsg->len, OMAP1510_SINGLE_XFER);
+        }
+
+        return ret;
+}
+#endif
+
+
+/* Whenever we initiate a transaction, the first byte clocked
+ * onto the bus after the start condition is the address (7 bit) of the
+ * device we want to talk to.  This function manipulates the address specified
+ * so that it makes sense to the hardware when written to the OMAP1510 peripheral.
+ *
+ * Note: 10 bit addresses are not supported in this driver, although they are
+ * supported by the hardware.  This functionality needs to be implemented.
+ */
+static inline int omap1510_doAddress(struct i2c_algo_omap1510_data *adap,
+                                     struct i2c_msg *msg, int retries) 
+{
+	unsigned short flags = msg->flags;
+	unsigned int addr;
+	int ret;
+
+/* Ten bit addresses not supported right now */
+	if ( (flags & I2C_M_TEN)  ) { 
+#if 0
+		addr = 0xf0 | (( msg->addr >> 7) & 0x03);
+		DEB2(printk("addr0: %d\n",addr));
+		ret = try_address(adap, addr, retries);
+		if (ret!=1) {
+			printk(__FUNCTION__ ": died at extended address code.\n");
+			return -EREMOTEIO;
+		}
+		omap1510_outw(adap,msg->addr & 0x7f);
+		if (ret != 1) {
+			printk(__FUNCTION__ ": died at 2nd address code.\n");
+			return -EREMOTEIO;
+		}
+		if ( flags & I2C_M_RD ) {
+			i2c_repstart(adap);
+			addr |= 0x01;
+			ret = try_address(adap, addr, retries);
+			if (ret!=1) {
+				printk(__FUNCTION__ ": died at extended address code.\n");
+				return -EREMOTEIO;
+			}
+		}
+#else
+                return -EREMOTEIO;
+#endif
+	} else {
+
+		addr = ( msg->addr << 1 );
+
+                /*
+                  We have the R/W bit of I2C_CMD_REG to set the RD bit,
+                  so don't use the standard bit-banging code.
+                */
+#if 0
+		if (flags & I2C_M_RD )
+			addr |= 1;
+		if (flags & I2C_M_REV_DIR_ADDR )
+			addr ^= 1;
+#endif
+
+		if ((omap1510_inw(adap, I2C_DEVICE_REG) & 0x7f) != addr) {
+			omap1510_outw(adap, I2C_DEVICE_REG, addr);
+			ret = try_address(adap, addr, retries);
+			if (ret!=1) {
+				DEB(printk(__FUNCTION__ ": died at address code.\n"));
+				return -EREMOTEIO;
+			}
+		}
+
+        }
+
+	return 0;
+}
+
+
+/* Description: Prepares the controller for a transaction (clearing status
+ * registers, data buffers, etc), and then calls either omap1510_readbytes or
+ * omap1510_sendbytes to do the actual transaction.
+ *
+ * still to be done: Before we issue a transaction, we should
+ * verify that the bus is not busy or in some unknown state.
+ */
+static int omap1510_xfer(struct i2c_adapter *i2c_adap,
+                         struct i2c_msg msgs[], 
+                         int num)
+{
+	struct i2c_algo_omap1510_data *adap = i2c_adap->algo_data;
+	struct i2c_msg *pmsg;
+	int i = 0;
+	int ret, timeout;
+       
+	pmsg = &msgs[i];
+
+        // length 0 generally means a probe, so don't fail.
+	if(!pmsg->len) {
+		DEB2(printk(__FUNCTION__ ": read/write length is 0\n");)
+//                        return -EIO;
+	}
+
+        omap1510_start_clock(adap);
+
+	/* Wait for any pending transfers to complete */
+	timeout = wait_for_bb(adap);
+	if (timeout) {
+		DEB2(printk(__FUNCTION__ ": Timeout waiting for host not busy\n");)
+                        return -EIO;
+	}
+
+	/* Flush FIFO */
+	omap1510_reset(adap);
+
+	/* Load address */
+	ret = omap1510_doAddress(adap, pmsg, i2c_adap->retries);
+	if (ret) {
+		return -EIO;
+        }
+        
+#if 0
+	/* Combined transaction (read and write) */
+	if(num > 1) {
+                DEB2(printk(__FUNCTION__ ": Call combined transaction\n"));
+                ret = omap1510_combined_transaction(i2c_adap, msgs, num);
+        }
+#endif
+        
+	DEB3(printk(__FUNCTION__ ": Msg %d, addr=0x%x, flags=0x%x, len=%d\n",
+                    i, msgs[i].addr, msgs[i].flags, msgs[i].len));
+        
+        if (pmsg->len) {
+                if(pmsg->flags & I2C_M_RD) 		/* Read */
+                        ret = omap1510_readbytes(i2c_adap, pmsg->buf, pmsg->len);
+                else {													/* Write */ 
+//                udelay(1000);
+                        ret = omap1510_sendbytes(i2c_adap, pmsg->buf, pmsg->len);
+                }
+        }
+        
+	if (ret != pmsg->len) {
+		DEB2(printk(__FUNCTION__ ": error or fail on read/write %d bytes.\n",ret)); 
+        }
+	else {
+		DEB3(printk(__FUNCTION__ ": read/write %d bytes.\n",ret));
+        }
+        
+        omap1510_stop(adap);
+	return ret;
+}
+
+
+/* Implements device specific ioctls.  Higher level ioctls can
+ * be found in i2c-core.c and are typical of any i2c controller (specifying
+ * slave address, timeouts, etc).  These ioctls take advantage of any hardware
+ * features built into the controller for which this algorithm-adapter set
+ * was written.  These ioctls allow you to take control of the data and clock
+ * lines and set the either high or low,
+ * similar to a GPIO pin.
+ */
+static int algo_control(struct i2c_adapter *adapter, 
+                        unsigned int cmd, unsigned long arg)
+{
+
+        struct i2c_algo_omap1510_data *adap = adapter->algo_data;
+        struct i2c_omap1510_msg s_msg;
+        char *buf;
+	int ret;
+
+        if (cmd == I2C_SREAD) {
+		if(copy_from_user(&s_msg, (struct i2c_omap1510_msg *)arg, 
+                                  sizeof(struct i2c_omap1510_msg))) 
+			return -EFAULT;
+		buf = kmalloc(s_msg.len, GFP_KERNEL);
+		if (buf== NULL)
+			return -ENOMEM;
+
+		/* Flush FIFO */
+                omap1510_reset(adap);
+
+		/* Load address */
+		omap1510_outw(adap, I2C_DEVICE_REG, s_msg.addr<<1);
+		omap1510_outw(adap, I2C_ADDRESS_REG, s_msg.waddr & 0xff);
+
+		ret = omap1510_readbytes(adapter, buf, s_msg.len);
+		if (ret>=0) {
+			if(copy_to_user( s_msg.buf, buf, s_msg.len) ) 
+				ret = -EFAULT;
+		}
+		kfree(buf);
+	}
+	return 0;
+}
+
+
+#if 0            // use default instead
+static u32 omap1510_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C;
+}
+#endif
+
+/* -----exported algorithm data: -------------------------------------	*/
+
+static struct i2c_algorithm omap1510_algo = {
+	"OMAP1510 I2C algorithm",
+	I2C_ALGO_EXP,
+	omap1510_xfer,		/* master_xfer	*/
+	NULL,				/* smbus_xfer	*/
+	NULL,				/* slave_xmit		*/
+	NULL,				/* slave_recv		*/
+	algo_control,			/* ioctl		*/
+//	omap1510_func,			/* functionality	*/
+};
+
+
+/* 
+ * registering functions to load algorithms at runtime 
+ */
+int i2c_omap1510_add_bus(struct i2c_adapter *adap)
+{
+	int i;
+	short status;
+	struct i2c_algo_omap1510_data *omap1510_adap = adap->algo_data;
+
+	if (omap1510_test) {
+		int ret = test_bus(omap1510_adap, adap->name);
+		if (ret<0)
+			return -ENODEV;
+	}
+
+	DEB2(printk("i2c-algo-omap1510: hw routines for %s registered.\n",
+	            adap->name));
+
+	/* register new adapter to i2c module... */
+
+	adap->id |= omap1510_algo.id;
+	adap->algo = &omap1510_algo;
+
+	adap->timeout = 100;	/* default values, should	*/
+	adap->retries = 3;	/* be replaced by defines	*/
+	adap->flags = 0;
+
+#ifdef MODULE
+	MOD_INC_USE_COUNT;
+#endif
+
+	i2c_add_adapter(adap);
+	omap1510_init(omap1510_adap);
+
+	/* scan bus */
+	/* By default scanning the bus is turned off. */
+	if (omap1510_scan) {
+		printk(KERN_INFO " i2c-algo-omap1510: scanning bus %s.\n",
+		       adap->name);
+		for (i = 0x00; i < 0x7f; i+=2) {
+                        omap1510_reset(omap1510_adap);
+                        while (omap1510_inw(omap1510_adap, I2C_STATUS_ACTIVITY_REG) & 0xf) {
+                                omap1510_reset(omap1510_adap);
+                        }
+			omap1510_outw(omap1510_adap, I2C_DEVICE_REG, i);
+			omap1510_start(omap1510_adap);
+			if ( (wait_for_pin(omap1510_adap, &status) == 0) && 
+                             ((status & I2C_ERROR_DEVICE) == 0) ) { 
+				printk("\n(%02x)\n",i>>1); 
+			} else {
+				printk("."); 
+			}
+//			udelay(omap1510_adap->udelay);
+//                        printk("status 0x%x, i 0x%x\n", status, i);
+		}
+	}
+	return 0;
+}
+
+
+int i2c_omap1510_del_bus(struct i2c_adapter *adap)
+{
+	int res;
+	if ((res = i2c_del_adapter(adap)) < 0)
+		return res;
+	DEB2(printk("i2c-algo-omap1510: adapter unregistered: %s\n",adap->name));
+
+#ifdef MODULE
+	MOD_DEC_USE_COUNT;
+#endif
+	return 0;
+}
+
+
+int __init i2c_algo_omap1510_init (void)
+{
+	printk(KERN_INFO "OMAP1510 (i2c) algorithm module\n");
+	return 0;
+}
+
+
+void i2c_algo_omap1510_exit(void)
+{
+	return;
+}
+
+
+EXPORT_SYMBOL(i2c_omap1510_add_bus);
+EXPORT_SYMBOL(i2c_omap1510_del_bus);
+
+/* The MODULE_* macros resolve to nothing if MODULES is not defined
+ * when this file is compiled.
+ */
+MODULE_AUTHOR("RidgeRun");
+MODULE_DESCRIPTION("OMAP1510 I2C algorithm");
+MODULE_LICENSE("GPL");
+
+MODULE_PARM(omap1510_test, "i");
+MODULE_PARM(omap1510_scan, "i");
+MODULE_PARM(i2c_debug,"i");
+
+MODULE_PARM_DESC(omap1510_test, "Test if the I2C bus is available");
+MODULE_PARM_DESC(omap1510_scan, "Scan for active chips on the bus");
+MODULE_PARM_DESC(i2c_debug,
+        "debug level - 0 off; 1 normal; 2,3 more verbose; 9 omap1510-protocol");
+
+
+/* This function resolves to init_module (the function invoked when a module
+ * is loaded via insmod) when this file is compiled with MODULES defined.
+ * Otherwise (i.e. if you want this driver statically linked to the kernel),
+ * a pointer to this function is stored in a table and called
+ * during the intialization of the kernel (in do_basic_setup in /init/main.c) 
+ *
+ * All this functionality is complements of the macros defined in linux/init.h
+ */
+module_init(i2c_algo_omap1510_init);
+
+
+/* If MODULES is defined when this file is compiled, then this function will
+ * resolved to cleanup_module.
+ */
+module_exit(i2c_algo_omap1510_exit);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-algo-omap1510.h linux-2.4.19/drivers/i2c/i2c-algo-omap1510.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-algo-omap1510.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/i2c/i2c-algo-omap1510.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,72 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-algo-omap1510.h i2c driver algorithms for OMAP1510 adapters           */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-97 Simon G. Vogl
+                   1998-99 Hans Berglund
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* Modifications by MontaVista Software, 2001
+   Changes made to support the ITE IIC peripheral */
+
+/* Modifications by RidgeRun, Inc.
+   Changes made to support the OMAP1510 controller */
+
+
+#ifndef I2C_ALGO_OMAP_H
+#define I2C_ALGO_OMAP_H 
+
+#include <linux/i2c.h>
+
+/* Example of a sequential read request:
+	struct i2c_iic_msg s_msg; 
+
+	s_msg.addr=device_address;
+	s_msg.len=length;
+	s_msg.buf=buffer;
+	s_msg.waddr=word_address;
+	ioctl(file, I2C_SREAD, &s_msg);
+ */
+#define I2C_SREAD	0x780	/* SREAD ioctl command */
+
+struct i2c_omap1510_msg {
+	__u16 addr;	/* device address */
+	__u16 waddr;	/* word address */
+	short len;	/* msg length */
+	char *buf;	/* pointer to msg data */
+};
+
+struct i2c_algo_omap1510_data {
+	void *data;		/* private data for low-level routines	*/
+	void (*setomap1510) (void *data, int ctl, u16 val);
+	u16  (*getomap1510) (void *data, int ctl);
+	int  (*getown) (void *data);
+	int  (*getclock) (void *data);
+	void (*waitforpin) (void);     
+
+	/* local settings */
+	int udelay;
+	int mdelay;
+	int timeout;
+};
+
+int i2c_omap1510_add_bus(struct i2c_adapter *);
+int i2c_omap1510_del_bus(struct i2c_adapter *);
+
+#endif /* I2C_ALGO_OMAP_H */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-omap1510.h linux-2.4.19/drivers/i2c/i2c-omap1510.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/i2c-omap1510.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/i2c/i2c-omap1510.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,108 @@
+/*
+ * File: i2c-omap1510.h
+ *
+ * TI OMAP1510 I2C module register definitions
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef I2C_OMAP1510_H
+#define I2C_OMAP1510_H
+	
+/* I2C Registers: */
+
+#define I2C_BASE	(0xfffb3800)
+#define I2C_REV		(*(volatile u16 *)(I2C_BASE + 0x0))
+#define I2C_IE		(*(volatile u16 *)(I2C_BASE + 0x4))
+#define I2C_STAT	(*(volatile u16 *)(I2C_BASE + 0x8))
+#define I2C_IV		(*(volatile u16 *)(I2C_BASE + 0xc))
+#define I2C_BUF		(*(volatile u16 *)(I2C_BASE + 0x14))
+#define I2C_CNT		(*(volatile u16 *)(I2C_BASE + 0x18))
+#define I2C_DATA	(*(volatile u16 *)(I2C_BASE + 0x1c))
+#define I2C_CON		(*(volatile u16 *)(I2C_BASE + 0x24))
+#define I2C_OA		(*(volatile u16 *)(I2C_BASE + 0x28))
+#define I2C_SA		(*(volatile u16 *)(I2C_BASE + 0x2c))
+#define I2C_PSC		(*(volatile u16 *)(I2C_BASE + 0x30))
+#define I2C_SCLL	(*(volatile u16 *)(I2C_BASE + 0x34))
+#define I2C_SCLH	(*(volatile u16 *)(I2C_BASE + 0x38))
+#define I2C_SYSTEST	(*(volatile u16 *)(I2C_BASE + 0x3c))
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+
+#define XRDY_IE	(1 << 4)	// Transmit data ready interrupt enable
+#define RRDY_IE	(1 << 3)	// Receive data ready interrupt enable
+#define ARDY_IE	(1 << 2)	// Register access ready interrupt enable
+#define NACK_IE	(1 << 1)	// No acknowledgment interrupt enable
+#define AL_IE	(1 << 0)	// Arbitration lost interrupt enable
+
+/* I2C Status Register (I2C_STAT): */
+
+#define SBD	(1 << 15)	// Single byte data
+#define BB	(1 << 12)	// Bus busy
+#define ROVR	(1 << 11)	// Receive overrun
+#define XUDF	(1 << 10)	// Transmit underflow
+#define AAS	(1 << 9)	// Address as slave
+#define AD0	(1 << 8)	// Address zero
+#define XRDY	(1 << 4)	// Transmit data ready
+#define RRDY	(1 << 3)	// Receive data ready
+#define ARDY	(1 << 2)	// Register access ready
+#define NACK	(1 << 1)	// No acknowledgment interrupt enable
+#define AL	(1 << 0)	// Arbitration lost interrupt enable
+
+/* I2C Interrupt Vector Register (I2C_IV): */
+
+#define INTCODE_MASK	7
+#define INTCODE_AL	1
+#define	INTCODE_NAK	2
+#define INTCODE_ARDY	3
+#define INTCODE_RRDY	4
+#define INTCODE_XRDY	5
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define RDMA_EN		(1 << 15)	// Receive DMA channel enable
+#define XDMA_EN		(1 << 7)	// Transmit DMA channel enable
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_EN	(1 << 15)	// I2C module enable
+#define BE	(1 << 14)	// Big endian mode
+#define STB	(1 << 11)	// Start byte mode (master mode only)
+#define MST	(1 << 10)	// Master/slave mode
+#define TRX	(1 << 9)	// Transmitter/receiver mode (master mode only)
+#define XA	(1 << 8)	// Expand address
+#define RM	(1 << 2)	// Repeat mode (master mode only)
+#define STP	(1 << 1)	// Stop condition (master mode only)
+#define STT	(1 << 0)	// Start condition (master mode only)
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define ST_EN	(1 << 15)		// System test enable
+#define FREE	(1 << 14)		// Free running mode (on breakpoint)
+#define TMODE_MASK	(3 << 12)	// Test mode select
+#define TMODE_SHIFT	(12)		// Test mode select
+#define SCL_I	(1 << 3)	// SCL line sense input value
+#define SCL_O	(1 << 2)	// SCL line drive output value
+#define SDA_I	(1 << 1)	// SDA line sense input value
+#define SDA_O	(1 << 0)	// SDA line drive output value
+
+#endif  // I2C_OMAP1510_H
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/i2c/Makefile linux-2.4.19/drivers/i2c/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/i2c/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/i2c/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -6,6 +6,7 @@
 
 export-objs	:= i2c-core.o i2c-algo-bit.o i2c-algo-pcf.o \
 		   i2c-algo-ite.o i2c-proc.o
+export-objs	+= i2c-algo-omap1510.o i2c-adap-omap1510.o
 
 # Init order: core, chardev, bit adapters, pcf adapters
 
@@ -19,6 +20,8 @@
 obj-$(CONFIG_I2C_VELLEMAN)	+= i2c-velleman.o
 obj-$(CONFIG_I2C_FRODO)		+= i2c-frodo.o
 obj-$(CONFIG_I2C_OMAHA)		+= i2c-omaha.o
+##obj-$(CONFIG_I2C_BIT_OMAP_GPIO) += i2c-algo-omap1510.o i2c-adap-omap1510.o
+obj-$(CONFIG_I2C_BIT_OMAP_GPIO) += i2c-algo-bit.o i2c-adap-omap1510.o
 
 # PCF adapters
 obj-$(CONFIG_I2C_ALGOPCF)	+= i2c-algo-pcf.o
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/l3/Config.in linux-2.4.19/drivers/l3/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/l3/Config.in	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/l3/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -7,6 +7,7 @@
 tristate 'L3 support' CONFIG_L3
 dep_bool '  L3 bit-banging interfaces' CONFIG_L3_ALGOBIT $CONFIG_L3
 dep_bool '    SA11x0 GPIO adapter' CONFIG_L3_BIT_SA1100_GPIO $CONFIG_L3_ALGOBIT $CONFIG_ARCH_SA1100
+dep_bool '    OMAP GPIO adapter' CONFIG_L3_BIT_OMAP_GPIO $CONFIG_L3_ALGOBIT $CONFIG_ARCH_OMAP
 
 comment 'Other L3 adapters'
 dep_bool '  SA1111 adapter' CONFIG_L3_SA1111 $CONFIG_L3
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/l3/l3-bit-omap1510.c linux-2.4.19/drivers/l3/l3-bit-omap1510.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/l3/l3-bit-omap1510.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/l3/l3-bit-omap1510.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,193 @@
+/*
+ *  Derived from:
+ *   linux/drivers/l3/l3-bit-sa1100.c
+ *
+ *  Copyright (C) 2001 Russell King
+ *  Copyright (C) 2001 Steve Johnson (stevej@ridgerun.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is a L3 bus driver.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/l3/algo-bit.h>
+
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#define NAME "l3-bit-omap1510-gpio"
+
+struct bit_data {
+	unsigned int	sda;
+	unsigned int	scl;
+	unsigned int	l3_mode;
+};
+
+/*
+ * L3 bus GPIO pin definitions
+ */
+
+#define L3_DataPin	(1 << 8)
+#define L3_ClockPin	(1 << 7)
+#define L3_ModePin	(1 << 6)
+
+   /* GPIO Alternate Function Reg.    */
+#define GAFR (*(volatile u16 *) GPIO_INT_MASK_REG)  
+   /* GPIO Pin output Set Reg.        */
+#define GPSR (*(volatile u16 *) GPIO_DATA_OUTPUT_REG)
+   /* GPIO Pin output Clear Reg.      */
+#define GPCR GPSR
+   /* GPIO Pin Direction Reg.         */
+#define GPDR (*(volatile u16 *) GPIO_DIR_CONTROL_REG)
+   /* GPIO Pin Level Reg.             */
+#define GPLR (*(volatile u16 *) GPIO_DATA_INPUT_REG)
+   /* GPIO Pin Control Reg.             */
+#define GPCtlR (*(volatile u16 *) GPIO_PIN_CONTROL_REG)
+
+
+static int getsda(void *data)
+{
+	struct bit_data *bits = data;
+
+	return GPLR & bits->sda;
+}
+
+/*
+ * iPAQs need the clock line driven hard high and low.
+ */
+static void l3_setscl(void *data, int state)
+{
+	struct bit_data *bits = data;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (state)
+		GPSR |= bits->scl;
+	else
+		GPCR &= ~bits->scl;
+	GPDR &= ~bits->scl;              // 0 for output
+	local_irq_restore(flags);
+}
+
+static void l3_setsda(void *data, int state)
+{
+	struct bit_data *bits = data;
+
+	if (state)
+		GPSR |= bits->sda;
+	else
+		GPCR &= ~bits->sda;
+}
+
+static void l3_setdir(void *data, int in)
+{
+	struct bit_data *bits = data;
+	unsigned long flags;
+
+	local_irq_save(flags);
+        // 0 for output
+	if (in)
+		GPDR |= bits->sda;
+	else
+		GPDR &= ~bits->sda;
+	local_irq_restore(flags);
+}
+
+static void l3_setmode(void *data, int state)
+{
+	struct bit_data *bits = data;
+
+	if (state)
+		GPSR |= bits->l3_mode;
+	else
+		GPCR &= ~bits->l3_mode;
+}
+
+static struct l3_algo_bit_data l3_bit_data = {
+	data:		NULL,
+	setdat:		l3_setsda,
+	setclk:		l3_setscl,
+	setmode:	l3_setmode,
+	setdir:		l3_setdir,
+	getdat:		getsda,
+	data_hold:	1,
+	data_setup:	1,
+	clock_high:	1,
+	mode_hold:	1,
+	mode_setup:	1,
+};
+
+static DECLARE_MUTEX(l3_lock);
+#define LOCK		&l3_lock
+
+static struct l3_adapter l3_adapter = {
+	owner:		THIS_MODULE,
+	name:		NAME,
+	algo_data:	&l3_bit_data,
+	lock:		LOCK,
+};
+
+static struct bit_data bit_data;
+
+static int __init l3_init(struct bit_data *bits)
+{
+	l3_bit_data.data = bits;
+	return l3_bit_add_bus(&l3_adapter);
+}
+
+static void __exit l3_exit(void)
+{
+	struct bit_data *bit = &bit_data;
+
+        GPCR &= ~(bit->sda | bit->scl | bit->l3_mode);   // turn off
+
+	l3_bit_del_bus(&l3_adapter);
+}
+
+static int __init bus_init(void)
+{
+	struct bit_data *bit = &bit_data;
+	unsigned long flags;
+	int ret;
+
+        bit->sda     = L3_DataPin;
+        bit->scl     = L3_ClockPin;
+        bit->l3_mode = L3_ModePin;
+
+	if (!bit->sda)
+		return -ENODEV;
+
+	/*
+	 * Default level for L3 mode is low.
+	 * We set SCL and SDA high (i2c idle state).
+	 */
+	local_irq_save(flags);
+        GPDR |= (bit->sda | bit->scl | bit->l3_mode);   // input while changing state
+        GAFR |= (bit->sda | bit->scl | bit->l3_mode);   // not ints 
+        GPCtlR |= (bit->sda | bit->scl | bit->l3_mode); // MPU pin
+        GPSR |= (bit->sda | bit->scl | bit->l3_mode);   // 1 output
+        GPDR &= ~(bit->sda | bit->scl | bit->l3_mode);  // 0 for output
+	local_irq_restore(flags);
+
+        ret = l3_init(bit);
+
+	return ret;
+}
+
+static void __exit bus_exit(void)
+{
+	l3_exit();
+}
+
+module_init(bus_init);
+module_exit(bus_exit);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/l3/Makefile linux-2.4.19/drivers/l3/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/l3/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/drivers/l3/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -16,6 +16,7 @@
 l3-$(CONFIG_L3_ALGOBIT)		+= l3-algo-bit.o
 l3-$(CONFIG_BIT_SA1100_GPIO)	+= l3-bit-sa1100.o
 l3-$(CONFIG_L3_SA1111)		+= l3-sa1111.o
+l3-$(CONFIG_L3_BIT_OMAP_GPIO)	+= l3-bit-omap1510.o
 
 obj-$(CONFIG_L3)		+= l3-core.o $(l3-y) $(l3-drv-y)
 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/mtd/bootldr.c linux-2.4.19/drivers/mtd/bootldr.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/mtd/bootldr.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/mtd/bootldr.c	2003-01-09 17:48:44.000000000 +0200
@@ -0,0 +1,214 @@
+/*
+ * Read flash partition table from Compaq Bootloader
+ *
+ * Copyright 2001 Compaq Computer Corporation.
+ *
+ * $Id: bootldr.c,v 1.1.1.1 2003/01/09 15:48:44 tmlind Exp $
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ */
+
+/*
+ * Maintainer: Jamey Hicks (jamey.hicks@compaq.com)
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/setup.h>
+#include <linux/bootmem.h>
+
+#define FLASH_PARTITION_NAMELEN 32
+enum LFR_FLAGS {
+   LFR_SIZE_PREFIX = 1,		/* prefix data with 4-byte size */
+   LFR_PATCH_BOOTLDR = 2,	/* patch bootloader's 0th instruction */
+   LFR_KERNEL = 4,		/* add BOOTIMG_MAGIC, imgsize and VKERNEL_BASE to head of programmed region (see bootldr.c) */
+   LFR_EXPAND = 8               /* expand partition size to fit rest of flash */
+};
+
+// the tags are parsed too early to malloc or alloc_bootmem so we'll fix it
+// for now
+#define MAX_NUM_PARTITIONS 8
+typedef struct FlashRegion {
+   char name[FLASH_PARTITION_NAMELEN];
+   unsigned long base;
+   unsigned long size;
+   enum LFR_FLAGS flags;
+} FlashRegion;
+
+typedef struct BootldrFlashPartitionTable {
+  int magic; /* should be filled with 0x646c7470 (btlp) BOOTLDR_PARTITION_MAGIC */
+  int npartitions;
+  struct FlashRegion partition[8];
+} BootldrFlashPartitionTable;
+
+#define BOOTLDR_MAGIC      0x646c7462        /* btld: marks a valid bootldr image */
+#define BOOTLDR_PARTITION_MAGIC  0x646c7470  /* btlp: marks a valid bootldr partition table in params sector */
+
+#define BOOTLDR_MAGIC_OFFSET 0x20 /* offset 0x20 into the bootldr */
+#define BOOTCAP_OFFSET 0X30 /* offset 0x30 into the bootldr */
+
+#define BOOTCAP_WAKEUP	(1<<0)
+#define BOOTCAP_PARTITIONS (1<<1) /* partition table stored in params sector */
+#define BOOTCAP_PARAMS_AFTER_BOOTLDR (1<<2) /* params sector right after bootldr sector(s), else in last sector */
+
+static struct BootldrFlashPartitionTable Table;
+static struct BootldrFlashPartitionTable *partition_table = NULL;
+
+
+int parse_bootldr_partitions(struct mtd_info *master, struct mtd_partition **pparts)
+{
+	struct mtd_partition *parts;
+	int ret, retlen, i;
+	int npartitions = 0;
+	long partition_table_offset;
+	long bootmagic = 0;
+	long bootcap = 0;
+	int namelen = 0;
+
+	char *names; 
+
+#if 0
+	/* verify bootldr magic */
+	ret = master->read(master, BOOTLDR_MAGIC_OFFSET, sizeof(long), &retlen, (void *)&bootmagic);
+	if (ret) 
+		goto out;
+        if (bootmagic != BOOTLDR_MAGIC)
+                goto out;
+	/* see if bootldr supports partition tables and where to find the partition table */
+	ret = master->read(master, BOOTCAP_OFFSET, sizeof(long), &retlen, (void *)&bootcap);
+	if (ret) 
+		goto out;
+
+	if (!(bootcap & BOOTCAP_PARTITIONS))
+		goto out;
+	if (bootcap & BOOTCAP_PARAMS_AFTER_BOOTLDR)
+		partition_table_offset = master->erasesize;
+	else
+		partition_table_offset = master->size - master->erasesize;
+
+	printk(__FUNCTION__ ": partition_table_offset=%#lx\n", partition_table_offset);
+	printk(__FUNCTION__ ": ptable_addr=%#lx\n", ptable_addr);
+
+
+	/* Read the partition table */
+	partition_table = (struct BootldrFlashPartitionTable *)kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!partition_table)
+		return -ENOMEM;
+
+	ret = master->read(master, partition_table_offset,
+			   PAGE_SIZE, &retlen, (void *)partition_table);
+	if (ret)
+	    goto out;
+
+#endif
+	if (!partition_table)
+	    return -ENOMEM;
+
+	
+	printk(__FUNCTION__ ": magic=%#x\n", partition_table->magic);
+	printk(__FUNCTION__ ": numPartitions=%#x\n", partition_table->npartitions);
+
+
+	/* check for partition table magic number */
+	if (partition_table->magic != BOOTLDR_PARTITION_MAGIC) 
+		goto out;
+	npartitions = (partition_table->npartitions > MAX_NUM_PARTITIONS)?
+	    MAX_NUM_PARTITIONS:partition_table->npartitions;	
+
+	printk(__FUNCTION__ ": npartitions=%#x\n", npartitions);
+
+	for (i = 0; i < npartitions; i++) {
+		namelen += strlen(partition_table->partition[i].name) + 1;
+	}
+
+	parts = kmalloc(sizeof(*parts)*npartitions + namelen, GFP_KERNEL);
+	if (!parts) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	names = (char *)&parts[npartitions];
+	memset(parts, 0, sizeof(*parts)*npartitions + namelen);
+
+
+
+	// from here we use the partition table
+	for (i = 0; i < npartitions; i++) {
+                struct FlashRegion *partition = &partition_table->partition[i];
+		const char *name = partition->name;
+		parts[i].name = names;
+		names += strlen(name) + 1;
+		strcpy(parts[i].name, name);
+
+                if (partition->flags & LFR_EXPAND)
+                        parts[i].size = MTDPART_SIZ_FULL;
+                else
+                        parts[i].size = partition->size;
+		parts[i].offset = partition->base;
+		parts[i].mask_flags = 0;
+		
+		printk("        partition %s o=%x s=%x\n", 
+		       parts[i].name, parts[i].offset, parts[i].size);
+
+	}
+
+	ret = npartitions;
+	*pparts = parts;
+
+ out:
+#if 0
+	if (partition_table)
+		kfree(partition_table);
+#endif
+	
+	return ret;
+}
+
+
+static int __init parse_tag_ptable(const struct tag *tag)
+{
+    char buf[128];
+    int i;
+    int j;
+    
+    partition_table = &Table;
+
+#ifdef CONFIG_DEBUG_LL    
+    sprintf(buf,"ptable: magic = = 0x%lx  npartitions= %d \n",
+	    tag->u.ptable.magic,tag->u.ptable.npartitions);
+    printascii(buf);
+    
+    for (i=0; i<tag->u.ptable.npartitions; i++){
+	sprintf(buf,"ptable: partition name = %s base= 0x%lx  size= 0x%lx flags= 0x%lx\n",
+	    (char *) (&tag->u.ptable.partition[i].name[0]),
+		tag->u.ptable.partition[i].base,
+		tag->u.ptable.partition[i].size,
+		tag->u.ptable.partition[i].flags);
+	printascii(buf);
+    }
+#endif
+
+    memcpy((void *)partition_table,(void *) (&(tag->u.ptable)),sizeof(partition_table) +
+	sizeof(struct FlashRegion)*tag->u.ptable.npartitions);
+
+    
+    return 0;
+}
+
+__tagtable(ATAG_PTABLE, parse_tag_ptable);
+
+EXPORT_SYMBOL(parse_bootldr_partitions);
+
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Compaq Computer Corporation");
+MODULE_DESCRIPTION("Parsing code for Compaq bootldr partitions");
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/Config.in linux-2.4.19/drivers/mtd/maps/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/Config.in	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/mtd/maps/Config.in	2003-01-15 09:48:33.000000000 +0200
@@ -82,6 +82,7 @@
    dep_tristate '  NV-RAM mapping AUTCPU12 board' CONFIG_MTD_AUTCPU12 $CONFIG_ARCH_AUTCPU12
    dep_tristate '  CFI Flash device mapped on EDB7312' CONFIG_MTD_EDB7312 $CONFIG_ARCH_EDB7212 $CONFIG_MTD_CFI
    dep_tristate '  JEDEC Flash device mapped on impA7' CONFIG_MTD_IMPA7 $CONFIG_MTD_JEDECPROBE
+   dep_tristate '  CFI Flash device mapped on TI OMAP' CONFIG_MTD_OMAP $CONFIG_MTD_CFI $CONFIG_ARCH_OMAP $CONFIG_MTD_PARTITIONS
 fi
 if [ "$CONFIG_ALPHA" = "y" ]; then
    dep_tristate '  Flash chip mapping on TSUNAMI' CONFIG_MTD_TSUNAMI $CONFIG_MTD_GENPROBE
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/Makefile linux-2.4.19/drivers/mtd/maps/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/Makefile	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/mtd/maps/Makefile	2003-01-15 09:48:04.000000000 +0200
@@ -47,5 +47,6 @@
 obj-$(CONFIG_MTD_EDB7312)       += edb7312.o
 obj-$(CONFIG_MTD_IMPA7)         += impa7.o
 obj-$(CONFIG_MTD_REDWOOD)       += redwood.o
+obj-$(CONFIG_MTD_OMAP)		+= omap-flash.o
 
 include $(TOPDIR)/Rules.make
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/omap-flash.c linux-2.4.19/drivers/mtd/maps/omap-flash.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/mtd/maps/omap-flash.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/mtd/maps/omap-flash.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,357 @@
+/*
+ * Flash memory access on OMAP based devices
+ *
+ * (C) 2002 MontaVista Software, Inc.
+ *
+ * $Id: omap-flash.c,v 1.1 2003/01/09 17:49:04 tmlind Exp $
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+
+#ifndef CONFIG_ARCH_OMAP
+#error This is for OMAP architecture only
+#endif
+
+
+static __u8 omap_read8(struct map_info *map, unsigned long ofs)
+{
+	return readb(map->map_priv_1 + ofs);
+}
+
+static __u16 omap_read16(struct map_info *map, unsigned long ofs)
+{
+	return readw(map->map_priv_1 + ofs);
+}
+
+static __u32 omap_read32(struct map_info *map, unsigned long ofs)
+{
+	return readl(map->map_priv_1 + ofs);
+}
+
+static void omap_copy_from(struct map_info *map, void *to,
+	unsigned long from, ssize_t len)
+{
+	memcpy(to, (void *)(map->map_priv_1 + from), len);
+}
+
+static void omap_write8(struct map_info *map, __u8 d, unsigned long adr)
+{
+	writeb(d, map->map_priv_1 + adr);
+}
+
+static void omap_write16(struct map_info *map, __u16 d, unsigned long adr)
+{
+	writew(d, map->map_priv_1 + adr);
+}
+
+static void omap_write32(struct map_info *map, __u32 d, unsigned long adr)
+{
+	writel(d, map->map_priv_1 + adr);
+}
+
+static void omap_copy_to(struct map_info *map, unsigned long to,
+	const void *from, ssize_t len)
+{
+	memcpy((void *)(map->map_priv_1 + to), from, len);
+}
+
+static void omap_set_vpp(struct map_info *map, int vpp)
+{
+	uint v = *((volatile uint *)(OMAP_EMIFS_CONFIG_REG));
+
+	if (vpp)
+		v |= OMAP_EMIFS_CONFIG_WP;
+	else
+		v &= ~OMAP_EMIFS_CONFIG_WP;
+
+	*((volatile uint *)(OMAP_EMIFS_CONFIG_REG)) = v;
+}
+
+
+static struct map_info omap_map_flash_0 = {
+	name:		"OMAP flash",
+	read8:		omap_read8,
+	read16:		omap_read16,
+	read32:		omap_read32,
+	copy_from:	omap_copy_from,
+	write8:		omap_write8,
+	write16:	omap_write16,
+	write32:	omap_write32,
+	copy_to:	omap_copy_to,
+	set_vpp:	omap_set_vpp,
+	buswidth:	2,
+	map_priv_1:	OMAP_FLASH_0_BASE,
+};
+
+static struct map_info omap_map_flash_1 = {
+	name:		"OMAP flash",
+	read8:		omap_read8,
+	read16:		omap_read16,
+	read32:		omap_read32,
+	copy_from:	omap_copy_from,
+	write8:		omap_write8,
+	write16:	omap_write16,
+	write32:	omap_write32,
+	copy_to:	omap_copy_to,
+	set_vpp:	omap_set_vpp,
+	buswidth:	2,
+	map_priv_1:	OMAP_FLASH_1_BASE,
+};
+
+
+/*
+ * Here are partition information for all known OMAP-based devices.
+ * See include/linux/mtd/partitions.h for definition of the mtd_partition
+ * structure.
+ *
+ * The *_max_flash_size is the maximum possible mapped flash size which
+ * is not necessarily the actual flash size.  It must be no more than
+ * the value specified in the "struct map_desc *_io_desc" mapping
+ * definition for the corresponding machine.
+ *
+ * Please keep these in alphabetical order, and formatted as per existing
+ * entries.  Thanks.
+ */
+
+#if	defined(CONFIG_OMAP_INNOVATOR)
+/* Both Flash 0 and 1 are the same size */
+static unsigned long innovator_max_flash_size = OMAP_FLASH_0_SIZE;
+static struct mtd_partition innovator_flash_0_partitions[] = {
+	{
+		name:		"BootLoader",
+		size:		0x00020000,
+		offset:		0,
+		mask_flags:	MTD_WRITEABLE,  /* force read-only */
+	}, {
+		name:		"Params",
+		size:		0x00040000,
+		offset:		MTDPART_OFS_APPEND,
+		mask_flags:	MTD_WRITEABLE,  /* force read-only */
+	}, {
+		name:		"Kernel",
+		size:		0x00200000,
+		offset:		MTDPART_OFS_APPEND,
+	}, {
+		name:		"Flash0 FileSys",
+		size:		MTDPART_SIZ_FULL,
+		offset:		MTDPART_OFS_APPEND,
+	}
+};
+
+static struct mtd_partition innovator_flash_1_partitions[] = {
+	{
+		name:		"Flash1 FileSys",
+		size:		MTDPART_SIZ_FULL,
+		offset:		MTDPART_OFS_APPEND,
+	}
+};
+#endif
+
+#if	defined(CONFIG_OMAP_PERSEUS)
+static unsigned long perseus_max_flash_size = OMAP_FLASH_CS0_SIZE;
+static struct mtd_partition perseus_partitions[] = {
+	{
+		name:		"Bootloader",
+		size:		0x00100000,
+		offset:		0,
+		mask_flags:	MTD_WRITEABLE,  /* force read-only */
+	}, {
+		name:		"zImage",
+		size:		0x000a0000,
+		offset:		MTDPART_OFS_APPEND,
+	}, {
+		name:		"Root FS",
+		size:		0x00660000,
+		offset:		MTDPART_OFS_APPEND,
+	}, {
+		name:		"User1 FS",
+		size:		0x00400000,
+		offset:		MTDPART_OFS_APPEND,
+	}, {
+		name:		"User2 FS",
+		size:		MTDPART_SIZ_FULL,
+		offset:		MTDPART_OFS_APPEND,
+	}
+};
+#endif
+
+
+
+extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
+extern int parse_bootldr_partitions(struct mtd_info *master, struct mtd_partition **pparts);
+
+static struct mtd_partition *parsed_parts;
+
+static struct mtd_info *flash0_mtd;
+static struct mtd_info *flash1_mtd;
+
+static int __init init_flash_0 (void)
+{
+
+	struct mtd_partition *parts;
+	int nb_parts = 0;
+	int parsed_nr_parts = 0;
+	const char *part_type;
+
+	/*
+	 * Static partition definition selection
+	 */
+	part_type = "static";
+
+#if	defined(CONFIG_OMAP_INNOVATOR)
+	if (machine_is_innovator()) {
+		parts = innovator_flash_0_partitions;
+		nb_parts = ARRAY_SIZE(innovator_flash_0_partitions);
+		omap_map_flash_0.size = innovator_max_flash_size;
+	}
+#endif
+#if	defined(CONFIG_OMAP_PERSEUS)
+	if (machine_is_perseus()) {
+		parts = perseus_partitions;
+		nb_parts = ARRAY_SIZE(perseus_partitions);
+		omap_map_flash_0.size = perseus_max_flash_size;
+	}
+#endif
+
+	/*
+	 * Now let's probe for the actual flash.  Do it here since
+	 * specific machine settings might have been set above.
+	 */
+	printk(KERN_NOTICE "OMAP flash 0: probing %d-bit flash bus\n",
+		omap_map_flash_0.buswidth*8);
+	flash0_mtd = do_map_probe("cfi_probe", &omap_map_flash_0);
+	if (!flash0_mtd)
+		return -ENXIO;
+	flash0_mtd->module = THIS_MODULE;
+
+	/*
+	 * Dynamic partition selection stuff (might override the static ones)
+	 */
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+	if (parsed_nr_parts == 0) {
+		int ret = parse_redboot_partitions(flash0_mtd, &parsed_parts);
+
+		if (ret > 0) {
+			part_type = "RedBoot";
+			parsed_nr_parts = ret;
+		}
+	}
+#endif
+#ifdef CONFIG_MTD_BOOTLDR_PARTS
+	if (parsed_nr_parts == 0) {
+		int ret = parse_bootldr_partitions(flash0_mtd, &parsed_parts);
+		if (ret > 0) {
+			part_type = "Compaq bootldr";
+			parsed_nr_parts = ret;
+		}
+	}
+#endif
+
+	if (parsed_nr_parts > 0) {
+		parts = parsed_parts;
+		nb_parts = parsed_nr_parts;
+	}
+
+	if (nb_parts == 0) {
+		printk(KERN_NOTICE "OMAP flash: no partition info available,"
+			"registering whole flash at once\n");
+		add_mtd_device(flash0_mtd);
+	} else {
+		printk(KERN_NOTICE "Using %s partition definition\n",
+			part_type);
+		add_mtd_partitions(flash0_mtd, parts, nb_parts);
+	}
+	return 0;
+}
+
+#if	defined(CONFIG_OMAP_INNOVATOR)
+static int __init init_flash_1 (void)
+{
+
+	struct mtd_partition *parts;
+	int nb_parts = 0;
+	const char *part_type;
+
+	/*
+	 * Static partition definition selection
+	 */
+	part_type = "static";
+
+	if (machine_is_innovator()) {
+		parts = innovator_flash_1_partitions;
+		nb_parts = ARRAY_SIZE(innovator_flash_1_partitions);
+		omap_map_flash_1.size = innovator_max_flash_size;
+	}
+
+	/*
+	 * Now let's probe for the actual flash.  Do it here since
+	 * specific machine settings might have been set above.
+	 */
+	printk(KERN_NOTICE "OMAP flash 1: probing %d-bit flash bus\n",
+		omap_map_flash_1.buswidth*8);
+	flash1_mtd = do_map_probe("cfi_probe", &omap_map_flash_1);
+	if (!flash1_mtd)
+		return -ENXIO;
+	flash1_mtd->module = THIS_MODULE;
+
+	if (nb_parts == 0) {
+		printk(KERN_NOTICE "OMAP flash 1: no partition info available,"
+			"registering whole flash at once\n");
+		add_mtd_device(flash1_mtd);
+	} else {
+		printk(KERN_NOTICE "Using %s partition definition\n",
+			part_type);
+		add_mtd_partitions(flash1_mtd, parts, nb_parts);
+	}
+	return 0;
+}
+#endif
+
+int __init omap_mtd_init(void)
+{
+	int status;
+
+	if (status = init_flash_0 ()) {
+		printk(KERN_ERR "OMAP Flash 0: unable to init map\n");
+	}
+#if	defined(CONFIG_OMAP_INNOVATOR)
+	if (status = init_flash_1 ()) {
+		printk(KERN_ERR "OMAP Flash 1: unable to init map\n");
+	}
+#endif
+	return status;
+}
+
+static void __exit omap_mtd_cleanup(void)
+{
+	if (flash0_mtd) {
+		del_mtd_partitions(flash0_mtd);
+		map_destroy(flash0_mtd);
+		if (parsed_parts)
+			kfree(parsed_parts);
+	}
+	if (flash1_mtd) {
+		del_mtd_partitions(flash1_mtd);
+		map_destroy(flash1_mtd);
+		if (parsed_parts)
+			kfree(parsed_parts);
+	}
+}
+
+module_init(omap_mtd_init);
+module_exit(omap_mtd_cleanup);
+
+MODULE_AUTHOR("George G. Davis");
+MODULE_DESCRIPTION("OMAP CFI map driver");
+MODULE_LICENSE("GPL");
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/net/Config.in linux-2.4.19/drivers/net/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/net/Config.in	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/net/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -26,7 +26,7 @@
 if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
    if [ "$CONFIG_ARM" = "y" ]; then  
       dep_bool '  ARM EBSA110 AM79C961A support' CONFIG_ARM_AM79C961A $CONFIG_ARCH_EBSA110
-      dep_tristate '  Cirrus Logic CS8900A support' CONFIG_ARM_CIRRUS
+      ###dep_tristate '  Cirrus Logic CS8900A support' CONFIG_ARM_CIRRUS
       if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
          source drivers/acorn/net/Config.in
       fi
@@ -109,7 +109,8 @@
       dep_tristate '    SMC Ultra MCA support' CONFIG_ULTRAMCA $CONFIG_MCA
       dep_tristate '    SMC Ultra support' CONFIG_ULTRA $CONFIG_ISA
       dep_tristate '    SMC Ultra32 EISA support' CONFIG_ULTRA32 $CONFIG_EISA
-      dep_tristate '    SMC 9194 support' CONFIG_SMC9194 $CONFIG_ISA
+      ##dep_tristate '    SMC 9194 support' CONFIG_SMC9194 $CONFIG_ISA
+      tristate     '    SMC 9194 support' CONFIG_SMC9194
    fi
    bool '  Racal-Interlan (Micom) NI cards' CONFIG_NET_VENDOR_RACAL
    if [ "$CONFIG_NET_VENDOR_RACAL" = "y" ]; then
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/net/smc9194.c linux-2.4.19/drivers/net/smc9194.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/net/smc9194.c	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/net/smc9194.c	2003-01-09 19:49:04.000000000 +0200
@@ -56,7 +56,6 @@
  .				 Use dev->name instead of CARDNAME for printk
  .				 Add ethtool support, full duplex support
  .				 Add LAN91C96 support.
- .      11/08/01 Matt Domsch     Use common crc32 function
  ----------------------------------------------------------------------------*/
 
 #define DRV_NAME	"smc9194"
@@ -80,7 +79,6 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/crc32.h>
 #include <linux/errno.h>
 #include <linux/ethtool.h>
 
@@ -93,12 +91,17 @@
 #include <asm/io.h>
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_ARCH_SA1100
+#if	defined(CONFIG_ARCH_SA1100) || \
+	defined(CONFIG_ARCH_PXA)
 #include <asm/hardware.h>
+#endif
+#if	defined(CONFIG_ASSABET_NEPONSET)
 #include <asm/arch/assabet.h>
 #endif
 
 #include "smc9194.h"
+
+
 /*------------------------------------------------------------------------
  .
  . Configuration options, for the experienced user to change.
@@ -109,12 +112,23 @@
  . Do you want to use 32 bit xfers?  This should work on all chips, as
  . the chipset is designed to accommodate them.
 */
-#ifdef __sh__
+#if	defined(__sh__) || \
+	defined(CONFIG_OMAP_1510P1) || \
+	defined(CONFIG_OMAP_INNOVATOR)
 #undef USE_32_BIT
 #else
 #define USE_32_BIT 1
 #endif
 
+#if	!defined(CONFIG_SA1100_GRAPHICSCLIENT) && \
+	!defined(CONFIG_SA1100_PFS168) && \
+	!defined(CONFIG_SA1100_FLEXANET) && \
+	!defined(CONFIG_SA1100_GRAPHICSMASTER) && \
+	!defined(CONFIG_ASSABET_NEPONSET) && \
+	!defined(CONFIG_ARCH_LUBBOCK) && \
+	!defined(CONFIG_ARCH_PXA_IDP) && \
+	!defined(CONFIG_OMAP_1510P1) && \
+	!defined(CONFIG_OMAP_INNOVATOR)
 /*
  .the SMC9194 can be at any of the following port addresses.  To change,
  .for a slightly different card, you can add it to the array.  Keep in
@@ -124,6 +138,7 @@
 	0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
 	0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0
 };
+#endif
 
 /*
  . Wait time for memory to be free.  This probably shouldn't be
@@ -247,6 +262,10 @@
 */
 static void smc_set_multicast_list(struct net_device *dev);
 
+/*
+ . CRC compute
+ */
+static int crc32(char * s, int length);
 
 /*---------------------------------------------------------------
  .
@@ -305,7 +324,11 @@
  . specified in the input to the device.  */
 static int smc_findirq(struct net_device *dev);
 
-#ifndef CONFIG_ASSABET_NEPONSET
+#if	defined(CONFIG_ASSABET_NEPONSET)
+
+#undef SMC_IO_EXTENT
+#define SMC_IO_EXTENT	(16 << 2)
+
 /*
  * These functions allow us to handle IO addressing as we wish - this
  * ethernet controller can be connected to a variety of busses.  Some
@@ -313,74 +336,56 @@
  */
 static inline u8 smc_inb(u_int base, u_int reg)
 {
-	return inb(base + reg);
+	u_int port = base + reg * 4;
+
+	return readb(port);
 }
 
 static inline u16 smc_inw(u_int base, u_int reg)
 {
-	return inw(base + reg);
+	u_int port = base + reg * 4;
+
+	return readb(port) | readb(port + 4) << 8;
 }
 
 static inline void smc_ins(u_int base, u_int reg, u8 *data, u_int len)
 {
-	u_int port = base + reg;
-#ifdef USE_32_BIT
-	/* QUESTION:  Like in the TX routine, do I want
-	   to send the DWORDs or the bytes first, or some
-	   mixture.  A mixture might improve already slow PIO
-	   performance  */
-	PRINTK3((" Reading %d dwords (and %d bytes) \n",
-		len >> 2, len & 3));
-	insl(port, data, len >> 2);
-	/* read the left over bytes */
-	insb(port, data + (len & ~3), len & 3);
-#else
-	PRINTK3((" Reading %d words and %d byte(s) \n",
-		len >> 1, len & 1));
-	insw(port, data, len >> 1);
-	if (len & 1) {
-		data += len & ~1;
-		*data = inb(port);
-	}
-#endif
+	u_int port = base + reg * 4;
+
+	insb(port, data, len);
 }
 
 static inline void smc_outb(u8 val, u_int base, u_int reg)
 {
-	outb(val, base + reg);
+	u_int port = base + reg * 4;
+
+	writeb(val, port);
 }
 
 static inline void smc_outw(u16 val, u_int base, u_int reg)
 {
-	outw(val, base + reg);
+	u_int port = base + reg * 4;
+
+	writeb(val, port);
+	writeb(val >> 8, port + 4);
 }
 
 static inline void smc_outl(u32 val, u_int base, u_int reg)
 {
-	u_int port = base + reg;
-#ifdef USE_32_BIT
-	outl(val, port);
-#else
-	outw(val, port);
-	outw(val >> 16, port);
-#endif
+	u_int port = base + reg * 4;
+
+	writeb(val, port);
+	writeb(val >> 8, port + 4);
+	writeb(val >> 16, port + 8);
+	writeb(val >> 24, port + 12);
 }
 
 static inline void smc_outs(u_int base, u_int reg, u8 *data, u_int len)
 {
-	u_int port = base + reg;
-#ifdef USE_32_BIT
-	if (len & 2) {
-		outsl(port, data, len >> 2);
-		outw(*((word *)(data + (len & ~3))), port);
-	}
-	else
-		outsl(port, data, len >> 2);
-#else
-	outsw(port, data, len >> 1);
-#endif
-}
+	u_int port = base + reg * 4;
 
+	outsb(port, data, len & ~1);
+}
 
 /*-------------------------------------------------------------------------
  .  I define some macros to make it easier to do somewhat common
@@ -391,15 +396,15 @@
 
 #define SMC_SELECT_BANK(x)				\
 	{						\
-		smc_outw(x, ioaddr, BANK_SELECT);	\
+		smc_outb(x, ioaddr, BANK_SELECT);	\
 	} 
 
 /* define a small delay for the reset */
 #define SMC_DELAY()					\
 	{						\
-		smc_inw(ioaddr, RCR);			\
-		smc_inw(ioaddr, RCR);			\
-		smc_inw(ioaddr, RCR);			\
+		smc_inb(ioaddr, RCR);			\
+		smc_inb(ioaddr, RCR);			\
+		smc_inb(ioaddr, RCR);			\
 	}
 
 /* this enables an interrupt in the interrupt mask register */
@@ -411,73 +416,90 @@
 		smc_outb(mask, ioaddr, INT_MASK);	\
 	}
 
-/* this sets the absolutel interrupt mask */
+/* this sets the absolute interrupt mask */
 #define SMC_SET_INT(x)					\
 	{						\
-		smc_outw((x), INT_MASK);		\
+		smc_outb((x), ioaddr, INT_MASK);	\
 	}
 
-#else
+/* Acknowledge an interrupt. */
+#define SMC_ACK_INT(x)					\
+	{						\
+		smc_outb((x), ioaddr, INTERRUPT);	\
+	}
 
-#undef SMC_IO_EXTENT
-#define SMC_IO_EXTENT	(16 << 2)
+#elif	defined(CONFIG_SA1100_GRAPHICSCLIENT) || \
+	defined(CONFIG_SA1100_PFS168) || \
+	defined(CONFIG_SA1100_FLEXANET) || \
+	defined(CONFIG_SA1100_GRAPHICSMASTER) || \
+	defined(CONFIG_ARCH_LUBBOCK) || \
+	defined(CONFIG_ARCH_PXA_IDP)
 
 /*
- * These functions allow us to handle IO addressing as we wish - this
- * ethernet controller can be connected to a variety of busses.  Some
- * busses do not support 16 bit or 32 bit transfers.  --rmk
+ * We can only do 16-bit reads and writes in the static memory space.
+ * Byte reads must read 16 bits and return the correct byte.
+ * Byte writes must do a read/modify/write.
  */
+
+/* The first two address lines aren't connected... */
+#undef SMC_IO_EXTENT
+#define SMC_IO_EXTENT	(16 << 2)
+
 static inline u8 smc_inb(u_int base, u_int reg)
 {
-	u_int port = base + reg * 4;
-
-	return readb(port);
+	u_int port = base + (reg & ~1) * 4;
+	u_int res = readw(port);
+	if (reg & 1)
+		res >>= 8;
+	return res;
 }
 
 static inline u16 smc_inw(u_int base, u_int reg)
 {
 	u_int port = base + reg * 4;
-
-	return readb(port) | readb(port + 4) << 8;
+	return readw(port);
 }
 
 static inline void smc_ins(u_int base, u_int reg, u8 *data, u_int len)
 {
 	u_int port = base + reg * 4;
 
-	insb(port, data, len);
+	insw(port, data, len>>1);
+	if (len & 1)
+		data[len-1] = readw(port);
 }
 
 static inline void smc_outb(u8 val, u_int base, u_int reg)
 {
-	u_int port = base + reg * 4;
-
-	writeb(val, port);
+	u_int port = base + (reg & ~1) * 4;
+	u_int res = readw(port);
+	if (reg & 1) {
+		res &= 0xff;
+		res |= val << 8;
+	} else {
+		res &= 0xff00;
+		res |= val;
+	}
+	writew(res, port);
 }
 
 static inline void smc_outw(u16 val, u_int base, u_int reg)
 {
 	u_int port = base + reg * 4;
-
-	writeb(val, port);
-	writeb(val >> 8, port + 4);
+	writew(val, port);
 }
 
 static inline void smc_outl(u32 val, u_int base, u_int reg)
 {
 	u_int port = base + reg * 4;
-
-	writeb(val, port);
-	writeb(val >> 8, port + 4);
-	writeb(val >> 16, port + 8);
-	writeb(val >> 24, port + 12);
+	writew(val, port);
+	writew(val >> 16, port + 8);
 }
 
 static inline void smc_outs(u_int base, u_int reg, u8 *data, u_int len)
 {
 	u_int port = base + reg * 4;
-
-	outsb(port, data, len & ~1);
+	outsw(port, data, len>>1);
 }
 
 /*-------------------------------------------------------------------------
@@ -489,33 +511,173 @@
 
 #define SMC_SELECT_BANK(x)				\
 	{						\
-		smc_outb(x, ioaddr, BANK_SELECT);	\
+		smc_outw(x, ioaddr, BANK_SELECT);	\
 	} 
 
 /* define a small delay for the reset */
 #define SMC_DELAY()					\
 	{						\
-		smc_inb(ioaddr, RCR);			\
-		smc_inb(ioaddr, RCR);			\
-		smc_inb(ioaddr, RCR);			\
+		smc_inw(ioaddr, RCR);			\
+		smc_inw(ioaddr, RCR);			\
+		smc_inw(ioaddr, RCR);			\
 	}
 
 /* this enables an interrupt in the interrupt mask register */
 #define SMC_ENABLE_INT(x)				\
 	{						\
-		byte mask;				\
-		mask = smc_inb(ioaddr, INT_MASK);	\
-		mask |= (x);				\
-		smc_outb(mask, ioaddr, INT_MASK);	\
+		word mask;				\
+		mask = smc_inw(ioaddr, INTERRUPT);	\
+		mask |= (x) << 8;			\
+		smc_outw(mask, ioaddr, INT_MASK);	\
 	}
 
-/* this sets the absolutel interrupt mask */
+/* this sets the absolute interrupt mask */
 #define SMC_SET_INT(x)					\
 	{						\
-		smc_outb((x), ioaddr, INT_MASK);	\
+		smc_outw((x) << 8, ioaddr, INTERRUPT);	\
+	}
+
+/* Acknowledge an interrupt. */
+#define SMC_ACK_INT(x)					\
+	{						\
+		smc_outb((x), ioaddr, INTERRUPT);	\
 	}
 
+#else	/* Assume default is CONFIG_ISA */
+
+/*
+ * These functions allow us to handle IO addressing as we wish - this
+ * ethernet controller can be connected to a variety of busses.  Some
+ * busses do not support 16 bit or 32 bit transfers.  --rmk
+ */
+static inline u8 smc_inb(u_int base, u_int reg)
+{
+	return inb(base + reg);
+}
+
+static inline u16 smc_inw(u_int base, u_int reg)
+{
+	return inw(base + reg);
+}
+
+static inline void smc_ins(u_int base, u_int reg, u8 *data, u_int len)
+{
+	u_int port = base + reg;
+#ifdef USE_32_BIT
+	/* QUESTION:  Like in the TX routine, do I want
+	   to send the DWORDs or the bytes first, or some
+	   mixture.  A mixture might improve already slow PIO
+	   performance  */
+	PRINTK3((" Reading %d dwords (and %d bytes) \n",
+		len >> 2, len & 3));
+	insl(port, data, len >> 2);
+	/* read the left over bytes */
+	if (len & 2)
+		*((u16 *)(data + (len & ~3))) = inw(port);
+	if (len & 1) 
+		*(data + (len & ~1)) = inb(port);
+#else
+	PRINTK3((" Reading %d words and %d byte(s) \n",
+		len >> 1, len & 1));
+	insw(port, data, len >> 1);
+	if (len & 1) {
+		data += len & ~1;
+		*data = inb(port);
+	}
+#endif
+}
+
+static inline void smc_outb(u8 val, u_int base, u_int reg)
+{
+	outb(val, base + reg);
+}
+
+static inline void smc_outw(u16 val, u_int base, u_int reg)
+{
+	outw(val, base + reg);
+}
+
+static inline void smc_outl(u32 val, u_int base, u_int reg)
+{
+	u_int port = base + reg;
+#ifdef USE_32_BIT
+	outl(val, port);
+#else
+	outw(val, port);
+	outw(val >> 16, port);
+#endif
+}
+
+static inline void smc_outs(u_int base, u_int reg, u8 *data, u_int len)
+{
+	u_int port = base + reg;
+#ifdef USE_32_BIT
+	if (len & 2) {
+		outsl(port, data, len >> 2);
+		outw(*((word *)(data + (len & ~3))), port);
+	}
+	else
+		outsl(port, data, len >> 2);
+#else
+	outsw(port, data, len >> 1);
 #endif
+}
+
+
+/*-------------------------------------------------------------------------
+ .  I define some macros to make it easier to do somewhat common
+ . or slightly complicated, repeated tasks. 
+ --------------------------------------------------------------------------*/
+
+/* select a register bank, 0 to 3  */
+
+#define SMC_SELECT_BANK(x)				\
+	{						\
+		smc_outw(x, ioaddr, BANK_SELECT);	\
+	} 
+
+/* define a small delay for the reset */
+#define SMC_DELAY()					\
+	{						\
+		smc_inw(ioaddr, RCR);			\
+		smc_inw(ioaddr, RCR);			\
+		smc_inw(ioaddr, RCR);			\
+	}
+
+/* This enables an interrupt in the interrupt mask register.
+ * Some boards (such as the OMAP Innovator) are
+ * wired in such a way that both 8-bit and 16-bit accesses to 
+ * the chip are interpreted by the chip as 16-bit accesses.  
+ * In order for these boards to work we must avoid 8-bit 
+ * writes to avoid corrupting the other half of a 16-bit register.
+ * In this case we write a zero to the interrupt acknowledge 
+ * register, which is harmless.
+ */
+#define SMC_ENABLE_INT(x)				\
+	{						\
+		u16 mask;				\
+		mask = smc_inw(ioaddr, INTERRUPT) & 0xff00; \
+		mask |= (x) << 8;			\
+		smc_outw(mask, ioaddr, INTERRUPT);	\
+	}
+
+/* this sets the absolute interrupt mask */
+#define SMC_SET_INT(x)					\
+	{						\
+		smc_outw((x) << 8, ioaddr, INTERRUPT);	\
+	}
+
+/* Acknowledge an interrupt, preserving the interrupt
+ * mask register.
+ */
+#define SMC_ACK_INT(x)					\
+	{						\
+		u16 ack;				\
+		ack = smc_inw(ioaddr, INTERRUPT) & 0xff00; \
+		ack |= (x) & 0xff;			\
+		smc_outw(ack, ioaddr, INTERRUPT);	\
+	}
+#endif	/* Assume default is CONFIG_ISA */
 
 /*
  . A rather simple routine to print out a packet for debugging purposes.
@@ -657,8 +819,8 @@
 
 	/* and tell the card to stay away from that nasty outside world */
 	SMC_SELECT_BANK(0);
-	smc_outb(RCR_CLEAR, ioaddr, RCR);
-	smc_outb(TCR_CLEAR, ioaddr, TCR);
+	smc_outw(RCR_CLEAR, ioaddr, RCR);
+	smc_outw(TCR_CLEAR, ioaddr, TCR);
 #if 0
 	/* finally, shut the chip down */
 	SMC_SELECT_BANK(1);
@@ -710,7 +872,7 @@
 			continue;
 
 		/* only use the low order bits */
-		position = ether_crc_le(6, cur_addr->dmi_addr) & 0x3f;
+		position = crc32(cur_addr->dmi_addr, 6) & 0x3f;
 
 		/* do some messy swapping to put the bit in the right spot */
 		multicast_table[invert3[position&7]] |=
@@ -720,11 +882,40 @@
 	/* now, the table can be loaded into the chipset */
 	SMC_SELECT_BANK(3);
 
-	for (i = 0; i < 8 ; i++) {
-		smc_outb(multicast_table[i], ioaddr, MULTICAST1 + i);
+	for (i = 0; i < 8 ; i += 2) {
+		smc_outw(multicast_table[i] | (multicast_table[i + 1] << 8), 
+			ioaddr, MULTICAST1 + i);
+	}
+}
+
+/*
+  Finds the CRC32 of a set of bytes.
+  Again, from Peter Cammaert's code.
+*/
+static int crc32(char * s, int length)
+{
+	/* indices */
+	int perByte;
+	int perBit;
+	/* crc polynomial for Ethernet */
+	const unsigned long poly = 0xedb88320;
+	/* crc value - preinitialized to all 1's */
+	unsigned long crc_value = 0xffffffff;
+
+	for (perByte = 0; perByte < length; perByte ++) {
+		unsigned char	c;
+
+		c = *(s++);
+		for (perBit = 0; perBit < 8; perBit++) {
+			crc_value = (crc_value>>1)^
+				(((crc_value^c)&0x01)?poly:0);
+			c >>= 1;
+		}
 	}
+	return	crc_value;
 }
 
+
 /*
  . Function: smc_wait_to_send_packet(struct sk_buff * skb, struct net_device *)
  . Purpose:
@@ -809,7 +1000,7 @@
 		status = smc_inb(ioaddr, INTERRUPT);
 		if (status & IM_ALLOC_INT) {
 			/* acknowledge the interrupt */
-			smc_outb(IM_ALLOC_INT, ioaddr, INTERRUPT);
+			SMC_ACK_INT(IM_ALLOC_INT);
 			break;
 		}
  	} while (-- time_out);
@@ -942,7 +1133,9 @@
 int __init smc_init(struct net_device *dev)
 {
 	int ret = -ENODEV;
-#if defined(CONFIG_ASSABET_NEPONSET)
+
+#if	defined(CONFIG_ASSABET_NEPONSET)
+
 	if (machine_is_assabet() && machine_has_neponset()) {
 		unsigned int *addr;
 		unsigned char ecor;
@@ -999,7 +1192,135 @@
 			iounmap(addr);
 	}
 
-#elif defined(CONFIG_ISA)
+#elif	defined(CONFIG_SA1100_GRAPHICSCLIENT) || \
+	defined(CONFIG_SA1100_GRAPHICSMASTER)
+
+	if (machine_is_graphicsclient() || machine_is_graphicsmaster()) {
+		int base_addr = ADS_ETHERNET;
+
+		// Max recovery timing
+		MSC1 &= ~0xFFFF;
+		MSC1 |= 0x8649;
+
+		ret = smc_probe(dev, base_addr);
+	}
+
+#elif	defined(CONFIG_SA1100_FLEXANET)
+
+	if (machine_is_flexanet()) {
+		volatile unsigned *attaddr;
+		int ioaddr;
+		unsigned flags;
+
+		/* Get the I/O and attribute base addresses
+		 * declared in flexanet.h */
+		ioaddr  = FHH_ETH_IOBASE;
+		attaddr = (unsigned *) FHH_ETH_MMBASE;
+
+		/* Ethernet IRQ setup (GPIO is input, falling edge) */
+		GPDR &= ~(GPIO_ETH_IRQ);
+		set_GPIO_IRQ_edge( GPIO_ETH_IRQ, GPIO_FALLING_EDGE );
+		dev->irq = IRQ_GPIO_ETH;
+
+		local_irq_save(flags);
+
+		/* first reset, then enable the device. Sequence is critical */
+		attaddr[ECOR] |= ECOR_RESET;
+		udelay(100);
+		attaddr[ECOR] &= ~ECOR_RESET;
+		attaddr[ECOR] |= ECOR_ENABLE;
+
+		local_irq_restore(flags);
+
+		/* force 16-bit mode */
+		attaddr[ECSR] &= ~ECSR_IOIS8;
+
+		ret = smc_probe(dev, ioaddr);
+	}
+
+#elif	defined(CONFIG_ARCH_LUBBOCK) || \
+	defined(CONFIG_ARCH_PXA_IDP)
+
+	if (machine_is_lubbock() || machine_is_pxa_idp()) {
+		int ioaddr = machine_is_lubbock() ?
+			LUBBOCK_ETH_BASE : IDP_ETH_BASE;
+		volatile unsigned *attaddr = (unsigned *) (ioaddr + 0x100000);
+		unsigned flags;
+
+		/* first reset, then enable the device. Sequence is critical */
+		local_irq_save(flags);
+		attaddr[ECOR] |= ECOR_RESET;
+		udelay(100);
+		attaddr[ECOR] &= ~ECOR_RESET;
+		attaddr[ECOR] |= ECOR_ENABLE;
+
+		/* force 16-bit mode */
+		attaddr[ECSR] &= ~ECSR_IOIS8;
+		mdelay(1);
+		local_irq_restore(flags);
+
+		dev->irq = LUBBOCK_ETH_IRQ;	
+		ret = smc_probe(dev, ioaddr);
+	}
+
+#elif	defined(CONFIG_SA1100_PFS168)
+
+	if (machine_is_pfs168()) {
+		volatile u_int * ioaddr;
+		u_long flags;
+
+		/* First, enable access to the SMC91C96 via some undocumented
+		 * black magic register bit flipping.
+		*/
+		ioaddr = (volatile u_int *)ioremap(0x1a020000, 8*1024);
+		if (!ioaddr)
+			return -ENOMEM;
+		((u_char *)(ioaddr))[0] = 0x41;
+		udelay(100);
+		((u_char *)(ioaddr))[8] = 0x00;
+		udelay(100);
+		iounmap(ioaddr); /* don't need this anymore... */
+
+		/*
+		 * The PFS-168 uses GPIO26 for the SMC9196 interrupts.
+		 * So set up GPIO26 for edge triggered interrupts now.
+		 */
+		/* Set GPIO 26 to input */
+		GPDR &= ~(GPIO_GPIO(26));
+		/* Set transition detect */
+		set_GPIO_IRQ_edge( GPIO_GPIO(26), GPIO_RISING_EDGE );
+
+		ioaddr = (volatile u_int *)ioremap(0x18000000, 8*1024);
+		if (!ioaddr)
+			return -ENOMEM;
+
+		dev->irq = IRQ_GPIO26;
+
+		ret = smc_probe(dev, (int)ioaddr);
+		if (ret)
+			iounmap(ioaddr);
+	}
+
+#elif	defined(CONFIG_OMAP_1510P1) || \
+	defined(CONFIG_OMAP_INNOVATOR)
+
+	int base_addr = OMAP1510P1_FPGA_ETHR_BASE;
+
+	SET_MODULE_OWNER(dev);
+
+	dev->irq = INT_ETHER;
+
+	/* Take the ethernet chip out of reset and wait for the
+	   EEPROM load to complete
+	*/
+        outb(inb(OMAP1510P1_FPGA_RST) & ~1, OMAP1510P1_FPGA_RST);
+        udelay(750);
+
+	if (smc_probe(dev, base_addr) == 0)
+		return 0;
+
+#else	/* Assume default is CONFIG_ISA */
+
 	int i;
 	int base_addr = dev->base_addr;
 
@@ -1017,7 +1338,8 @@
 			return 0;
 
 	/* couldn't find anything */
-#endif
+#endif	/* Assume default is CONFIG_ISA */
+
 	return ret;
 }
 
@@ -1111,7 +1433,16 @@
 	if ((temp & 0xFF00) != 0x3300)
 		return -ENODEV;
 
-#ifndef CONFIG_ASSABET_NEPONSET
+#if	!defined(CONFIG_SA1100_GRAPHICSCLIENT) && \
+	!defined(CONFIG_SA1100_PFS168) && \
+	!defined(CONFIG_SA1100_FLEXANET) && \
+	!defined(CONFIG_SA1100_GRAPHICSMASTER) && \
+	!defined(CONFIG_ASSABET_NEPONSET) && \
+	!defined(CONFIG_ARCH_LUBBOCK) && \
+	!defined(CONFIG_ARCH_PXA_IDP) && \
+	!defined(CONFIG_OMAP_1510P1) && \
+	!defined(CONFIG_OMAP_INNOVATOR)
+
 	/* well, we've already written once, so hopefully another time won't
  	   hurt.  This time, I need to switch the bank register to bank 1,
 	   so I can access the base address register */
@@ -1125,6 +1456,7 @@
 		   been a SMC chip after all. */
 		return -ENODEV;
 	}
+
 #endif
 
 	return 0;
@@ -1266,6 +1598,18 @@
 		dev->dev_addr[i] = address & 0xFF;
 	}
 
+	if ((dev->dev_addr[0] & 0x01) != 0) {
+		/*
+		 * Assigned address is a multicast MAC which is not good.
+		 * Some people apparently defined it backwards in the eprom.
+		 */
+		for (i = 0; i < 3; i++) {
+			unsigned char tmp = dev->dev_addr[i];
+			dev->dev_addr[i] = dev->dev_addr[5-i];
+			dev->dev_addr[5-i] = tmp;
+		}
+	}
+
 	if (!is_valid_ether_addr(dev->dev_addr))
 		printk("%s: Invalid ethernet MAC address.  Please set using "
 			"ifconfig\n", dev->name);
@@ -1638,7 +1982,7 @@
 			PRINTK2((KERN_WARNING "%s: TX ERROR handled\n",
 				dev->name));
 			smc_tx(dev);
-			smc_outb(IM_TX_INT, ioaddr, INTERRUPT);
+			SMC_ACK_INT(IM_TX_INT);
 		} else if (status & IM_TX_EMPTY_INT) {
 			/* update stats */
 			SMC_SELECT_BANK(0);
@@ -1654,7 +1998,7 @@
 			SMC_SELECT_BANK(2);
 			PRINTK2((KERN_WARNING "%s: TX_BUFFER_EMPTY handled\n",
 				dev->name));
-			smc_outb(IM_TX_EMPTY_INT, ioaddr, INTERRUPT);
+			SMC_ACK_INT(IM_TX_EMPTY_INT);
 			mask &= ~IM_TX_EMPTY_INT;
 			lp->stats.tx_packets += lp->packets_waiting;
 			lp->packets_waiting = 0;
@@ -1678,14 +2022,14 @@
 		} else if (status & IM_RX_OVRN_INT) {
 			lp->stats.rx_errors++;
 			lp->stats.rx_fifo_errors++;
-			smc_outb(IM_RX_OVRN_INT, ioaddr, INTERRUPT);
+			SMC_ACK_INT(IM_RX_OVRN_INT);
 		} else if (status & IM_EPH_INT) {
 			PRINTK(("%s: UNSUPPORTED: EPH INTERRUPT\n",
 				dev->name));
 		} else if (status & IM_ERCV_INT) {
 			PRINTK(("%s: UNSUPPORTED: ERCV INTERRUPT\n",
 				dev->name));
-			smc_outb(IM_ERCV_INT, ioaddr, INTERRUPT);
+			SMC_ACK_INT(IM_ERCV_INT);
 		}
 	} while (timeout --);
 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/aic23.h linux-2.4.19/drivers/sound/aic23.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/aic23.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/sound/aic23.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,113 @@
+/*
+ * File: aic23.h
+ *
+ * Defines for TI TLV320AIC23 CODEC
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+#ifndef aic23_h
+#define aic23_h
+
+// Codec TLV320AIC23 
+#define LEFT_LINE_VOLUME_ADDR		0x00 
+#define RIGHT_LINE_VOLUME_ADDR		0x01
+#define LEFT_CHANNEL_VOLUME_ADDR	0x02
+#define RIGHT_CHANNEL_VOLUME_ADDR	0x03
+#define ANALOG_AUDIO_CONTROL_ADDR	0x04
+#define DIGITAL_AUDIO_CONTROL_ADDR	0x05
+#define POWER_DOWN_CONTROL_ADDR		0x06
+#define DIGITAL_AUDIO_FORMAT_ADDR	0x07
+#define SAMPLE_RATE_CONTROL_ADDR	0x08
+#define DIGITAL_INTERFACE_ACT_ADDR	0x09
+#define RESET_CONTROL_ADDR		0x0F 
+
+// Left line input volume control register
+#define LRS_ENABLED			0x0100
+#define LIM_MUTED			0x0080
+#define LIV_CONTROL			0x001F
+#define LIV_DEFAULT			0x0017
+#define LIV_MAX				0x001f
+
+// Left channel headphone volume control register
+#define LZC_ON				0x0080
+#define LHV_DEFAULT			0x0067
+#define LHV_MAX				0x007f
+
+// Analog audio path control register
+#define STE_ENABLED			0x0020
+#define DAC_SELECTED			0x0010
+#define BYPASS_ON			0x0008
+#define INSEL_MIC			0x0004
+#define MICM_MUTED			0x0002
+#define MICB_20DB			0x0001
+
+// Digital audio path control register
+#define DACM_MUTE			0x0008
+#define DEEMP_32K			0x0002
+#define DEEMP_44K			0x0004
+#define DEEMP_48K			0x0006
+#define ADCHP_ON			0x0001
+
+// Power control down register 
+#define DEVICE_POWER_OFF	  	0x0080
+#define CLK_OFF				0x0040
+#define OSC_OFF				0x0020
+#define OUT_OFF				0x0010
+#define DAC_OFF				0x0008
+#define ADC_OFF				0x0004
+#define MIC_OFF				0x0002
+#define LINE_OFF			0x0001
+
+// Digital audio interface register
+#define MS_MASTER			0x0040
+#define LRSWAP_ON			0x0020
+#define LRP_ON				0x0010
+#define IWL_16				0x0000
+#define IWL_20				0x0004
+#define IWL_24				0x0008
+#define IWL_32				0x000C
+#define FOR_I2S				0x0002
+#define FOR_DSP				0x0003
+
+// Sample rate control register
+#define CLKOUT_HALF			0x0080
+#define CLKIN_HALF			0x0040
+#define BOSR_384fs			0x0002 //BOSR_272fs when in USB mode
+#define USB_CLK_ON			0x0001
+#define SR_MASK                         0xf
+#define SR_SHIFT                        2
+#define BOSR_SHIFT                      1
+
+	// Digital interface register
+#define ACT_ON				0x0001
+      
+//#define DEV_AIC23_ID                    (0x1A)    // 0x1b cs high  0x1A cs low
+#define DEV_AIC23_ID                    (0x1A >> 1)    // 0x1b cs high  0x1A cs low
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/Config.in linux-2.4.19/drivers/sound/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/Config.in	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/sound/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -130,6 +130,19 @@
    dep_tristate '    Generic DAC on the SA11x0 SSP port' CONFIG_SOUND_SA1100SSP $CONFIG_SOUND_SA1100
 fi
 
+if [ "$CONFIG_ARCH_OMAP1510" = "y" ]; then
+   dep_tristate '  OMAP Sound Drivers' CONFIG_SOUND_OMAP $CONFIG_ARCH_OMAP1510 $CONFIG_SOUND
+   dep_mbool    '    Allow DSP to control Audio McBSP' CONFIG_DSP_MCBSP1 $CONFIG_SOUND_OMAP
+   dep_tristate '    UDA1341 Stereo Codec' CONFIG_SOUND_OMAP_UDA1341 $CONFIG_L3 $CONFIG_SOUND_OMAP $CONFIG_SOUND
+   if [ "$CONFIG_SOUND_OMAP_UDA1341" = "y" ]; then
+      define_bool CONFIG_SOUND_UDA1341 y
+   fi
+   if [ "$CONFIG_SOUND_OMAP_UDA1341" = "m" ]; then
+      define_bool CONFIG_SOUND_UDA1341 m
+   fi
+   dep_tristate '    AIC23 Stereo Codec' CONFIG_SOUND_OMAP_AIC23 $CONFIG_I2C $CONFIG_SOUND_OMAP $CONFIG_SOUND
+fi
+
 dep_tristate '  OSS sound modules' CONFIG_SOUND_OSS $CONFIG_SOUND
 
 if [ "$CONFIG_SOUND_OSS" = "y" -o "$CONFIG_SOUND_OSS" = "m" ]; then
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/Makefile linux-2.4.19/drivers/sound/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/Makefile	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/sound/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -12,6 +12,7 @@
 		    sound_core.o sound_syms.o uart401.o	\
 		    nm256_audio.o ac97.o ac97_codec.o aci.o \
 		    sa1100-audio.o
+export-objs	+=  omap-audio.o
 
 # Each configuration option enables a list of files.
 
@@ -72,12 +73,15 @@
 obj-$(CONFIG_SOUND_MAESTRO)	+= maestro.o
 obj-$(CONFIG_SOUND_MAESTRO3)	+= maestro3.o ac97_codec.o
 obj-$(CONFIG_SOUND_TRIDENT)	+= trident.o ac97_codec.o
+obj-$(CONFIG_SOUND_OMAP)	+= omap-audio.o
 obj-$(CONFIG_SOUND_SA1100)	+= sa1100-audio.o
 obj-$(CONFIG_SOUND_UDA1341)	+= uda1341.o
 obj-$(CONFIG_SOUND_ASSABET_UDA1341) += assabet-uda1341.o
 obj-$(CONFIG_SOUND_PANGOLIN_UDA1341) += pangolin-uda1341.o
 obj-$(CONFIG_SOUND_H3600_UDA1341) += h3600-uda1341.o
 obj-$(CONFIG_SOUND_SA1111_UDA1341) += sa1111-uda1341.o
+obj-$(CONFIG_SOUND_OMAP_UDA1341)	+= omap1510-uda1341.o 
+obj-$(CONFIG_SOUND_OMAP_AIC23)	+= omap1510-aic23.o 
 obj-$(CONFIG_SOUND_SA1100SSP)	+= sa1100ssp.o
 obj-$(CONFIG_SOUND_EMU10K1)	+= ac97_codec.o
 obj-$(CONFIG_SOUND_BCM_CS4297A)	+= swarm_cs4297a.o
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap1510-aic23.c linux-2.4.19/drivers/sound/omap1510-aic23.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap1510-aic23.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/sound/omap1510-aic23.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,883 @@
+/*
+ * Glue audio driver for the TI OMAP1510 & TI AIC23 CODEC
+ *
+ * Copyright (c) 2000 Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 2001, Steve Johnson <stevej@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ *
+ * This is the machine specific part of the TI OMAP1510 support.
+ * This driver makes use of the UDA1341 and the omap1510-audio modules.
+ *
+ * History:
+ *
+ * 2000-05-21	Nicolas Pitre	Initial UDA1341 driver release.
+ *
+ * 2000-07-??	George France	Bitsy support.
+ *
+ * 2000-12-13	Deborah Wallach	Fixed power handling for iPAQ/h3600
+ *
+ * 2001-06-03	Nicolas Pitre	Made this file a separate module, based on
+ * 				the former sa1100-uda1341.c driver.
+ *
+ * 2001-07-13	Nicolas Pitre	Fixes for all supported samplerates.
+ *
+ * 2002-05-23   Steve Johnson   Modified for OMAP1510.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/errno.h>
+#include <linux/sound.h>
+#include <linux/soundcard.h>
+#include <linux/i2c.h>
+
+#include <asm/semaphore.h>
+#include <asm/uaccess.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/arch/fpga.h>
+#include <asm/arch/ck.h>
+
+#include "omap-audio.h"
+#include <asm/arch/mcbsp.h>
+#include "aic23.h"
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define DPRINTK( x... )  printk( ##x )
+#else
+#define DPRINTK( x... )
+#endif
+
+#define AUDIO_NAME		"OMAP1510_AIC23"
+
+#define AUDIO_RATE_DEFAULT	44100
+
+/* Define the macro MCBSP_I2S_MASTER to make the McBSP the I2S
+ * master and the CODEC the I2S slave.  If this macro is not defined 
+ * then the CODEC is the I2S master and the McBSP is the I2S slave.
+ */
+#define MCBSP_I2S_MASTER
+
+/*
+  Local prototypes.
+*/
+static void omap1510_audio_init(void *dummy);
+static void omap1510_audio_shutdown(void *dummy);
+static int omap1510_audio_ioctl(struct inode *inode, struct file *file,
+                                uint cmd, ulong arg);
+
+/* Addresses to scan */
+// static unsigned short normal_i2c[] = { DEV_AIC23_ID };
+static unsigned short normal_i2c[] = { I2C_CLIENT_END };
+// static unsigned short normal_i2c_range[] = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short normal_i2c_range[] = { 0x1a, 0x1b, I2C_CLIENT_END };
+static unsigned short probe[2]        = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short probe_range[2]  = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short ignore[2]       = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short ignore_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short force[2]        = { I2C_CLIENT_END, I2C_CLIENT_END };
+static struct i2c_client_address_data addr_data = {
+	normal_i2c, normal_i2c_range, 
+	probe, probe_range, 
+	ignore, ignore_range, 
+	force
+};
+
+static int this_adap;
+static struct i2c_driver driver;
+static struct i2c_client aic23 = {
+        "(unset)",		
+        -1,
+        0,
+        0,
+        NULL,
+        &driver    
+};
+
+static int input_or_output;
+
+static audio_stream_t output_stream;
+static audio_stream_t input_stream;
+
+static audio_state_t audio_state = {
+	output_stream:	&output_stream,
+	output_dma:	eAudioTx,
+	output_id:	"AIC23 out",
+	input_stream:	&input_stream,
+	input_dma:	eAudioRx,
+	input_id:	"AIC23 in",
+//	need_tx_for_rx:	1,  TODO Try this once receive is working.
+	need_tx_for_rx:	0,
+	hw_init:	omap1510_audio_init,
+	hw_shutdown:	omap1510_audio_shutdown,
+	client_ioctl:	omap1510_audio_ioctl,
+	sem:		__MUTEX_INITIALIZER(audio_state.sem),
+};
+
+#define REC_MASK (SOUND_MASK_LINE | SOUND_MASK_MIC)
+#define DEV_MASK (REC_MASK | SOUND_MASK_VOLUME)
+
+#define SET_VOLUME 1
+#define SET_LINE   2
+
+#define DEFAULT_VOLUME          93
+#define DEFAULT_INPUT_VOLUME     0	/* 0 ==> mute line in */
+					/* use input vol of 75 for 0dB gain */
+
+#define OUTPUT_VOLUME_MIN 0x30
+#define OUTPUT_VOLUME_MAX LHV_MAX
+#define OUTPUT_VOLUME_RANGE (OUTPUT_VOLUME_MAX - OUTPUT_VOLUME_MIN)
+#define OUTPUT_VOLUME_MASK OUTPUT_VOLUME_MAX
+
+#define INPUT_VOLUME_MIN 0x0
+#define INPUT_VOLUME_MAX LIV_MAX
+#define INPUT_VOLUME_RANGE (INPUT_VOLUME_MAX - INPUT_VOLUME_MIN)
+#define INPUT_VOLUME_MASK INPUT_VOLUME_MAX
+
+struct {
+        u8 volume;
+        u16 volume_reg;
+        u8 line;
+        u8 mic;
+        u16 input_volume_reg;
+        int mod_cnt;
+} aic23_local;
+
+/*
+  Simplified write routine.  I know the i2c message
+  is just two bytes and won't be more.
+*/
+static void omap1510_write_i2c(u8 address, u16 data) 
+{
+        u8 buf[2];
+        int ret = 0;
+        int retries = 5;
+
+	DPRINTK(__FUNCTION__ ": addr 0x%02x, data 0x%04x\n", address, data);
+        buf[0] = ((address << 1) | ((data & 0x100) >> 8));
+        buf[1] = (data & 0xff);
+        while ((ret != sizeof(buf)) && (retries--)) {
+                if (sizeof(buf) != (ret = i2c_master_send(&aic23, (const char *)buf, sizeof(buf)))) {
+                        DPRINTK(__FUNCTION__ ": expected %d, received %d, address 0x%x\n", sizeof(buf), ret, address);
+                        DPRINTK("retries - %d\n", retries);
+                }
+        }
+
+}
+
+static void aic23_update(int flag, int val)
+{
+        u8 volume;
+
+        switch (flag) {
+        case SET_VOLUME:
+                aic23_local.volume_reg &= ~OUTPUT_VOLUME_MASK;
+                // Convert 0 -> 100 volume to 0x30 -> 0x7f volume range
+                volume = ((val * OUTPUT_VOLUME_RANGE) / 100) + OUTPUT_VOLUME_MIN;
+                aic23_local.volume_reg |= volume;
+                omap1510_write_i2c(LEFT_CHANNEL_VOLUME_ADDR, aic23_local.volume_reg);
+                omap1510_write_i2c(RIGHT_CHANNEL_VOLUME_ADDR, aic23_local.volume_reg);
+                break;
+
+        case SET_LINE:
+                // [4:0] 12dB to -34.5dB in 1.5 steps 10111=0
+                aic23_local.input_volume_reg &= ~INPUT_VOLUME_MASK;
+                // Convert 0 -> 100 volume to 0x0 -> 0x1f volume range
+                volume = ((val * INPUT_VOLUME_RANGE) / 100) + INPUT_VOLUME_MIN;
+                aic23_local.input_volume_reg |= volume;
+                omap1510_write_i2c(LEFT_LINE_VOLUME_ADDR, aic23_local.input_volume_reg);
+                omap1510_write_i2c(RIGHT_LINE_VOLUME_ADDR, aic23_local.input_volume_reg);
+                break;
+        }
+
+}
+
+static int mixer_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg)
+{
+        int val;
+        int gain;
+        int ret = 0;
+        int nr = _IOC_NR(cmd);
+
+	/*
+	 * We only accept mixer (type 'M') ioctls.
+	 */
+	if (_IOC_TYPE(cmd) != 'M')
+		return -EINVAL;
+
+	DPRINTK(__FUNCTION__ " 0x%08x\n", cmd);
+
+	if (cmd == SOUND_MIXER_INFO) {
+		struct mixer_info mi;
+                
+		strncpy(mi.id, "AIC23", sizeof(mi.id));
+		strncpy(mi.name, "TI AIC23", sizeof(mi.name));
+		mi.modify_counter = aic23_local.mod_cnt;
+		return copy_to_user((void *)arg, &mi, sizeof(mi));
+	}
+
+	if (_IOC_DIR(cmd) & _IOC_WRITE) {
+		ret = get_user(val, (int *)arg);
+		if (ret)
+			goto out;
+
+                // Ignore separate left/right channel for now,
+                // even the codec does support it.
+		gain = val & 255;
+
+		switch (nr) {
+		case SOUND_MIXER_VOLUME:
+			aic23_local.volume = val;
+			aic23_local.mod_cnt++;
+			aic23_update(SET_VOLUME, gain);
+			break;
+
+		case SOUND_MIXER_LINE:
+			aic23_local.line = val;
+			aic23_local.mod_cnt++;
+			aic23_update(SET_LINE, gain);
+			break;
+
+		case SOUND_MIXER_MIC:
+			aic23_local.mic = val;
+			aic23_local.mod_cnt++;
+			aic23_update(SET_LINE, gain);
+			break;
+
+		case SOUND_MIXER_RECSRC:
+			break;
+
+		default:
+			ret = -EINVAL;
+		}
+	}
+
+	if (ret == 0 && _IOC_DIR(cmd) & _IOC_READ) {
+		ret = 0;
+
+		switch (nr) {
+		case SOUND_MIXER_VOLUME:     val = aic23_local.volume;	break;
+		case SOUND_MIXER_LINE:       val = aic23_local.line;	break;
+		case SOUND_MIXER_MIC:        val = aic23_local.mic;	break;
+		case SOUND_MIXER_RECSRC:     val = REC_MASK;	break;
+		case SOUND_MIXER_RECMASK:    val = REC_MASK;	break;
+		case SOUND_MIXER_DEVMASK:    val = DEV_MASK;	break;
+		case SOUND_MIXER_CAPS:       val = 0;		break;
+		case SOUND_MIXER_STEREODEVS: val = 0;		break;
+		default:	val = 0;     ret = -EINVAL;	break;
+		}
+
+		if (ret == 0)
+			ret = put_user(val, (int *)arg);
+	}
+ out:
+	return ret;
+
+}
+
+static struct file_operations omap1510_mixer_fops = {
+	ioctl:		mixer_ioctl,
+	owner:		THIS_MODULE
+};
+
+
+/*
+ * Audio interface
+ */
+
+static long audio_samplerate = AUDIO_RATE_DEFAULT;
+
+static void omap1510_set_samplerate(long val)
+{
+        int clock_divider = 0;
+        int sampling_rate = 0;
+        int bosr = 0;
+        u16 tmp;
+
+	/* We don't want to mess with clocks when frames are in flight */
+        // TODO - could call omap1510_dma_flush_all, or could poll on
+        // enable bit to wait for DMA writes to stop.
+
+	/* wait for any frame to complete */
+	udelay(125);
+
+	DPRINTK(__FUNCTION__ " %d\n", val);
+
+/* #define CODEC_CLOCK 12000000 */
+#define CODEC_CLOCK 16934400
+#if (CODEC_CLOCK == 12000000)
+
+#ifdef CONFIG_OMAP_INNOVATOR
+	/* set the CODEC clock input source to 12.000MHz */
+	fpga_write(fpga_read(OMAP1510P1_FPGA_POWER) & ~0x01, 
+			OMAP1510P1_FPGA_POWER);
+#endif
+
+        /*
+         * We have the following clock sources:
+         * 12.000 MHz
+         *
+         *  Available sampling rates:
+         *  96kHz, 88.2KHz, 48kHz, 44.1kHz, 32kHz, 8kHz,
+         *  and half of those 24kHz, 16kHz, (4kHz)
+         *  Won't bother supporting those in ().
+         */
+        if (val >= 96000)
+                val = 96000;
+        else if (val >= 88200)
+                val = 88200;
+        else if (val >= 48000)
+                val = 48000;
+        else if (val >= 44100)
+                val = 44100;
+        else if (val >= 32000)
+                val = 32000;
+        else if (val >= 24000)
+                val = 24000;
+        else if (val >= 16000)
+                val = 16000;
+        else 
+                val = 8000;
+
+        /* Set the clock divider */
+        switch (val) {
+        case 24000:
+        case 16000:
+                clock_divider = CLKIN_HALF;
+                break;
+        default:
+                break;
+        }
+
+        /* Set the sampling rate bits */
+        bosr=0;
+        switch (val) {
+        case 96000:
+                sampling_rate = 0x07;
+                break;
+        case 88200:
+                bosr = 1;
+                sampling_rate = 0x0f;
+                break;
+        case 48000:
+        case 24000:
+                sampling_rate = 0;
+                break;
+        case 44100:
+                bosr = 1;
+                sampling_rate = 0x08;
+                break;
+        case 32000:
+        case 16000:
+                sampling_rate = 6;
+                break;
+        case 8000:
+                sampling_rate = 3;
+                break;
+        }
+
+        // Set sample rate at CODEC
+        tmp = (clock_divider | (sampling_rate << SR_SHIFT) | (bosr << BOSR_SHIFT) | USB_CLK_ON);
+        omap1510_write_i2c(SAMPLE_RATE_CONTROL_ADDR, tmp);
+#else	/* if (CODEC_CLOCK == 12000000) */
+
+#ifdef CONFIG_OMAP_INNOVATOR
+	/* set the CODEC clock input source to 16.9344MHz */
+	fpga_write(fpga_read(OMAP1510P1_FPGA_POWER) | 0x01, 
+			OMAP1510P1_FPGA_POWER);
+#endif
+        /*
+         * We have the following clock sources:
+         * 16.9344 MHz
+         *
+         *  Available sampling rates:
+         *  88.2KHz, 44.1kHz, 22.05kHz
+         */
+	if (val >= 88200)
+                val = 88200;
+        else if (val >= 44100)
+                val = 44100;
+	else
+		val = 22050;
+
+        /* Set the sampling rate bits */
+        bosr=1;
+        switch (val) {
+        case 88200:
+                sampling_rate = 0x0f;
+                break;
+        case 44100:
+                sampling_rate = 0x08;
+                break;
+        case 22050:
+                clock_divider = CLKIN_HALF;
+                sampling_rate = 0x08;
+                break;
+        }
+
+        // Set sample rate at CODEC
+        tmp = (clock_divider | (sampling_rate << SR_SHIFT) | (bosr << BOSR_SHIFT));
+        omap1510_write_i2c(SAMPLE_RATE_CONTROL_ADDR, tmp);
+#endif	/* if (CODEC_CLOCK == 12000000) */
+
+#ifdef MCBSP_I2S_MASTER
+        /* 
+           Set Sample Rate at McBSP
+
+           Formula : 
+           Codec System Clock = CODEC_CLOCK, or half if clock_divider = 1;
+           clkgdv = ((Codec System Clock / (SampleRate * BitsPerSample * 2)) - 1);
+
+           FWID = BitsPerSample - 1;
+           FPER = (BitsPerSample * 2) - 1;
+        */  
+        {
+                int clkgdv;
+
+                if (clock_divider == CLKIN_HALF) {
+                        clkgdv = ((CODEC_CLOCK / 2) / (val * 16 * 2)) - 1;
+                } 
+                else {
+                        clkgdv = (CODEC_CLOCK / (val * 16 * 2)) - 1;
+                }
+
+                outw((FWID(15) | CLKGDV(clkgdv)), AUDIO_SRGR1);   
+//              outw((FWID(15) | CLKGDV(7)), AUDIO_SRGR1);      // 48K
+//              outw((FWID(15) | CLKGDV(0x2f)), AUDIO_SRGR1);   // 8K
+                outw((FSGM | FPER(31)), AUDIO_SRGR2);
+        }
+#endif
+
+	audio_samplerate = val;
+}
+
+static void omap1510_audio_init(void *dummy)
+{
+        dma_regs_t *dma_regs;
+        u16 tmp;
+
+        if (input_or_output == FMODE_WRITE) {
+                dma_regs = output_stream.dma_regs;
+        }
+        else if (input_or_output == FMODE_READ) {
+                dma_regs = input_stream.dma_regs;
+        }
+        else {
+                return;
+        }
+
+        // Reset codec
+        omap1510_write_i2c(RESET_CONTROL_ADDR, 0);
+
+        /*
+          Now here's an ugly hack.  To use McBSP1, you need to enable
+          a clock on the DSP.  So enable the MPUI, set the clock,
+          and start the DSP.  
+
+          An even uglier, evil hack.  If this is going to take the DSP
+          out of reset, shove an idle loop at the reset vector
+          and make it loop instead of crash.  You will still see
+          a DSP watchdog timer go off.
+
+          I would prefer having a DSP program (probably the MP3 decoder) set
+          up the DSP, but this allows an ARM-only MP3 decoder to work.  With
+          this code, the DSP is never put into idle, so the OMAP chip cannot 
+          go into any decent low-power mode.  Also, all of the DSP interface
+          dependencies (such as MPUI_STROBE settings) would be taken care
+          of.  Plus, we wouldn't have to worry about different boot vector
+          addresses depending on the chip version.
+        */
+
+        {
+                u32 boot_vector;
+                u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
+
+                tmp = inw(0xfffece10);	/* read ARM_RSTCT1 register */
+                if (0 == (tmp & 0x6)) {      // check if DSP is up
+			DPRINTK(__FUNCTION__ ": Bringing DSP out of reset.\n");
+                        if (0 == (tmp & 0x4)) {   // MPUI in reset
+                                tmp |= 0x4;
+                                outw(tmp, 0xfffece10);
+                                ck_enable(api_ck);
+                        }
+                        tmp = inw(0xe1008008);	/* read DSP_IDLECT2 register */
+                        if (0 == (tmp & 0x2)) {  // DSP CLKM enable
+                                tmp |= 0x2;
+                                outw(tmp, 0xe1008008);
+                        }
+                        tmp = inw(0xe1008014);	/* read DSP_RSTCT2 register */
+                        if (0 == (tmp & 0x1)) {  // DSP PER_EN bit
+                                tmp |= 0x1;
+                                outw(tmp, 0xe1008014);
+                        }
+                        tmp = inw(0xfffece00);	/* read ARM_CKCTL register */
+                        tmp |= 0x2000;
+                        outw(tmp, 0xfffece00);
+                        // Write C55 code at reset vector.
+                        if (cpu_type() == OMAP1509) {
+                                boot_vector = 0x4c000;
+                        }
+                        else {
+                                boot_vector = 0x10000;
+                        }
+                        memcpy((void *)(OMAP1510_DSP_BASE + boot_vector), 
+                               &c55_start, 
+                               sizeof(c55_start));
+                        outw(0x5, 0xfffec918);   // Set DSP boot mode
+                        tmp = inw(0xfffece10);   // take DSP out of reset
+                        tmp |= 0x6;
+                        outw(tmp, 0xfffece10);
+                }     
+                else {        // DSP's up, just check the clock/per bits
+                        tmp = inw(0xe1008008);
+                        if (0 == (tmp & 0x2)) {  // DSP CLKM enable
+                                tmp |= 0x2;
+                                outw(tmp, 0xe1008008);
+                        }
+                        tmp = inw(0xe1008014);
+                        if (0 == (tmp & 0x1)) {  // DSP PER_EN bit
+                                tmp |= 0x1;
+                                outw(tmp, 0xe1008014);
+                        }
+                }
+        }          
+
+
+        /*  
+            Configure the DMA channel and MCBSP.
+        */
+
+        if (input_or_output == FMODE_WRITE) {
+                // Setup DMA channel to McBSP1 audio Tx.
+                dma_regs->csdp = 0x0a01;
+                dma_regs->ccr = 0x1000 | audio_state.output_dma;            // source auto increment, don't enable yet
+                dma_regs->cicr = 0x23;
+                dma_regs->cdsa_l = ((OMAP1510_MCBSP1_BASE + 0x806) & 0xffff);     //McBSP1 DXR1
+                dma_regs->cdsa_u = ((OMAP1510_MCBSP1_BASE + 0x806) >> 16);
+                dma_regs->cfn = 0x1;
+                omap_dma_setup(audio_state.output_dma, eDmaOut);
+        }
+        else {
+                // Setup DMA channel to McBSP1 audio Rx.
+                dma_regs->csdp = 0x0015;                                   
+                dma_regs->ccr = 0x4000 | audio_state.input_dma;            // destn auto increment, don't enable yet
+                dma_regs->cicr = 0x23;
+                dma_regs->cssa_l = ((OMAP1510_MCBSP1_BASE + 0x802) & 0xffff);     //McBSP1 DRR1
+                dma_regs->cssa_u = ((OMAP1510_MCBSP1_BASE + 0x802) >> 16);
+                dma_regs->cfn = 0x1;
+                omap_dma_setup(audio_state.input_dma, eDmaIn);
+        }
+        // Initialize McBSP channel
+        // See TI application report, 
+        //  SPRA595, "TMS320C6000 McBSP: I2S Interface" 
+        //  for info on why these registers have these values.
+        // Default to 16 bits/sample stereo.
+        outw(0x0000, AUDIO_SPCR1);  // disable
+        outw(0x0000, AUDIO_SPCR2);  // disable
+#ifdef MCBSP_I2S_MASTER
+	/* configure MCBSP to be the I2S master */
+        outw((FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP), AUDIO_PCR0);
+
+         // 16 bits per Receive/Transmit word, 2 word per frame, 16-bit stereo.
+        outw((XFRLEN1(0) | XWDLEN1(2)), AUDIO_XCR1);
+        outw((XPHASE | XFRLEN2(0) | XWDLEN2(2) | XDATDLY(1) | XFIG), AUDIO_XCR2);
+        outw(RFRLEN1(0) | RWDLEN1(2), AUDIO_RCR1);   
+        outw((RPHASE | RFRLEN2(0) | RWDLEN2(2) | RDATDLY(1) | RFIG), AUDIO_RCR2);
+        outw((RINTM(3) | RRST), AUDIO_SPCR1);                // enable input
+        outw((FRST | GRST | XRST | XINTM(3)), AUDIO_SPCR2);  // enable output
+#else	/* ifdef MCBSP_I2S_MASTER */
+	/* configure MCBSP to be the I2S slave */
+        outw(CLKXP | CLKRP, AUDIO_PCR0);
+
+         // 16 bits per Receive/Transmit word, 2 word per frame, 16-bit stereo.
+        outw((XFRLEN1(0) | XWDLEN1(2)), AUDIO_XCR1);
+        outw((XPHASE | XFRLEN2(0) | XWDLEN2(2) | XDATDLY(1) | XFIG), AUDIO_XCR2);
+        outw(RFRLEN1(0) | RWDLEN1(2), AUDIO_RCR1);   
+        outw((RPHASE | RFRLEN2(0) | RWDLEN2(2) | RDATDLY(1) | RFIG), AUDIO_RCR2);
+        outw((RINTM(3) | RRST), AUDIO_SPCR1);	// enable input
+        outw((XINTM(3) | XRST), AUDIO_SPCR2);	// enable output
+#endif	/* ifdef MCBSP_I2S_MASTER */
+
+	DPRINTK(__FUNCTION__ ", line %d: McBSP enabled\n", __LINE__);
+	DPRINTK("McBSP1:  DRR2 =0x%04x, DRR1 =0x%04x, DXR2 =0x%04x, DXR1 =0x%04x\n",
+		inw(AUDIO_DRR2), inw(AUDIO_DRR1), inw(AUDIO_DXR2), inw(AUDIO_DXR1));
+	DPRINTK("McBSP1:  SPCR2=0x%04x, SPCR1=0x%04x, RCR2 =0x%04x, RCR1 = 0x%04x\n",
+		inw(AUDIO_SPCR2), inw(AUDIO_SPCR1), inw(AUDIO_RCR2), inw(AUDIO_RCR1));
+	DPRINTK("McBSP1:  XCR2 =0x%04x, XCR1 =0x%04x, SRGR2=0x%04x, SRGR1=0x%04x\n",
+		inw(AUDIO_XCR2), inw(AUDIO_XCR1), inw(AUDIO_SRGR2), inw(AUDIO_SRGR1));
+	DPRINTK("McBSP1:  MCR2 =0x%04x, MCR1 =0x%04x, RCERA=0x%04x, RCERB=0x%04x\n",
+		inw(AUDIO_MCR2), inw(AUDIO_MCR1), inw(AUDIO_RCERA), inw(AUDIO_RCERB));
+	DPRINTK("McBSP1:  XCERA=0x%04x, XCERB=0x%04x, PCR0 =0x%04x\n",
+		inw(AUDIO_XCERA), inw(AUDIO_XCERB), inw(AUDIO_PCR0));
+
+	/* Initialize the AIC23 internal state */
+        /*  
+            The AIC23 uses 9 bits for register control.  The
+            extra bit gets placed in the LSB of the subregister
+            address, and the address is shifted by one.
+        */
+            
+	// the volume control is only for earphone not line out
+	// line input volume can be controlled but not in following code
+	// which pick the default value 0dB
+
+	// Left line input volume control
+	tmp = 0;	/* set LRS_ENABLED to simultaneously adjust left/right */
+//        tmp |= LIV_DEFAULT;	// [4:0] 12dB to -34.5dB in 1.5 steps 10111=0
+//        tmp |= LIV_MAX;	        // [4:0] 12dB to -34.5dB in 1.5 steps 10111=0
+//        tmp |= LIM_MUTED;
+        aic23_local.line = DEFAULT_INPUT_VOLUME;
+        aic23_local.mic = DEFAULT_INPUT_VOLUME;
+        aic23_local.input_volume_reg = tmp;
+        aic23_update(SET_LINE, DEFAULT_INPUT_VOLUME);
+//        omap1510_write_i2c(LEFT_LINE_VOLUME_ADDR, tmp);
+//        omap1510_write_i2c(RIGHT_LINE_VOLUME_ADDR, tmp);
+
+	// Left/Right headphone channel volume control
+	// Zero-cross detect on
+	tmp = LZC_ON;	/* set LRS_ENABLED to simultaneously adjust left/right */ 
+//	tmp |= LHV_DEFAULT;	// Volume dB, base volume
+//	tmp |= LHV_MAX; 	// Volume dB, base volume
+        aic23_local.volume = DEFAULT_VOLUME;
+        aic23_local.volume_reg = tmp;
+        aic23_update(SET_VOLUME, DEFAULT_VOLUME);
+//        omap1510_write_i2c(LEFT_CHANNEL_VOLUME_ADDR, tmp);
+//        omap1510_write_i2c(RIGHT_CHANNEL_VOLUME_ADDR, tmp);
+
+	// Analog audio path control
+	// DAC selected
+	tmp = DAC_SELECTED; 
+//	tmp |= STE_ENABLED;
+	tmp |= INSEL_MIC; // comment out for line input
+//	tmp |= MICB_20DB;
+//	tmp |= MICM_MUTED; 
+        omap1510_write_i2c(ANALOG_AUDIO_CONTROL_ADDR, tmp);
+
+	// Digital audio path control
+	// De-emphasis control 44.1kHz
+	tmp = DEEMP_44K;
+        omap1510_write_i2c(DIGITAL_AUDIO_CONTROL_ADDR, tmp);
+
+	// Power control, everything is on. TI code sets to 0x100, which is invalid in AIC23 spec?
+	tmp = 0x0;
+        omap1510_write_i2c(POWER_DOWN_CONTROL_ADDR, tmp);
+
+	// Digital audio interface, master/slave mode, I2S, 16 bit
+	tmp = FOR_I2S;
+#ifndef MCBSP_I2S_MASTER
+	tmp |= MS_MASTER;
+#endif
+        omap1510_write_i2c(DIGITAL_AUDIO_FORMAT_ADDR, tmp);
+
+	// Digital interface
+	tmp = ACT_ON;
+        omap1510_write_i2c(DIGITAL_INTERFACE_ACT_ADDR, tmp);
+
+        /* clock configuration */
+        omap1510_set_samplerate(audio_samplerate);
+
+}
+
+static void omap1510_audio_shutdown(void *dummy)
+{
+        /* 
+           Turn off codec after it is done.  
+           Can't do it immediately, since it may still have
+           buffered data.
+
+           Wait 20ms (arbitrary value) and then turn it off.
+        */
+        
+        set_current_state(TASK_INTERRUPTIBLE);
+        schedule_timeout(2);
+
+        // Disable the McBSP channel
+        outw(0x0000, AUDIO_DXR1);  // flush data
+        outw(0x0000, AUDIO_DXR1);  // flush data
+        outw(0x0000, AUDIO_SPCR1);  // disable SPCR1
+        outw(0x0000, AUDIO_SPCR2);  // disable SPCR2     
+
+        omap1510_write_i2c(RESET_CONTROL_ADDR, 0);
+        omap1510_write_i2c(POWER_DOWN_CONTROL_ADDR, 0xff);
+        
+}
+
+static int omap1510_audio_ioctl(struct inode *inode, struct file *file,
+                                uint cmd, ulong arg)
+{
+	long val;
+	int ret = 0;
+
+	DPRINTK(__FUNCTION__ " 0x%08x\n", cmd);
+
+	/*
+	 * These are platform dependent ioctls which are not handled by the
+	 * generic omap-audio module.
+	 */
+	switch (cmd) {
+	case SNDCTL_DSP_STEREO:
+		ret = get_user(val, (int *) arg);
+		if (ret)
+			return ret;
+		/* the AIC23 is stereo only */
+		ret = (val == 0) ? -EINVAL : 1;
+		return put_user(ret, (int *) arg);
+
+	case SNDCTL_DSP_CHANNELS:
+	case SOUND_PCM_READ_CHANNELS:
+		/* the AIC23 is stereo only */
+		return put_user(2, (long *) arg);
+
+	case SNDCTL_DSP_SPEED:
+		ret = get_user(val, (long *) arg);
+		if (ret) break;
+		omap1510_set_samplerate(val);
+		/* fall through */
+
+	case SOUND_PCM_READ_RATE:
+		return put_user(audio_samplerate, (long *) arg);
+
+	case SNDCTL_DSP_SETFMT:
+	case SNDCTL_DSP_GETFMTS:
+		/* we can do 16-bit only */
+		return put_user(AFMT_S16_LE, (long *) arg);
+
+	default:
+		/* Maybe this is meant for the mixer (As per OSS Docs) */
+		return mixer_ioctl(inode, file, cmd, arg);
+	}
+
+	return ret;
+}
+
+static int omap1510_audio_open(struct inode *inode, struct file *file)
+{
+        // Set a flag so we know how to initialize hardware.
+        if (file->f_mode & FMODE_WRITE) {
+                input_or_output = FMODE_WRITE;
+        }
+        else if (file->f_mode & FMODE_READ) {
+                input_or_output = FMODE_READ;
+        }
+        else {
+                input_or_output = 0;
+        }
+                
+	return omap_audio_attach(inode, file, &audio_state);
+}
+
+/*
+ * Missing fields of this structure will be patched with the call
+ * to omap_audio_attach().
+ */
+static struct file_operations omap1510_audio_fops = {
+	open:		omap1510_audio_open,
+	owner:		THIS_MODULE
+};
+
+
+static int aic23_attach(struct i2c_adapter *adap, int addr,
+			unsigned short flags, int kind)
+{
+
+        // This makes sure this is only attached once.
+	if (this_adap > 0)
+		return -1;
+	this_adap++;
+	
+        aic23.adapter = adap;
+        aic23.addr = addr;
+
+        printk(__FUNCTION__": chip found @ 0x%x\n", addr<<1);
+
+        i2c_attach_client(&aic23);
+
+	MOD_INC_USE_COUNT;
+
+	return 0;
+}
+
+static int aic23_probe(struct i2c_adapter *adap)
+{
+	this_adap = 0;
+//	if (adap->id == I2C_ALGO_EXP)
+		return i2c_probe(adap, &addr_data, aic23_attach);
+	return 0;
+}
+
+static int aic23_detach(struct i2c_client *client)
+{
+	i2c_detach_client(client);
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+/* ----------------------------------------------------------------------- */
+
+static struct i2c_driver driver = {
+        "i2c aic23 driver",
+        I2C_DRIVERID_EXP0,           // Fake ID
+        I2C_DF_NOTIFY,
+        aic23_probe,
+        aic23_detach,
+};
+
+
+static int audio_dev_id, mixer_dev_id;
+
+static int __init omap1510_aic23_init(void)
+{
+	int ret;
+        u8 fpga;
+        
+        /*
+          Turn on chip select for CODEC (shared with touchscreen).  
+          Don't turn it back off, in case touch screen needs it.
+        */                           
+        fpga = fpga_read(OMAP1510P1_FPGA_TOUCHSCREEN);
+        fpga |= 0x4;
+        fpga_write(fpga, OMAP1510P1_FPGA_TOUCHSCREEN);
+        
+        aic23_local.volume = DEFAULT_VOLUME;
+
+	ret = i2c_add_driver(&driver);
+	if ((ret) || (this_adap == 0)) {          // didn't attach
+                printk( KERN_INFO "OMAP1510 audio support failed to find AIC23.\n" );
+		goto out;
+        }
+
+	/* register devices */
+	audio_dev_id = register_sound_dsp(&omap1510_audio_fops, -1);
+	mixer_dev_id = register_sound_mixer(&omap1510_mixer_fops, -1);
+
+	printk( KERN_INFO "OMAP1510 audio support initialized\n" );
+	return 0;
+
+out:
+	return ret;
+}
+
+static void __exit omap1510_aic23_exit(void)
+{
+	unregister_sound_dsp(audio_dev_id);
+	unregister_sound_mixer(mixer_dev_id);
+        i2c_del_driver(&driver);
+}
+
+module_init(omap1510_aic23_init);
+module_exit(omap1510_aic23_exit);
+
+MODULE_AUTHOR("Nicolas Pitre, George France, Steve Johnson");
+MODULE_DESCRIPTION("Glue audio driver for the TI OMAP1510 & AIC23 codec.");
+MODULE_LICENSE("GPL");
+
+EXPORT_NO_SYMBOLS;
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap1510-uda1341.c linux-2.4.19/drivers/sound/omap1510-uda1341.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap1510-uda1341.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/sound/omap1510-uda1341.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,452 @@
+/*
+ * Glue audio driver for the TI OMAP1510 & Philips UDA1341 codec.
+ *
+ * Copyright (c) 2000 Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 2001, Steve Johnson <stevej@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ *
+ * This is the machine specific part of the TI OMAP1510 support.
+ * This driver makes use of the UDA1341 and the omap1510-audio modules.
+ *
+ * History:
+ *
+ * 2000-05-21	Nicolas Pitre	Initial UDA1341 driver release.
+ *
+ * 2000-07-??	George France	Bitsy support.
+ *
+ * 2000-12-13	Deborah Wallach	Fixed power handling for iPAQ/h3600
+ *
+ * 2001-06-03	Nicolas Pitre	Made this file a separate module, based on
+ * 				the former sa1100-uda1341.c driver.
+ *
+ * 2001-07-13	Nicolas Pitre	Fixes for all supported samplerates.
+ *
+ * 2001-10-31   Steve Johnson   Modified for OMAP1510.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/errno.h>
+#include <linux/sound.h>
+#include <linux/soundcard.h>
+#include <linux/l3/l3.h>
+#include <linux/l3/uda1341.h>
+
+#include <asm/semaphore.h>
+#include <asm/uaccess.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/arch/fpga.h>
+#include <asm/arch/ck.h>
+
+#include "omap-audio.h"
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DPRINTK( x... )  printk( ##x )
+#else
+#define DPRINTK( x... )
+#endif
+
+
+#define AUDIO_NAME		"OMAP1510_UDA1341"
+
+#define AUDIO_RATE_DEFAULT	44100
+
+/*
+  Local prototypes.
+*/
+static void omap1510_audio_init(void *dummy);
+static void omap1510_audio_shutdown(void *dummy);
+static int omap1510_audio_ioctl(struct inode *inode, struct file *file,
+                                uint cmd, ulong arg);
+
+static struct l3_client uda1341;
+
+#if OLD_DMA
+static audio_stream_t output_stream = {
+        dma_ch: -1,
+};
+static audio_stream_t input_stream = {
+        dma_ch: -1,
+};
+#else
+static audio_stream_t output_stream;
+static audio_stream_t input_stream;
+#endif
+
+static audio_state_t audio_state = {
+	output_stream:	&output_stream,
+	output_dma:	eAudioTx,
+	output_id:	"UDA1341 out",
+	input_stream:	&input_stream,
+	input_dma:	eAudioRx,
+	input_id:	"UDA1341 in",
+//	need_tx_for_rx:	1,  TODO Try this once receive is working.
+	need_tx_for_rx:	0,
+	hw_init:	omap1510_audio_init,
+	hw_shutdown:	omap1510_audio_shutdown,
+	client_ioctl:	omap1510_audio_ioctl,
+	sem:		__MUTEX_INITIALIZER(audio_state.sem),
+};
+
+
+
+static int
+mixer_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg)
+{
+printk(__FUNCTION__ "called\n");
+	/*
+	 * We only accept mixer (type 'M') ioctls.
+	 */
+	if (_IOC_TYPE(cmd) != 'M')
+		return -EINVAL;
+
+	return l3_command(&uda1341, cmd, (void *)arg);
+}
+
+static struct file_operations omap1510_mixer_fops = {
+	ioctl:		mixer_ioctl,
+	owner:		THIS_MODULE
+};
+
+
+/*
+ * Audio interface
+ */
+
+static long audio_samplerate = AUDIO_RATE_DEFAULT;
+
+static void omap1510_set_samplerate(long val)
+{
+	struct uda1341_cfg cfg;
+        u8 fpga;
+
+printk(__FUNCTION__ "called\n");
+	/* We don't want to mess with clocks when frames are in flight */
+        // TODO - could call omap1510_dma_flush_all, or could poll on
+        // enable bit to wait for DMA writes to stop.
+
+	/* wait for any frame to complete */
+	udelay(125);
+
+        /*
+         * We have the following clock sources:
+         * 12.288 MHz and 16.9344 MHz.
+         * We have dividers in the FPGA (1, 2, 4), and in
+         * the codec.
+         *   clock   epld div  codec_div  freq
+         *  12.288     1        256       48K
+         *   "         4        384        8K
+         *  16.9344    1        384       44.1K
+         *   "         2        384       22.05K
+         *   "         4        384       11.025K
+         */
+
+        if (val >= 48000)
+                val = 48000;
+        else if (val >= 44100)
+                val = 44100;
+        else if (val >= 22050)
+                val = 22050;
+        else if (val >= 11025)
+                val = 11025;
+        else 
+                val = 8000;
+
+        /* Set the external clock generator */
+        switch (val) {
+        case 48000:
+        case 8000:
+                /* 12.288 MHz */
+                fpga = fpga_read(OMAP1510P1_FPGA_AUDIO);
+                if (fpga & 0x4) {
+                        fpga &= ~0x4;
+                        fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);
+                }
+                break;
+        default:
+                /* 16.3944 MHz */
+                fpga = fpga_read(OMAP1510P1_FPGA_AUDIO);
+                if ((fpga & 0x4) == 0) {
+                        fpga |= 0x4;
+                        fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);
+                }
+                break;
+        }
+
+        /* Select the clock divisor */
+        switch (val) {
+#if 0
+        case 
+        case 
+		cfg.fs = 512;
+                break;
+#endif
+        case 48000:
+		cfg.fs = 256;
+                break;
+        default:
+		cfg.fs = 384;
+                break;
+        }
+
+	cfg.format = FMT_I2S;
+	l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg);
+	audio_samplerate = val;
+}
+
+static void omap1510_audio_init(void *dummy)
+{
+        dma_regs_t *dma_regs = output_stream.dma_regs;
+        u8 fpga;
+
+printk(__FUNCTION__ "called\n");
+        /*                              
+          Init FPGA.       
+          Turn on Audio amplifier and set 12.288 MHz clock             
+        */                           
+        fpga = fpga_read(OMAP1510P1_FPGA_POWER);
+        fpga &= 0xfe;
+        fpga_write(fpga, OMAP1510P1_FPGA_POWER);
+        fpga = 0xc;        
+        fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);              
+
+
+#ifndef CONFIG_DSP_MCBSP1
+
+        /*
+          Now here's an ugly hack.  To use McBSP1, you need to enable
+          a clock on the DSP.  So enable the MPUI, set the clock,
+          and start the DSP.  
+
+          An even uglier, evil hack.  If this is going to take the DSP
+          out of reset, shove an idle loop at the reset vector
+          and make it loop instead of crash.  You will still see
+          a DSP watchdog timer go off.
+        */
+
+        {
+                u16 tmp;
+                u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
+
+                tmp = inw(ARM_RSTCT1);
+		// check if DSP is up
+                if (!(tmp & (ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN))) {
+                        if (!(tmp & ARM_RSTCT1_DSP_RST)) {   // MPUI in reset
+                                tmp |= ARM_RSTCT1_DSP_RST;
+                                outw(tmp, ARM_RSTCT1);
+                                ck_enable(api_ck);
+                        }
+			// REVISIT: I'm not finding this in the OMAP1509 TRM:
+                        tmp = inw(0xe1008008);
+                        if (0 == (tmp & 0x2)) {  // DSP CLKM enable
+                                tmp |= 0x2;
+                                outw(tmp, 0xe1008008);
+                        }
+                        tmp = inw(0xe1008014);
+                        if (0 == (tmp & 0x1)) {  // DSP PER_EN bit
+                                tmp |= 0x1;
+                                outw(tmp, 0xe1008014);
+                        }
+                        tmp = inw(ARM_CKCTL);   // Enable DSP
+                        tmp |= 0x2000;
+                        outw(tmp, ARM_CKCTL);
+                        // Write C55 code at reset vector.
+                        memcpy((OMAP1510_DSP_BASE + 0x4c000), 
+                               &c55_start, 
+                               sizeof(c55_start));
+                        outw(0x5, MPUI_DSP_BOOT_CONFIG); // Set DSP boot mode
+                        tmp = inw(ARM_RSTCT1);   // take DSP out of reset
+                        tmp |= ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN;
+                        outw(tmp, ARM_RSTCT1);                         
+                } else {
+			// DSP's up, just check the clock/per bits
+                        tmp = inw(0xe1008008);
+                        if (0 == (tmp & 0x2)) {  // DSP CLKM enable
+                                tmp |= 0x2;
+                                outw(tmp, 0xe1008008);
+                        }
+                        tmp = inw(0xe1008014);
+                        if (0 == (tmp & 0x1)) {  // DSP PER_EN bit
+                                tmp |= 0x1;
+                                outw(tmp, 0xe1008014);
+                        }
+                }
+        }          
+
+
+        /*  
+            While we're waiting for the UDA1341 to wake up, let's configure the
+            DMA channel and MCBSP.
+        */
+
+
+        // Setup DMA channel to McBSP1 audio Tx.
+        dma_regs->csdp = 0x0a01;
+        dma_regs->ccr = 0x1000 | audio_state.output_dma;            // source auto increment, don't enable yet
+        dma_regs->cicr = 0x0b;
+        dma_regs->cdsa_l = ((OMAP1510_MCBSP1_BASE + 0x806) & 0xffff);     //McBSP1 DXR1
+        dma_regs->cdsa_u = ((OMAP1510_MCBSP1_BASE + 0x806) >> 16);
+        dma_regs->cfn = 0x1;
+        omap_dma_setup(audio_state.output_dma, eDmaOut);
+
+        // Initialize McBSP channel
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x80a);  // SPCR1
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x808);  // SPCR2
+        outw(0x0f03, OMAP1510_MCBSP1_BASE + 0x824);  // PCR0
+        outw(0x0040, OMAP1510_MCBSP1_BASE + 0x80e);  // RCR1
+        outw(0x8045, OMAP1510_MCBSP1_BASE + 0x80c);  // RCR2
+        outw(0x0040, OMAP1510_MCBSP1_BASE + 0x812);  // XCR1
+        outw(0x8041, OMAP1510_MCBSP1_BASE + 0x810);  // XCR2
+        outw(0x0f0b, OMAP1510_MCBSP1_BASE + 0x816);  // SRGR1
+        outw(0x101f, OMAP1510_MCBSP1_BASE + 0x814);  // SRGR2
+        outw(0x0001, OMAP1510_MCBSP1_BASE + 0x80a);  // SPCR1 enable
+        outw(0x03f1, OMAP1510_MCBSP1_BASE + 0x808);  // SPCR2 enable
+
+#endif
+
+        /* Wait for the UDA1341 to wake up */
+        mdelay(1);
+
+        /* external clock configuration */
+        omap1510_set_samplerate(audio_samplerate);
+
+	/* Initialize the UDA1341 internal state */
+	l3_open(&uda1341);
+
+}
+
+static void omap1510_audio_shutdown(void *dummy)
+{
+        u8 fpga;
+printk(__FUNCTION__ "called\n");
+
+#ifndef CONFIG_DSP_MCBSP1
+
+        // Disable the McBSP channel
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x806);  // flush data
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x806);  // flush data
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x80a);  // disable SPCR1
+        outw(0x0000, OMAP1510_MCBSP1_BASE + 0x808);  // disable SPCR2     
+
+#endif
+
+	/* disable the audio clocks/signals */
+	l3_close(&uda1341);
+
+        // Turn off clocks, but don't turn off audio amplifier
+        // or you will hear a nasty noise when you turn it back
+        // on.
+        fpga = 0;
+        fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);
+}
+
+static int omap1510_audio_ioctl(struct inode *inode, struct file *file,
+                                uint cmd, ulong arg)
+{
+	long val;
+	int ret = 0;
+
+printk(__FUNCTION__ "called\n");
+	/*
+	 * These are platform dependent ioctls which are not handled by the
+	 * generic omap-audio module.
+	 */
+	switch (cmd) {
+	case SNDCTL_DSP_STEREO:
+		ret = get_user(val, (int *) arg);
+		if (ret)
+			return ret;
+		/* the UDA1341 is stereo only */
+		ret = (val == 0) ? -EINVAL : 1;
+		return put_user(ret, (int *) arg);
+
+	case SNDCTL_DSP_CHANNELS:
+	case SOUND_PCM_READ_CHANNELS:
+		/* the UDA1341 is stereo only */
+		return put_user(2, (long *) arg);
+
+	case SNDCTL_DSP_SPEED:
+		ret = get_user(val, (long *) arg);
+		if (ret) break;
+		omap1510_set_samplerate(val);
+		/* fall through */
+
+	case SOUND_PCM_READ_RATE:
+		return put_user(audio_samplerate, (long *) arg);
+
+	case SNDCTL_DSP_SETFMT:
+	case SNDCTL_DSP_GETFMTS:
+		/* we can do 16-bit only */
+		return put_user(AFMT_S16_LE, (long *) arg);
+
+	default:
+		/* Maybe this is meant for the mixer (As per OSS Docs) */
+		return mixer_ioctl(inode, file, cmd, arg);
+	}
+
+	return ret;
+}
+
+static int omap1510_audio_open(struct inode *inode, struct file *file)
+{
+printk(__FUNCTION__ "called\n");
+	return omap_audio_attach(inode, file, &audio_state);
+}
+
+/*
+ * Missing fields of this structure will be patched with the call
+ * to omap_audio_attach().
+ */
+static struct file_operations omap1510_audio_fops = {
+	open:		omap1510_audio_open,
+	owner:		THIS_MODULE
+};
+
+
+static int audio_dev_id, mixer_dev_id;
+
+static int __init omap1510_uda1341_init(void)
+{
+	int ret;
+
+printk(__FUNCTION__ "called\n");
+	ret = l3_attach_client(&uda1341, "l3-bit-omap1510-gpio", "uda1341");
+	if (ret)
+		goto out;
+
+	/* register devices */
+	audio_dev_id = register_sound_dsp(&omap1510_audio_fops, -1);
+	mixer_dev_id = register_sound_mixer(&omap1510_mixer_fops, -1);
+
+	printk( KERN_INFO "OMAP1510 audio support initialized\n" );
+	return 0;
+
+out:
+	return ret;
+}
+
+static void __exit omap1510_uda1341_exit(void)
+{
+printk(__FUNCTION__ "called\n");
+	unregister_sound_dsp(audio_dev_id);
+	unregister_sound_mixer(mixer_dev_id);
+	l3_detach_client(&uda1341);
+}
+
+module_init(omap1510_uda1341_init);
+module_exit(omap1510_uda1341_exit);
+
+MODULE_AUTHOR("Nicolas Pitre, George France, Steve Johnson");
+MODULE_DESCRIPTION("Glue audio driver for the TI OMAP1510 & Philips UDA1341 codec.");
+
+EXPORT_NO_SYMBOLS;
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap-audio.c linux-2.4.19/drivers/sound/omap-audio.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap-audio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/sound/omap-audio.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,1063 @@
+/*
+ * Common audio handling for the SA11x0 processor
+ *
+ * Copyright (C) 2000, 2001 Nicolas Pitre <nico@cam.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ *
+ *
+ * This module handles the generic buffering/DMA/mmap audio interface for
+ * codecs connected to the SA1100 chip.  All features depending on specific
+ * hardware implementations like supported audio formats or samplerates are
+ * relegated to separate specific modules.
+ *
+ *
+ * History:
+ *
+ * 2000-05-21	Nicolas Pitre	Initial release.
+ *
+ * 2000-06-10	Erik Bunce	Add initial poll support.
+ *
+ * 2000-08-22	Nicolas Pitre	Removed all DMA stuff. Now using the
+ * 				generic SA1100 DMA interface.
+ *
+ * 2000-11-30	Nicolas Pitre	- Validation of opened instances;
+ * 				- Power handling at open/release time instead
+ * 				  of driver load/unload;
+ *
+ * 2001-06-03	Nicolas Pitre	Made this file a separate module, based on
+ * 				the former sa1100-uda1341.c driver.
+ *
+ * 2001-07-22	Nicolas Pitre	- added mmap() and realtime support
+ * 				- corrected many details to better comply
+ * 				  with the OSS API
+ *
+ * 2001-10-19	Nicolas Pitre	- brought DMA registration processing
+ * 				  into this module for better ressource
+ * 				  management.  This also fixes a bug
+ * 				  with the suspend/resume logic.
+ *
+ * 2001-12-20	Nicolas Pitre	- moved DMA buffer handling out of the
+ * 				  generic code (since only this module
+ * 				  used it anyway) and reimplemented it
+ * 				  locally for much better efficiency.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/poll.h>
+#include <linux/pm.h>
+#include <linux/errno.h>
+#include <linux/sound.h>
+#include <linux/soundcard.h>
+#include <linux/sysrq.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/semaphore.h>
+#include <asm/dma.h>
+
+#include "omap-audio.h"
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DPRINTK( x... )  printk( ##x )
+#else
+#define DPRINTK( x... )
+#endif
+
+
+#define AUDIO_NAME		"omap-audio"
+#define AUDIO_NBFRAGS_DEFAULT	8
+#define AUDIO_FRAGSIZE_DEFAULT	32768
+
+
+#define AUDIO_ACTIVE(state)	((state)->rd_ref || (state)->wr_ref)
+
+#define SPIN_ADDR		(dma_addr_t)FLUSH_BASE_PHYS
+#define SPIN_SIZE		2048
+
+
+/*
+ * DMA processing
+ */
+
+#define DMA_REQUEST(dev, s, cb)	omap_request_dma(dev, "audio", cb, s, &s->dma_regs)
+#define DMA_FREE(s)		{omap_free_dma(s->dma_regs); s->dma_regs = 0;}
+#define DMA_START(s, d, l)	omap_start_dma(s->dma_regs, d, l)
+#define DMA_POS(s)		omap_get_dma_pos(s->dma_regs)
+#define DMA_STOP(s)		omap_stop_dma(s->dma_regs)
+#define DMA_CLEAR(s)		omap_clear_dma(s->dma_regs)
+#define DMA_RESET(s)		omap_reset_dma(s->dma_regs)
+
+static u_int audio_get_dma_pos(audio_stream_t *s)
+{
+	audio_buf_t *b = &s->buffers[s->dma_tail];
+	u_int offset;
+
+	if (b->dma_ref) {
+#if CONFIG_ARCH_OMAP
+                offset = 0;
+#else
+		offset = DMA_POS(s) - b->dma_addr;
+		if (offset >= s->fragsize)
+			offset = s->fragsize - 4;
+#endif
+	} else if (s->pending_frags) {
+		offset = b->offset;
+	} else {
+		offset = 0;
+	}
+	return offset;
+}
+
+
+static void audio_stop_dma(audio_stream_t *s)
+{
+	u_int pos;
+	unsigned long flags;
+	audio_buf_t *b;
+
+	if (s->dma_spinref > 0 || !s->buffers)
+		return;
+
+	local_irq_save(flags);
+	s->stopped = 1;
+	DMA_STOP(s);
+	pos = audio_get_dma_pos(s);
+	DMA_CLEAR(s);
+	if (s->spin_idle) {
+		DMA_START(s, SPIN_ADDR, SPIN_SIZE);
+		DMA_START(s, SPIN_ADDR, SPIN_SIZE);
+		s->dma_spinref = 2;
+	} else
+		s->dma_spinref = 0;
+	local_irq_restore(flags);
+
+	/* back up pointers to be ready to restart from the same spot */
+	while (s->dma_head != s->dma_tail) {
+		b = &s->buffers[s->dma_head];
+		if (b->dma_ref) {
+			b->dma_ref = 0;
+			b->offset = 0;
+		}
+		s->pending_frags++;
+		if (s->dma_head == 0)
+			s->dma_head = s->nbfrags;
+		s->dma_head--;
+	}
+	b = &s->buffers[s->dma_head];
+	if (b->dma_ref) {
+		b->offset = pos;
+		b->dma_ref = 0;
+	}
+}
+
+
+static void audio_reset(audio_stream_t *s)
+{
+	if (s->buffers) {
+		audio_stop_dma(s);
+		s->buffers[s->dma_head].offset = 0;
+		s->buffers[s->usr_head].offset = 0;
+		s->usr_head = s->dma_head;
+		s->pending_frags = 0;
+		sema_init(&s->sem, s->nbfrags);
+	}
+	s->active = 0;
+	s->stopped = 0;
+}
+
+
+static void audio_process_dma(audio_stream_t *s)
+{
+	int ret;
+
+	DPRINTK(__FUNCTION__ ": pending_frags = %d, usr_head = %d, dma_head = %d, dma_tail = %d, bytecount = %d, fragcount = %d\n",
+		s->pending_frags, s->usr_head, s->dma_head, s->dma_tail, s->bytecount, s->fragcount);
+	if (s->stopped)
+		goto spin;
+
+	if (s->dma_spinref > 0 && s->pending_frags) {
+		s->dma_spinref = 0;
+		DMA_CLEAR(s);
+	}
+
+	while (s->pending_frags) {
+		audio_buf_t *b = &s->buffers[s->dma_head];
+		u_int dma_size = s->fragsize - b->offset;
+		if (dma_size > MAX_DMA_SIZE)
+			dma_size = CUT_DMA_SIZE;
+		ret = DMA_START(s, b->dma_addr + b->offset, dma_size);
+		if (ret)
+			return;
+		b->dma_ref++;
+		b->offset += dma_size;
+		if (b->offset >= s->fragsize) {
+			s->pending_frags--;
+			if (++s->dma_head >= s->nbfrags)
+				s->dma_head = 0;
+		}
+	}
+
+spin:
+	if (s->spin_idle) {
+		int spincnt = 0;
+		while (DMA_START(s, SPIN_ADDR, SPIN_SIZE) == 0)
+			spincnt++;
+		/*
+		 * Note: if there is still a data buffer being
+		 * processed then the ref count is negative.  This
+		 * allows for the DMA termination to be accounted in
+		 * the proper order.  Of course dma_spinref can't be
+		 * greater than 0 if dma_ref is not 0 since we kill
+		 * the spinning above as soon as there is real data to process.
+		 */
+		if (s->buffers && s->buffers[s->dma_tail].dma_ref)
+			spincnt = -spincnt;
+		s->dma_spinref += spincnt;
+	}
+}
+
+
+static void audio_dma_callback(void *data)
+{
+	audio_stream_t *s = data;
+	audio_buf_t *b = &s->buffers[s->dma_tail];
+
+	DPRINTK(__FUNCTION__ ": b->dma_ref = %d, b->offset = %d\n", 
+		b->dma_ref, b->offset);
+
+	if (s->dma_spinref > 0) {
+		s->dma_spinref--;
+	} else if (!s->buffers) {
+		printk(KERN_CRIT "omap_audio: received DMA IRQ for non existent buffers!\n");
+		return;
+	} else if (b->dma_ref && --b->dma_ref == 0 && b->offset >= s->fragsize) {
+		/* This fragment is done */
+		b->offset = 0;
+		s->bytecount += s->fragsize;
+		s->fragcount++;
+		s->dma_spinref = -s->dma_spinref;
+		if (++s->dma_tail >= s->nbfrags)
+			s->dma_tail = 0;
+		if (!s->mapped)
+			up(&s->sem);
+		else
+			s->pending_frags++;
+		wake_up(&s->wq);
+	}
+
+	audio_process_dma(s);
+}
+
+
+/*
+ * Buffer creation/destruction
+ */
+
+static void audio_discard_buf(audio_stream_t * s)
+{
+	DPRINTK("audio_discard_buf\n");
+
+	/* ensure DMA isn't using those buffers */
+	audio_reset(s);
+
+	if (s->buffers) {
+		int frag;
+		for (frag = 0; frag < s->nbfrags; frag++) {
+			if (!s->buffers[frag].master)
+				continue;
+			consistent_free(s->buffers[frag].data,
+					s->buffers[frag].master,
+					s->buffers[frag].dma_addr);
+		}
+		kfree(s->buffers);
+		s->buffers = NULL;
+	}
+}
+
+
+static int audio_setup_buf(audio_stream_t * s)
+{
+	int frag;
+	int dmasize = 0;
+	char *dmabuf = NULL;
+	dma_addr_t dmaphys = 0;
+
+	if (s->buffers)
+		return -EBUSY;
+
+	s->buffers = kmalloc(sizeof(audio_buf_t) * s->nbfrags, GFP_KERNEL);
+	if (!s->buffers)
+		goto err;
+	memset(s->buffers, 0, sizeof(audio_buf_t) * s->nbfrags);
+
+	for (frag = 0; frag < s->nbfrags; frag++) {
+		audio_buf_t *b = &s->buffers[frag];
+
+		/*
+		 * Let's allocate non-cached memory for DMA buffers.
+		 * We try to allocate all memory at once.
+		 * If this fails (a common reason is memory fragmentation),
+		 * then we allocate more smaller buffers.
+		 */
+		if (!dmasize) {
+			dmasize = (s->nbfrags - frag) * s->fragsize;
+			do {
+			  	dmabuf = consistent_alloc(GFP_KERNEL|GFP_DMA,
+							  dmasize,
+							  &dmaphys);
+				if (!dmabuf)
+					dmasize -= s->fragsize;
+			} while (!dmabuf && dmasize);
+			if (!dmabuf)
+				goto err;
+			b->master = dmasize;
+			memzero(dmabuf, dmasize);
+		}
+
+		b->data = dmabuf;
+		b->dma_addr = dmaphys;
+		DPRINTK("buf %d: start %p dma %#08x master %d fragsize %d\n", 
+			frag, b->data, b->dma_addr, b->master, s->fragsize);
+
+		dmabuf += s->fragsize;
+		dmaphys += s->fragsize;
+		dmasize -= s->fragsize;
+	}
+
+	s->usr_head = s->dma_head = s->dma_tail = 0;
+	s->bytecount = 0;
+	s->fragcount = 0;
+	sema_init(&s->sem, s->nbfrags);
+
+	return 0;
+
+err:
+	printk(AUDIO_NAME ": unable to allocate audio memory\n ");
+	audio_discard_buf(s);
+	return -ENOMEM;
+}
+
+
+/*
+ * Driver interface functions
+ */
+
+static int audio_write(struct file *file, const char *buffer,
+		       size_t count, loff_t * ppos)
+{
+	const char *buffer0 = buffer;
+	audio_state_t *state = file->private_data;
+	audio_stream_t *s = state->output_stream;
+	int chunksize, ret = 0;
+	unsigned long flags;
+
+	DPRINTK("audio_write: count=%d\n", count);
+
+	if (ppos != &file->f_pos)
+		return -ESPIPE;
+	if (s->mapped)
+		return -ENXIO;
+	if (!s->buffers && audio_setup_buf(s))
+		return -ENOMEM;
+
+	while (count > 0) {
+		audio_buf_t *b = &s->buffers[s->usr_head];
+
+		/* Wait for a buffer to become free */
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			if (down_trylock(&s->sem))
+				break;
+		} else {
+			ret = -ERESTARTSYS;
+			if (down_interruptible(&s->sem))
+				break;
+		}
+
+		/* Feed the current buffer */
+		chunksize = s->fragsize - b->offset;
+		if (chunksize > count)
+			chunksize = count;
+		DPRINTK("write %d to %d\n", chunksize, s->usr_head);
+		if (copy_from_user(b->data + b->offset, buffer, chunksize)) {
+			up(&s->sem);
+			return -EFAULT;
+		}
+		buffer += chunksize;
+		count -= chunksize;
+		b->offset += chunksize;
+		if (b->offset < s->fragsize) {
+			up(&s->sem);
+			break;
+		}
+
+		/* Update pointers and send current fragment to DMA */
+		b->offset = 0;
+		if (++s->usr_head >= s->nbfrags)
+			s->usr_head = 0;
+		local_irq_save(flags);
+		s->pending_frags++;
+		s->active = 1;
+		audio_process_dma(s);
+		local_irq_restore(flags);
+	}
+
+	if ((buffer - buffer0))
+		ret = buffer - buffer0;
+	DPRINTK("audio_write: return=%d\n", ret);
+	return ret;
+}
+
+
+static void audio_prime_rx(audio_state_t *state)
+{
+	audio_stream_t *is = state->input_stream;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (state->need_tx_for_rx) {
+		/*
+		 * With some codecs like the Philips UDA1341 we must ensure
+		 * there is an output stream at any time while recording since
+		 * this is how the UDA1341 gets its clock from the SA1100.
+		 * So while there is no playback data to send, the output DMA
+		 * will spin with all zeroes.  We use the cache flush special
+		 * area for that.
+		 */
+		state->output_stream->spin_idle = 1;
+		audio_process_dma(state->output_stream);
+	}
+	is->pending_frags = is->nbfrags;
+	sema_init(&is->sem, 0);
+	is->active = 1;
+	audio_process_dma(is);
+	local_irq_restore(flags);
+}
+
+
+static int audio_read(struct file *file, char *buffer,
+		      size_t count, loff_t * ppos)
+{
+	char *buffer0 = buffer;
+	audio_state_t *state = file->private_data;
+	audio_stream_t *s = state->input_stream;
+	int chunksize, ret = 0;
+	unsigned long flags;
+
+	DPRINTK("audio_read: count=%d\n", count);
+
+	if (ppos != &file->f_pos)
+		return -ESPIPE;
+	if (s->mapped)
+		return -ENXIO;
+
+	if (!s->active) {
+		if (!s->buffers && audio_setup_buf(s))
+			return -ENOMEM;
+		audio_prime_rx(state);
+	}
+
+	while (count > 0) {
+		audio_buf_t *b = &s->buffers[s->usr_head];
+
+		/* Wait for a buffer to become full */
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			if (down_trylock(&s->sem))
+				break;
+		} else {
+			ret = -ERESTARTSYS;
+			if (down_interruptible(&s->sem))
+				break;
+		}
+
+		/* Grab data from the current buffer */
+		chunksize = s->fragsize - b->offset;
+		if (chunksize > count)
+			chunksize = count;
+		DPRINTK("read %d from %d\n", chunksize, s->usr_head);
+		if (copy_to_user(buffer, b->data+ b->offset, chunksize)) {
+			up(&s->sem);
+			return -EFAULT;
+		}
+		buffer += chunksize;
+		count -= chunksize;
+		b->offset += chunksize;
+		if (b->offset < s->fragsize) {
+			up(&s->sem);
+			break;
+		}
+
+		/* Update pointers and return current fragment to DMA */
+		b->offset = 0;
+		if (++s->usr_head >= s->nbfrags)
+			s->usr_head = 0;
+		local_irq_save(flags);
+		s->pending_frags++;
+		audio_process_dma(s);
+		local_irq_restore(flags);
+	}
+
+	if ((buffer - buffer0))
+		ret = buffer - buffer0;
+	DPRINTK("audio_read: return=%d\n", ret);
+	return ret;
+}
+
+static int audio_sync(struct file *file)
+{
+	audio_state_t *state = file->private_data;
+	audio_stream_t *s = state->output_stream;
+	audio_buf_t *b;
+	u_int shiftval = 0;
+	unsigned long flags;
+	DECLARE_WAITQUEUE(wait, current);
+
+	DPRINTK("audio_sync\n");
+
+	if (!(file->f_mode & FMODE_WRITE) || !s->buffers || s->mapped)
+		return 0;
+
+	/*
+	 * Send current buffer if it contains data.  Be sure to send
+	 * a full sample count.
+	 */
+	b = &s->buffers[s->usr_head];
+	if (b->offset &= ~3) {
+		down(&s->sem);
+		/*
+		 * HACK ALERT !
+		 * To avoid increased complexity in the rest of the code
+		 * where full fragment sizes are assumed, we cheat a little
+		 * with the start pointer here and don't forget to restore
+		 * it later.
+		 */
+		shiftval = s->fragsize - b->offset;
+		b->offset = shiftval;
+		b->dma_addr -= shiftval;
+		s->bytecount -= shiftval;
+		if (++s->usr_head >= s->nbfrags)
+			s->usr_head = 0;
+		local_irq_save(flags);
+		s->pending_frags++;
+		audio_process_dma(s);
+		local_irq_restore(flags);
+	}
+
+	/* Let's wait for all buffers to complete */
+	set_current_state(TASK_INTERRUPTIBLE);
+	add_wait_queue(&s->wq, &wait);
+	while (s->pending_frags &&
+	       s->dma_tail != s->usr_head &&
+	       !signal_pending(current)) {
+		schedule();
+		set_current_state(TASK_INTERRUPTIBLE);
+	}
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&s->wq, &wait);
+
+	/* undo the pointer hack above */
+	if (shiftval) {
+		local_irq_save(flags);
+		b->dma_addr += shiftval;
+		/* ensure sane DMA code behavior if not yet processed */
+		if (b->offset != 0)
+			b->offset = s->fragsize;
+		local_irq_restore(flags);
+	}
+
+	return 0;
+}
+
+static int audio_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	audio_state_t *state = file->private_data;
+	audio_stream_t *s;
+	unsigned long size, vma_addr;
+	int i, ret;
+
+	if (vma->vm_pgoff != 0)
+		return -EINVAL;
+
+	if (vma->vm_flags & VM_WRITE) {
+		if (!state->wr_ref)
+			return -EINVAL;;
+		s = state->output_stream;
+	} else if (vma->vm_flags & VM_READ) {
+		if (!state->rd_ref)
+			return -EINVAL;
+		s = state->input_stream;
+	} else return -EINVAL;
+
+	if (s->mapped)
+		return -EINVAL;
+	size = vma->vm_end - vma->vm_start;
+	if (size != s->fragsize * s->nbfrags)
+		return -EINVAL;
+	if (!s->buffers && audio_setup_buf(s))
+		return -ENOMEM;
+	vma_addr = vma->vm_start;
+	for (i = 0; i < s->nbfrags; i++) {
+		audio_buf_t *buf = &s->buffers[i];
+		if (!buf->master)
+			continue;
+		ret = remap_page_range(vma_addr, buf->dma_addr, buf->master, vma->vm_page_prot);
+		if (ret)
+			return ret;
+		vma_addr += buf->master;
+	}
+	s->mapped = 1;
+
+	return 0;
+}
+
+static unsigned int audio_poll(struct file *file,
+			       struct poll_table_struct *wait)
+{
+	audio_state_t *state = file->private_data;
+	audio_stream_t *is = state->input_stream;
+	audio_stream_t *os = state->output_stream;
+	unsigned int mask = 0;
+
+	DPRINTK("audio_poll(): mode=%s%s\n",
+		(file->f_mode & FMODE_READ) ? "r" : "",
+		(file->f_mode & FMODE_WRITE) ? "w" : "");
+
+	if (file->f_mode & FMODE_READ) {
+		/* Start audio input if not already active */
+		if (!is->active) {
+			if (!is->buffers && audio_setup_buf(is))
+				return -ENOMEM;
+			audio_prime_rx(state);
+		}
+		poll_wait(file, &is->wq, wait);
+	}
+
+	if (file->f_mode & FMODE_WRITE) {
+		if (!os->buffers && audio_setup_buf(os))
+			return -ENOMEM;
+		poll_wait(file, &os->wq, wait);
+	}
+
+	if (file->f_mode & FMODE_READ)
+		if (( is->mapped && is->bytecount > 0) ||
+		    (!is->mapped && atomic_read(&is->sem.count) > 0))
+			mask |= POLLIN | POLLRDNORM;
+
+	if (file->f_mode & FMODE_WRITE)
+		if (( os->mapped && os->bytecount > 0) ||
+		    (!os->mapped && atomic_read(&os->sem.count) > 0))
+			mask |= POLLOUT | POLLWRNORM;
+
+	DPRINTK("audio_poll() returned mask of %s%s\n",
+		(mask & POLLIN) ? "r" : "",
+		(mask & POLLOUT) ? "w" : "");
+
+	return mask;
+}
+
+static loff_t audio_llseek(struct file *file, loff_t offset, int origin)
+{
+	return -ESPIPE;
+}
+
+static int audio_set_fragments(audio_stream_t *s, int val)
+{
+	if (s->active)
+		return -EBUSY;
+	if (s->buffers)
+		audio_discard_buf(s);
+	s->nbfrags = (val >> 16) & 0x7FFF;
+	val &= 0xffff;
+	if (val < 4)
+		val = 4;
+	if (val > 15)
+		val = 15;
+	s->fragsize = 1 << val;
+	if (s->nbfrags < 2)
+		s->nbfrags = 2;
+	if (s->nbfrags * s->fragsize > 128 * 1024)
+		s->nbfrags = 128 * 1024 / s->fragsize;
+	if (audio_setup_buf(s))
+		return -ENOMEM;
+	return val|(s->nbfrags << 16);
+}
+
+static int audio_ioctl(struct inode *inode, struct file *file,
+		       uint cmd, ulong arg)
+{
+	audio_state_t *state = file->private_data;
+	audio_stream_t *os = state->output_stream;
+	audio_stream_t *is = state->input_stream;
+	long val;
+
+	DPRINTK(__FILE__ " audio_ioctl 0x%08x\n", cmd);
+
+	/* dispatch based on command */
+	switch (cmd) {
+	case OSS_GETVERSION:
+		return put_user(SOUND_VERSION, (int *)arg);
+
+	case SNDCTL_DSP_GETBLKSIZE:
+		if (file->f_mode & FMODE_WRITE)
+			return put_user(os->fragsize, (int *)arg);
+		else
+			return put_user(is->fragsize, (int *)arg);
+
+	case SNDCTL_DSP_GETCAPS:
+		val = DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP;
+		if (is && os)
+			val |= DSP_CAP_DUPLEX;
+		return put_user(val, (int *)arg);
+
+	case SNDCTL_DSP_SETFRAGMENT:
+		if (get_user(val, (long *) arg))
+			return -EFAULT;
+		if (file->f_mode & FMODE_READ) {
+			int ret = audio_set_fragments(is, val);
+			if (ret < 0)
+				return ret;
+			ret = put_user(ret, (int *)arg);
+			if (ret)
+				return ret;
+		}
+		if (file->f_mode & FMODE_WRITE) {
+			int ret = audio_set_fragments(os, val);
+			if (ret < 0)
+				return ret;
+			ret = put_user(ret, (int *)arg);
+			if (ret)
+				return ret;
+		}
+		return 0;
+
+	case SNDCTL_DSP_SYNC:
+		return audio_sync(file);
+
+	case SNDCTL_DSP_SETDUPLEX:
+		return 0;
+
+	case SNDCTL_DSP_POST:
+		return 0;
+
+	case SNDCTL_DSP_GETTRIGGER:
+		val = 0;
+		if (file->f_mode & FMODE_READ && is->active && !is->stopped)
+			val |= PCM_ENABLE_INPUT;
+		if (file->f_mode & FMODE_WRITE && os->active && !os->stopped)
+			val |= PCM_ENABLE_OUTPUT;
+		return put_user(val, (int *)arg);
+
+	case SNDCTL_DSP_SETTRIGGER:
+		if (get_user(val, (int *)arg))
+			return -EFAULT;
+		if (file->f_mode & FMODE_READ) {
+			if (val & PCM_ENABLE_INPUT) {
+				unsigned long flags;
+				if (!is->active) {
+					if (!is->buffers && audio_setup_buf(is))
+						return -ENOMEM;
+					audio_prime_rx(state);
+				}
+				local_irq_save(flags);
+				is->stopped = 0;
+				audio_process_dma(is);
+				local_irq_restore(flags);
+			} else {
+				audio_stop_dma(is);
+			}
+		}
+		if (file->f_mode & FMODE_WRITE) {
+			if (val & PCM_ENABLE_OUTPUT) {
+				unsigned long flags;
+				if (!os->buffers && audio_setup_buf(os))
+					return -ENOMEM;
+				local_irq_save(flags);
+				if (os->mapped && !os->pending_frags) {
+					os->pending_frags = os->nbfrags;
+					sema_init(&os->sem, 0);
+					os->active = 1;
+				}
+				os->stopped = 0;
+				audio_process_dma(os);
+				local_irq_restore(flags);
+			} else {
+				audio_stop_dma(os);
+			}
+		}
+		return 0;
+
+	case SNDCTL_DSP_GETOPTR:
+	case SNDCTL_DSP_GETIPTR:
+	    {
+		count_info inf = { 0, };
+		audio_stream_t *s = (cmd == SNDCTL_DSP_GETOPTR) ? os : is;
+		int bytecount, offset;
+		unsigned long flags;
+
+		if ((s == is && !(file->f_mode & FMODE_READ)) ||
+		    (s == os && !(file->f_mode & FMODE_WRITE)))
+			return -EINVAL;
+		if (s->active) {
+			local_irq_save(flags);
+			offset = audio_get_dma_pos(s);
+			inf.ptr = s->dma_tail * s->fragsize + offset;
+			bytecount = s->bytecount + offset;
+			s->bytecount = -offset;
+			inf.blocks = s->fragcount;
+			s->fragcount = 0;
+			local_irq_restore(flags);
+			if (bytecount < 0)
+				bytecount = 0;
+			inf.bytes = bytecount;
+		}
+		return copy_to_user((void *)arg, &inf, sizeof(inf));
+	    }
+
+	case SNDCTL_DSP_GETOSPACE:
+	case SNDCTL_DSP_GETISPACE:
+	    {
+		audio_buf_info inf = { 0, };
+		audio_stream_t *s = (cmd == SNDCTL_DSP_GETOSPACE) ? os : is;
+
+		if ((s == is && !(file->f_mode & FMODE_READ)) ||
+		    (s == os && !(file->f_mode & FMODE_WRITE)))
+			return -EINVAL;
+		if (!s->buffers && audio_setup_buf(s))
+			return -ENOMEM;
+		inf.bytes = atomic_read(&s->sem.count) * s->fragsize;
+		inf.bytes -= s->buffers[s->usr_head].offset;
+		inf.fragments = inf.bytes / s->fragsize;
+		inf.fragsize = s->fragsize;
+		inf.fragstotal = s->nbfrags;
+		return copy_to_user((void *)arg, &inf, sizeof(inf));
+	    }
+
+	case SNDCTL_DSP_NONBLOCK:
+		file->f_flags |= O_NONBLOCK;
+		return 0;
+
+	case SNDCTL_DSP_RESET:
+		if (file->f_mode & FMODE_READ) {
+			audio_reset(is);
+			if (state->need_tx_for_rx) {
+				unsigned long flags;
+				local_irq_save(flags);
+				os->spin_idle = 0;
+				local_irq_restore(flags);
+			}
+		}
+		if (file->f_mode & FMODE_WRITE) {
+			audio_reset(os);
+		}
+		return 0;
+
+	default:
+		/*
+		 * Let the client of this module handle the
+		 * non generic ioctls
+		 */
+		return state->client_ioctl(inode, file, cmd, arg);
+	}
+
+	return 0;
+}
+
+static int audio_release(struct inode *inode, struct file *file)
+{
+	audio_state_t *state = file->private_data;
+	audio_stream_t *os = state->output_stream;
+	audio_stream_t *is = state->input_stream;
+
+	DPRINTK("audio_release\n");
+
+	down(&state->sem);
+
+	if (file->f_mode & FMODE_READ) {
+		audio_discard_buf(is);
+		DMA_FREE(is);
+		is->dma_spinref = 0;
+		if (state->need_tx_for_rx) {
+			os->spin_idle = 0;
+			if (!state->wr_ref) {
+				DMA_FREE(os);
+				os->dma_spinref = 0;
+			}
+		}
+		state->rd_ref = 0;
+	}
+
+	if (file->f_mode & FMODE_WRITE) {
+		audio_sync(file);
+		audio_discard_buf(os);
+		if (!state->need_tx_for_rx || !state->rd_ref) {
+			DMA_FREE(os);
+			os->dma_spinref = 0;
+		}
+		state->wr_ref = 0;
+	}
+
+	if (!AUDIO_ACTIVE(state)) {
+	       if (state->hw_shutdown)
+		       state->hw_shutdown(state->data);
+#ifdef CONFIG_PM
+	       pm_unregister(state->pm_dev);
+#endif
+	}
+
+	up(&state->sem);
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+
+static int audio_pm_callback(struct pm_dev *pm_dev, pm_request_t req, void *data)
+{
+	audio_state_t *state = pm_dev->data;
+	audio_stream_t *is = state->input_stream;
+	audio_stream_t *os = state->output_stream;
+	int stopstate;
+
+	switch (req) {
+	case PM_SUSPEND: /* enter D1-D3 */
+		if (is && is->dma_regs) {
+			stopstate = is->stopped;
+			audio_stop_dma(is);
+			DMA_CLEAR(is);
+			is->dma_spinref = 0;
+			is->stopped = stopstate;
+		}
+		if (os && os->dma_regs) {
+			stopstate = os->stopped;
+			audio_stop_dma(os);
+			DMA_CLEAR(os);
+			os->dma_spinref = 0;
+			os->stopped = stopstate;
+		}
+		if (AUDIO_ACTIVE(state) && state->hw_shutdown)
+			state->hw_shutdown(state->data);
+		break;
+	case PM_RESUME:  /* enter D0 */
+		if (AUDIO_ACTIVE(state) && state->hw_init)
+			state->hw_init(state->data);
+		if (os && os->dma_regs) {
+			DMA_RESET(os);
+			audio_process_dma(os);
+		}
+		if (is && is->dma_regs) {
+			DMA_RESET(is);
+			audio_process_dma(is);
+		}
+		break;
+	}
+	return 0;
+}
+
+#endif
+
+
+int omap_audio_attach(struct inode *inode, struct file *file,
+			audio_state_t *state)
+{
+	audio_stream_t *os = state->output_stream;
+	audio_stream_t *is = state->input_stream;
+	int err, need_tx_dma;
+
+	DPRINTK("audio_open\n");
+
+	down(&state->sem);
+
+	/* access control */
+	err = -ENODEV;
+	if ((file->f_mode & FMODE_WRITE) && !os)
+		goto out;
+	if ((file->f_mode & FMODE_READ) && !is)
+		goto out;
+	err = -EBUSY;
+	if ((file->f_mode & FMODE_WRITE) && state->wr_ref)
+		goto out;
+	if ((file->f_mode & FMODE_READ) && state->rd_ref)
+		goto out;
+	err = -EINVAL;
+	if ((file->f_mode & FMODE_READ) && state->need_tx_for_rx && !os)
+		goto out;
+
+	/* request DMA channels */
+	need_tx_dma = ((file->f_mode & FMODE_WRITE) ||
+		       ((file->f_mode & FMODE_READ) && state->need_tx_for_rx));
+	if (state->wr_ref || (state->rd_ref && state->need_tx_for_rx))
+		need_tx_dma = 0;
+	if (need_tx_dma) {
+		err = DMA_REQUEST(state->output_dma, os, audio_dma_callback);
+		if (err)
+			goto out;
+	}
+	if (file->f_mode & FMODE_READ) {
+		err = DMA_REQUEST(state->input_dma, is, audio_dma_callback);
+		if (err) {
+			if (need_tx_dma)
+				DMA_FREE(os);
+			goto out;
+		}
+	}
+
+	/* now complete initialisation */
+	if (!AUDIO_ACTIVE(state)) {
+		if (state->hw_init)
+			state->hw_init(state->data);
+#ifdef CONFIG_PM
+		state->pm_dev = pm_register(PM_SYS_DEV, 0, audio_pm_callback);
+		if (state->pm_dev)
+			state->pm_dev->data = state;
+#endif
+	}
+
+	if ((file->f_mode & FMODE_WRITE)) {
+		state->wr_ref = 1;
+		audio_reset(os);
+		os->fragsize = AUDIO_FRAGSIZE_DEFAULT;
+		os->nbfrags = AUDIO_NBFRAGS_DEFAULT;
+		os->mapped = 0;
+		init_waitqueue_head(&os->wq);
+	}
+	if (file->f_mode & FMODE_READ) {
+		state->rd_ref = 1;
+		audio_reset(is);
+		is->fragsize = AUDIO_FRAGSIZE_DEFAULT;
+		is->nbfrags = AUDIO_NBFRAGS_DEFAULT;
+		is->mapped = 0;
+		init_waitqueue_head(&is->wq);
+	}
+
+	file->private_data	= state;
+	file->f_op->release	= audio_release;
+	file->f_op->write	= audio_write;
+	file->f_op->read	= audio_read;
+	file->f_op->mmap	= audio_mmap;
+	file->f_op->poll	= audio_poll;
+	file->f_op->ioctl	= audio_ioctl;
+	file->f_op->llseek	= audio_llseek;
+	err = 0;
+
+out:
+	up(&state->sem);
+	return err;
+}
+
+EXPORT_SYMBOL(omap_audio_attach);
+
+MODULE_AUTHOR("Nicolas Pitre");
+MODULE_DESCRIPTION("Common audio handling for OMAP processors");
+MODULE_LICENSE("GPL");
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap-audio.h linux-2.4.19/drivers/sound/omap-audio.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/sound/omap-audio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/sound/omap-audio.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,69 @@
+/*
+ * Common audio handling for TI OMAP
+ *
+ * Copyright (c) 2000 Nicolas Pitre <nico@cam.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+
+/*
+ * Buffer Management
+ */
+
+typedef struct {
+	int offset;		/* current offset */
+	char *data;		/* points to actual buffer */
+	dma_addr_t dma_addr;	/* physical buffer address */
+	int dma_ref;		/* DMA refcount */
+	int master;		/* owner for buffer allocation, contain size when true */
+} audio_buf_t;
+
+typedef struct {
+	audio_buf_t *buffers;	/* pointer to audio buffer structures */
+	u_int usr_head;		/* user fragment index */
+	u_int dma_head;		/* DMA fragment index to go */
+	u_int dma_tail;		/* DMA fragment index to complete */
+	u_int fragsize;		/* fragment i.e. buffer size */
+	u_int nbfrags;		/* nbr of fragments i.e. buffers */
+	u_int pending_frags;	/* Fragments sent to DMA */
+	dma_regs_t *dma_regs;	/* points to our DMA registers */
+	int bytecount;		/* nbr of processed bytes */
+	int fragcount;		/* nbr of fragment transitions */
+	struct semaphore sem;	/* account for fragment usage */
+	wait_queue_head_t wq;	/* for poll */
+	int dma_spinref;	/* DMA is spinning */
+	int mapped:1;		/* mmap()'ed buffers */
+	int active:1;		/* actually in progress */
+	int stopped:1;		/* might be active but stopped */
+	int spin_idle:1;	/* have DMA spin on zeros when idle */
+} audio_stream_t;
+
+/*
+ * State structure for one instance
+ */
+
+typedef struct {
+	audio_stream_t *output_stream;
+	audio_stream_t *input_stream;
+	dma_device_t output_dma;
+	dma_device_t input_dma;
+	char *output_id;
+	char *input_id;
+	int rd_ref:1;		/* open reference for recording */
+	int wr_ref:1;		/* open reference for playback */
+	int need_tx_for_rx:1;	/* if data must be sent while receiving */
+	void *data;
+	void (*hw_init)(void *);
+	void (*hw_shutdown)(void *);
+	int (*client_ioctl)(struct inode *, struct file *, uint, ulong);
+	struct pm_dev *pm_dev;
+	struct semaphore sem;	/* to protect against races in attach() */
+} audio_state_t;
+
+/*
+ * Functions exported by this module
+ */
+extern int omap_audio_attach( struct inode *inode, struct file *file,
+				audio_state_t *state);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/usb/Config.in linux-2.4.19/drivers/usb/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/usb/Config.in	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/usb/Config.in	2003-01-15 10:06:28.000000000 +0200
@@ -5,7 +5,7 @@
 comment 'USB support'
 
 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
-if [ "$CONFIG_PCI" = "y" -o "$CONFIG_SA1111" = "y" ]; then
+if [ "$CONFIG_PCI" = "y" -o "$CONFIG_SA1111" = "y" -o "$CONFIG_ARCH_OMAP1510" = "y" ]; then
    tristate 'Support for USB' CONFIG_USB
 else
    define_bool CONFIG_USB n
@@ -35,6 +35,9 @@
    fi
    dep_tristate '  OHCI (Compaq, iMacs, OPTi, SiS, ALi, ...) support' CONFIG_USB_OHCI $CONFIG_USB
    dep_tristate '  SA1111 OHCI-compatible host interface support' CONFIG_USB_OHCI_SA1111 $CONFIG_USB
+   if [ "$CONFIG_ARCH_OMAP1510" = "y" ]; then
+     dep_tristate '    OMAP1510 OHCI-compatible host interface support' CONFIG_USB_OHCI_OMAP1510 $CONFIG_USB_OHCI
+   fi
 
    comment 'USB Device Class drivers'
    dep_tristate '  USB Audio support' CONFIG_USB_AUDIO $CONFIG_USB $CONFIG_SOUND
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/usb/Makefile linux-2.4.19/drivers/usb/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/usb/Makefile	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/usb/Makefile	2003-01-15 10:06:08.000000000 +0200
@@ -11,6 +11,7 @@
 # Objects that export symbols.
 
 export-objs		:= hcd.o usb.o ov511.o pwc-uncompress.o
+export-objs		+= omap1510-pci-pool.o
 
 # Multipart objects.
 
@@ -53,6 +54,7 @@
 obj-$(CONFIG_USB_UHCI)		+= usb-uhci.o
 obj-$(CONFIG_USB_UHCI_ALT)	+= uhci.o
 obj-$(CONFIG_USB_OHCI)		+= usb-ohci.o usb-ohci-pci.o
+obj-$(CONFIG_USB_OHCI_OMAP1510) += usb-ohci-omap1510.o omap1510-pci-pool.o
 obj-$(CONFIG_USB_OHCI_SA1111)	+= usb-ohci.o usb-ohci-sa1111.o
 
 ifneq ($(CONFIG_USB_EHCI_HCD),n)
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/usb/omap1510-pci-pool.c linux-2.4.19/drivers/usb/omap1510-pci-pool.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/usb/omap1510-pci-pool.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/usb/omap1510-pci-pool.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,453 @@
+/*
+ * omap1510-pci-pool.c
+ *
+ * This is a copy of drivers/pci/pci.c with everything except the pool 
+ * allocator deleted.  We need the pool allocator for the usb-ohci driver, and 
+ * some targets which use this driver do not have a PCI bus.
+ *
+ *	$Id: omap1510-pci-pool.c,v 1.1 2003/01/09 17:49:04 tmlind Exp $
+ *
+ *	PCI Bus Services, see include/linux/pci.h for further explanation.
+ *
+ *	Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ *	David Mosberger-Tang
+ *
+ *	Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/spinlock.h>
+#include <linux/pm.h>
+#include <linux/kmod.h>		/* for hotplug_path */
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/cache.h>
+
+#include <asm/page.h>
+#include <asm/dma.h>	/* isa_dma_bridge_buggy */
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* Here is a hack to replace the pci_alloc_consistent() function with one that 
+ * returns the USB local bus address for the DMA handle.  We are assuming 
+ * that the local bus MMU has been programmed such that RAM is linearly 
+ * mapped to the local bus address space beginning at 0x30000000.  If this 
+ * MMU mapping is implemented through static TLB loading as is done above, then 
+ * this only works for systems with a maximum of 32MB of RAM as that is the 
+ * most we can statically map with our 32 local bus MMU TLBs.
+ * It would be cleaner to do this by defining virt_to_bus() and 
+ * bus_to_virt() so that they convert between kernel virtual addresses 
+ * and USB local bus addresses, but there are other OMAP drivers that have been 
+ * written under the assumption that virt_to_bus() and bus_to_virt() convert 
+ * between kernel virtual addresses and physical addresses.
+ */
+
+#define OMAP1510_LB_OFFSET (0x30000000UL)
+
+#define phys_to_lb(x) (((unsigned long) (x)) - PHYS_OFFSET + OMAP1510_LB_OFFSET)
+#define lb_to_phys(x) (((unsigned long) (x)) - OMAP1510_LB_OFFSET + PHYS_OFFSET)
+
+void *omap_usb_pci_alloc_consistent(struct pci_dev *hwdev, 
+				    size_t size, dma_addr_t *handle)
+{
+	void *ret;
+	dma_addr_t lb_handle;
+	
+	ret = pci_alloc_consistent(hwdev, size, handle);
+	lb_handle = phys_to_lb(*handle);
+	*handle = lb_handle;
+	return ret;
+}
+
+void omap_usb_pci_free_consistent(struct pci_dev *hwdev, 
+				  size_t size, void *vaddr,
+				  dma_addr_t dma_handle)
+{
+	pci_free_consistent(hwdev, size, vaddr, lb_to_phys(dma_handle));
+	return;
+}
+
+/*
+ * The following is a copy of drivers/pci/pci.c with everything except the pool 
+ * allocator deleted.  We need the pool allocator for the usb-ohci driver, and 
+ * since the OMAP doesn't have a PCI bus the file drivers/pci/pci.c doesn't 
+ * get built on the OMAP.  Duplicating the pool allocator code here obviously 
+ * isn't the ideal approach, but for now it avoids having to reorganize  
+ * the generic PCI code.  The only modifications made to following code were to 
+ * replace pci_alloc_consistent/pci_free_consistent with 
+ * omap_usb_pci_alloc_consistent/omap_usb_pci_free_consistent.  --JAL
+ */
+ 
+/*
+ * Pool allocator ... wraps the pci_alloc_consistent page allocator, so
+ * small blocks are easily used by drivers for bus mastering controllers.
+ * This should probably be sharing the guts of the slab allocator.
+ */
+
+struct pci_pool {	/* the pool */
+	struct list_head	page_list;
+	spinlock_t		lock;
+	size_t			blocks_per_page;
+	size_t			size;
+	int			flags;
+	struct pci_dev		*dev;
+	size_t			allocation;
+	char			name [32];
+	wait_queue_head_t	waitq;
+};
+
+struct pci_page {	/* cacheable header for 'allocation' bytes */
+	struct list_head	page_list;
+	void			*vaddr;
+	dma_addr_t		dma;
+	unsigned long		bitmap [0];
+};
+
+#define	POOL_TIMEOUT_JIFFIES	((100 /* msec */ * HZ) / 1000)
+#define	POOL_POISON_BYTE	0xa7
+
+// #define CONFIG_PCIPOOL_DEBUG
+
+
+/**
+ * pci_pool_create - Creates a pool of pci consistent memory blocks, for dma.
+ * @name: name of pool, for diagnostics
+ * @pdev: pci device that will be doing the DMA
+ * @size: size of the blocks in this pool.
+ * @align: alignment requirement for blocks; must be a power of two
+ * @allocation: returned blocks won't cross this boundary (or zero)
+ * @flags: SLAB_* flags (not all are supported).
+ *
+ * Returns a pci allocation pool with the requested characteristics, or
+ * null if one can't be created.  Given one of these pools, pci_pool_alloc()
+ * may be used to allocate memory.  Such memory will all have "consistent"
+ * DMA mappings, accessible by the device and its driver without using
+ * cache flushing primitives.  The actual size of blocks allocated may be
+ * larger than requested because of alignment.
+ *
+ * If allocation is nonzero, objects returned from pci_pool_alloc() won't
+ * cross that size boundary.  This is useful for devices which have
+ * addressing restrictions on individual DMA transfers, such as not crossing
+ * boundaries of 4KBytes.
+ */
+struct pci_pool *
+pci_pool_create (const char *name, struct pci_dev *pdev,
+	size_t size, size_t align, size_t allocation, int flags)
+{
+	struct pci_pool		*retval;
+
+	if (align == 0)
+		align = 1;
+	if (size == 0)
+		return 0;
+	else if (size < align)
+		size = align;
+	else if ((size % align) != 0) {
+		size += align + 1;
+		size &= ~(align - 1);
+	}
+
+	if (allocation == 0) {
+		if (PAGE_SIZE < size)
+			allocation = size;
+		else
+			allocation = PAGE_SIZE;
+		// FIXME: round up for less fragmentation
+	} else if (allocation < size)
+		return 0;
+
+	if (!(retval = kmalloc (sizeof *retval, flags)))
+		return retval;
+
+#ifdef	CONFIG_PCIPOOL_DEBUG
+	flags |= SLAB_POISON;
+#endif
+
+	strncpy (retval->name, name, sizeof retval->name);
+	retval->name [sizeof retval->name - 1] = 0;
+
+	retval->dev = pdev;
+	INIT_LIST_HEAD (&retval->page_list);
+	spin_lock_init (&retval->lock);
+	retval->size = size;
+	retval->flags = flags;
+	retval->allocation = allocation;
+	retval->blocks_per_page = allocation / size;
+	init_waitqueue_head (&retval->waitq);
+
+#ifdef CONFIG_PCIPOOL_DEBUG
+	printk (KERN_DEBUG "pcipool create %s/%s size %d, %d/page (%d alloc)\n",
+		pdev ? pdev->slot_name : NULL, retval->name, size,
+		retval->blocks_per_page, allocation);
+#endif
+
+	return retval;
+}
+
+
+static struct pci_page *
+pool_alloc_page (struct pci_pool *pool, int mem_flags)
+{
+	struct pci_page	*page;
+	int		mapsize;
+
+	mapsize = pool->blocks_per_page;
+	mapsize = (mapsize + BITS_PER_LONG - 1) / BITS_PER_LONG;
+	mapsize *= sizeof (long);
+
+	page = (struct pci_page *) kmalloc (mapsize + sizeof *page, mem_flags);
+	if (!page)
+		return 0;
+	page->vaddr = omap_usb_pci_alloc_consistent (pool->dev,
+						     pool->allocation,
+						     &page->dma);
+	if (page->vaddr) {
+		memset (page->bitmap, 0xff, mapsize);	// bit set == free
+		if (pool->flags & SLAB_POISON)
+			memset (page->vaddr, POOL_POISON_BYTE, pool->allocation);
+		list_add (&page->page_list, &pool->page_list);
+	} else {
+		kfree (page);
+		page = 0;
+	}
+	return page;
+}
+
+
+static inline int
+is_page_busy (int blocks, unsigned long *bitmap)
+{
+	while (blocks > 0) {
+		if (*bitmap++ != ~0UL)
+			return 1;
+		blocks -= BITS_PER_LONG;
+	}
+	return 0;
+}
+
+static void
+pool_free_page (struct pci_pool *pool, struct pci_page *page)
+{
+	dma_addr_t	dma = page->dma;
+
+	if (pool->flags & SLAB_POISON)
+		memset (page->vaddr, POOL_POISON_BYTE, pool->allocation);
+	omap_usb_pci_free_consistent (pool->dev, pool->allocation, 
+				      page->vaddr, dma);
+	list_del (&page->page_list);
+	kfree (page);
+}
+
+
+/**
+ * pci_pool_destroy - destroys a pool of pci memory blocks.
+ * @pool: pci pool that will be destroyed
+ *
+ * Caller guarantees that no more memory from the pool is in use,
+ * and that nothing will try to use the pool after this call.
+ */
+void
+pci_pool_destroy (struct pci_pool *pool)
+{
+	unsigned long		flags;
+
+#ifdef CONFIG_PCIPOOL_DEBUG
+	printk (KERN_DEBUG "pcipool destroy %s/%s\n",
+		pool->dev ? pool->dev->slot_name : NULL,
+		pool->name);
+#endif
+
+	spin_lock_irqsave (&pool->lock, flags);
+	while (!list_empty (&pool->page_list)) {
+		struct pci_page		*page;
+		page = list_entry (pool->page_list.next,
+				struct pci_page, page_list);
+		if (is_page_busy (pool->blocks_per_page, page->bitmap)) {
+			printk (KERN_ERR "pci_pool_destroy %s/%s, %p busy\n",
+				pool->dev ? pool->dev->slot_name : NULL,
+				pool->name, page->vaddr);
+			/* leak the still-in-use consistent memory */
+			list_del (&page->page_list);
+			kfree (page);
+		} else
+			pool_free_page (pool, page);
+	}
+	spin_unlock_irqrestore (&pool->lock, flags);
+	kfree (pool);
+}
+
+
+/**
+ * pci_pool_alloc - get a block of consistent memory
+ * @pool: pci pool that will produce the block
+ * @mem_flags: SLAB_KERNEL or SLAB_ATOMIC
+ * @handle: pointer to dma address of block
+ *
+ * This returns the kernel virtual address of a currently unused block,
+ * and reports its dma address through the handle.
+ * If such a memory block can't be allocated, null is returned.
+ */
+void *
+pci_pool_alloc (struct pci_pool *pool, int mem_flags, dma_addr_t *handle)
+{
+	unsigned long		flags;
+	struct list_head	*entry;
+	struct pci_page		*page;
+	int			map, block;
+	size_t			offset;
+	void			*retval;
+
+restart:
+	spin_lock_irqsave (&pool->lock, flags);
+	list_for_each (entry, &pool->page_list) {
+		int		i;
+		page = list_entry (entry, struct pci_page, page_list);
+		/* only cachable accesses here ... */
+		for (map = 0, i = 0;
+				i < pool->blocks_per_page;
+				i += BITS_PER_LONG, map++) {
+			if (page->bitmap [map] == 0)
+				continue;
+			block = ffz (~ page->bitmap [map]);
+			if ((i + block) < pool->blocks_per_page) {
+				clear_bit (block, &page->bitmap [map]);
+				offset = (BITS_PER_LONG * map) + block;
+				offset *= pool->size;
+				goto ready;
+			}
+		}
+	}
+	if (!(page = pool_alloc_page (pool, mem_flags))) {
+		if (mem_flags == SLAB_KERNEL) {
+			DECLARE_WAITQUEUE (wait, current);
+
+			current->state = TASK_INTERRUPTIBLE;
+			add_wait_queue (&pool->waitq, &wait);
+			spin_unlock_irqrestore (&pool->lock, flags);
+
+			schedule_timeout (POOL_TIMEOUT_JIFFIES);
+
+			current->state = TASK_RUNNING;
+			remove_wait_queue (&pool->waitq, &wait);
+			goto restart;
+		}
+		retval = 0;
+		goto done;
+	}
+
+	clear_bit (0, &page->bitmap [0]);
+	offset = 0;
+ready:
+	retval = offset + page->vaddr;
+	*handle = offset + page->dma;
+done:
+	spin_unlock_irqrestore (&pool->lock, flags);
+	return retval;
+}
+
+
+static struct pci_page *
+pool_find_page (struct pci_pool *pool, dma_addr_t dma)
+{
+	unsigned long		flags;
+	struct list_head	*entry;
+	struct pci_page		*page;
+
+	spin_lock_irqsave (&pool->lock, flags);
+	list_for_each (entry, &pool->page_list) {
+		page = list_entry (entry, struct pci_page, page_list);
+		if (dma < page->dma)
+			continue;
+		if (dma < (page->dma + pool->allocation))
+			goto done;
+	}
+	page = 0;
+done:
+	spin_unlock_irqrestore (&pool->lock, flags);
+	return page;
+}
+
+
+/**
+ * pci_pool_free - put block back into pci pool
+ * @pool: the pci pool holding the block
+ * @vaddr: virtual address of block
+ * @dma: dma address of block
+ *
+ * Caller promises neither device nor driver will again touch this block
+ * unless it is first re-allocated.
+ */
+void
+pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t dma)
+{
+	struct pci_page		*page;
+	unsigned long		flags;
+	int			map, block;
+
+	if ((page = pool_find_page (pool, dma)) == 0) {
+		printk (KERN_ERR "pci_pool_free %s/%s, %p/%x (bad dma)\n",
+			pool->dev ? pool->dev->slot_name : NULL,
+			pool->name, vaddr, (int) (dma & 0xffffffff));
+		return;
+	}
+#ifdef	CONFIG_PCIPOOL_DEBUG
+	if (((dma - page->dma) + (void *)page->vaddr) != vaddr) {
+		printk (KERN_ERR "pci_pool_free %s/%s, %p (bad vaddr)/%x\n",
+			pool->dev ? pool->dev->slot_name : NULL,
+			pool->name, vaddr, (int) (dma & 0xffffffff));
+		return;
+	}
+#endif
+
+	block = dma - page->dma;
+	block /= pool->size;
+	map = block / BITS_PER_LONG;
+	block %= BITS_PER_LONG;
+
+#ifdef	CONFIG_PCIPOOL_DEBUG
+	if (page->bitmap [map] & (1UL << block)) {
+		printk (KERN_ERR "pci_pool_free %s/%s, dma %x already free\n",
+			pool->dev ? pool->dev->slot_name : NULL,
+			pool->name, dma);
+		return;
+	}
+#endif
+	if (pool->flags & SLAB_POISON)
+		memset (vaddr, POOL_POISON_BYTE, pool->size);
+
+	spin_lock_irqsave (&pool->lock, flags);
+	set_bit (block, &page->bitmap [map]);
+	if (waitqueue_active (&pool->waitq))
+		wake_up (&pool->waitq);
+	/*
+	 * Resist a temptation to do
+	 *    if (!is_page_busy(bpp, page->bitmap)) pool_free_page(pool, page);
+	 * it is not interrupt safe. Better have empty pages hang around.
+	 */
+	spin_unlock_irqrestore (&pool->lock, flags);
+}
+
+/* Pool allocator */
+
+EXPORT_SYMBOL (pci_pool_create);
+EXPORT_SYMBOL (pci_pool_destroy);
+EXPORT_SYMBOL (pci_pool_alloc);
+EXPORT_SYMBOL (pci_pool_free);
+EXPORT_SYMBOL (omap_usb_pci_alloc_consistent);
+EXPORT_SYMBOL (omap_usb_pci_free_consistent);
+
+MODULE_LICENSE("GPL");
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/usb/usb-ohci.c linux-2.4.19/drivers/usb/usb-ohci.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/usb/usb-ohci.c	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/usb/usb-ohci.c	2003-01-09 19:49:04.000000000 +0200
@@ -77,7 +77,15 @@
 // #define OHCI_VERBOSE_DEBUG	/* not always helpful */
 
 #include "usb-ohci.h"
-
+#ifdef CONFIG_USB_OHCI_OMAP1510
+extern void *omap_usb_pci_alloc_consistent(struct pci_dev *hwdev, 
+					   size_t size, dma_addr_t *handle);
+extern void omap_usb_pci_free_consistent(struct pci_dev *hwdev, 
+					 size_t size, void *vaddr,
+					 dma_addr_t dma_handle);
+#define pci_alloc_consistent omap_usb_pci_alloc_consistent
+#define pci_free_consistent omap_usb_pci_free_consistent
+#endif
 
 /*
  * Version Information
@@ -1509,7 +1517,8 @@
 /* replies to the request have to be on a FIFO basis so
  * we reverse the reversed done-list */
  
-static td_t * dl_reverse_done_list (ohci_t * ohci)
+//static td_t * dl_reverse_done_list (ohci_t * ohci)
+td_t * dl_reverse_done_list (ohci_t * ohci)
 {
 	__u32 td_list_hc;
 	td_t * td_rev = NULL;
@@ -1657,7 +1666,8 @@
 
 /* td done list */
 
-static void dl_done_list (ohci_t * ohci, td_t * td_list)
+//static void dl_done_list (ohci_t * ohci, td_t * td_list)
+void dl_done_list (ohci_t * ohci, td_t * td_list)
 {
   	td_t * td_list_next = NULL;
 	ed_t * ed;
@@ -2126,7 +2136,8 @@
 
 /* reset the HC and BUS */
 
-static int hc_reset (ohci_t * ohci)
+//static int hc_reset (ohci_t * ohci)
+int hc_reset (ohci_t * ohci)
 {
 	int timeout = 30;
 	int smm_timeout = 50; /* 0,5 sec */
@@ -2171,7 +2182,8 @@
  * enable interrupts 
  * connect the virtual root hub */
 
-static int hc_start (ohci_t * ohci)
+//static int hc_start (ohci_t * ohci)
+int hc_start (ohci_t * ohci)
 {
   	__u32 mask;
   	unsigned int fminterval;
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/usb/usb-ohci-omap1510.c linux-2.4.19/drivers/usb/usb-ohci-omap1510.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/usb/usb-ohci-omap1510.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/usb/usb-ohci-omap1510.c	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,127 @@
+/*
+ *  linux/drivers/usb/usb-ohci-omap1510.c
+ *
+ *  The outline of this code was taken from Brad Parkers <brad@heeltoe.com>
+ *  original OHCI driver modifications, and reworked into a cleaner form
+ *  by Russell King <rmk@arm.linux.org.uk>.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/pci.h>	/* for pci_pool_* prototypes */
+#include <linux/usb.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include "usb-ohci.h"
+
+#define OMAP1510_LB_OFFSET (0x30000000UL)
+
+int __devinit
+hc_add_ohci(struct pci_dev *dev, int irq, void *membase, unsigned long flags,
+	    ohci_t **ohci, const char *name, const char *slot_name);
+extern void hc_remove_ohci(ohci_t *ohci);
+
+static ohci_t *omap1510_ohci;
+
+static void __init omap1510_ohci_configure(void)
+{
+	/* TO DO:  make a proper header file for all of these registers. */
+	volatile unsigned char *fpga_usb_host_ctrl = (unsigned char *) 0xe800020c;
+
+	volatile unsigned short *apll_ctrl_reg  = (unsigned short *) 0xfffe084c;
+	volatile unsigned short *dpll_ctrl_reg  = (unsigned short *) 0xfffe083c;
+	volatile unsigned short *soft_req_reg   = (unsigned short *) 0xfffe0834;
+	volatile unsigned short *clock_ctrl_reg = (unsigned short *) 0xfffe0830;
+	volatile unsigned long *mod_conf_ctrl_0 = (unsigned long *)  0xfffe1080;
+
+	volatile unsigned long *lb_clock_div       = (unsigned long *)  0xfffec10c;
+	volatile unsigned short *lb_mmu_cntl_reg   = (unsigned short *) 0xfffec208;
+	volatile unsigned short *lb_mmu_lock_reg   = (unsigned short *) 0xfffec224;
+	volatile unsigned short *lb_mmu_ld_tlb_reg = (unsigned short *) 0xfffec228;
+	volatile unsigned short *lb_mmu_cam_h_reg  = (unsigned short *) 0xfffec22c;
+	volatile unsigned short *lb_mmu_cam_l_reg  = (unsigned short *) 0xfffec230;
+	volatile unsigned short *lb_mmu_ram_h_reg  = (unsigned short *) 0xfffec234;
+	volatile unsigned short *lb_mmu_ram_l_reg  = (unsigned short *) 0xfffec238;
+	int tlb;
+	unsigned long lbaddr, physaddr;
+
+	*lb_clock_div = (*lb_clock_div & 0xfffffff8) | 0x4;
+	*lb_mmu_cntl_reg = 0x1;
+	for (tlb = 0; tlb < 32; tlb++) {
+		lbaddr   = tlb * 0x00100000 + OMAP1510_LB_OFFSET;
+		physaddr = tlb * 0x00100000 + PHYS_OFFSET;
+		*lb_mmu_cam_h_reg = (lbaddr & 0x0fffffff) >> 22;
+		*lb_mmu_cam_l_reg = ((lbaddr & 0x003ffc00) >> 6) | 0xc;
+		*lb_mmu_ram_h_reg = physaddr >> 16;
+		*lb_mmu_ram_l_reg = (physaddr & 0x0000fc00) | 0x300;
+		*lb_mmu_lock_reg = tlb << 4;
+		*lb_mmu_ld_tlb_reg = 0x1;
+	}
+	*lb_mmu_cntl_reg = 0x3;
+
+#define APLL_CTRL_REG_APLL_NDPLL_SWITCH		0x0001
+#define DPLL_CTRL_REG_PLL_ENABLE		0x0010
+#define DPLL_CTRL_REG_LOCK			0x0001
+#define SOFT_REQ_REG_DPLL_REQ			0x0001
+#define CLOCK_CTRL_REG_USB_MCLK_EN		0x0010
+#define MOD_CONF_CTRL_0_USB_HOST_HHC_UHOST_EN	0x00000200
+
+	*apll_ctrl_reg &= ~APLL_CTRL_REG_APLL_NDPLL_SWITCH;
+	*dpll_ctrl_reg |= DPLL_CTRL_REG_PLL_ENABLE;
+	*soft_req_reg |= SOFT_REQ_REG_DPLL_REQ;
+	while(!(*dpll_ctrl_reg & DPLL_CTRL_REG_LOCK));
+	*clock_ctrl_reg |= CLOCK_CTRL_REG_USB_MCLK_EN;
+	*ARM_IDLECT2 |= (1 << EN_LBFREECK) | (1 << EN_LBCK);
+	*mod_conf_ctrl_0 |= MOD_CONF_CTRL_0_USB_HOST_HHC_UHOST_EN;
+
+	*fpga_usb_host_ctrl |= 0x20;
+
+	udelay(200);
+}
+
+static int __init omap1510_ohci_init(void)
+{
+	int ret;
+	/*
+	 * Request memory resources.
+	 */
+//	if (!request_mem_region(_USB_OHCI_OP_BASE, _USB_EXTENT, "usb-ohci"))
+//		return -EBUSY;
+
+	omap1510_ohci_configure();
+
+	/*
+	 * Initialise the generic OHCI driver.
+	 */
+	ret = hc_add_ohci((struct pci_dev *)1, IH2_BASE + 6,
+			  (void *)0xfffba000, 0, &omap1510_ohci,
+			  "usb-ohci", "omap1510");
+
+//	if (ret)
+//		release_mem_region(_USB_OHCI_OP_BASE, _USB_EXTENT);
+
+	return ret;
+}
+
+static void __exit omap1510_ohci_exit(void)
+{
+	volatile unsigned long *mod_conf_ctrl_0 = (unsigned long *)  0xfffe1080;
+
+	hc_remove_ohci(omap1510_ohci);
+
+	*mod_conf_ctrl_0 &= ~MOD_CONF_CTRL_0_USB_HOST_HHC_UHOST_EN;
+
+	/*
+	 * Release memory resources.
+	 */
+//	release_mem_region(_USB_OHCI_OP_BASE, _USB_EXTENT);
+}
+
+module_init(omap1510_ohci_init);
+module_exit(omap1510_ohci_exit);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/Config.in linux-2.4.19/drivers/video/Config.in
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/Config.in	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/video/Config.in	2003-01-09 19:49:04.000000000 +0200
@@ -45,6 +45,10 @@
      if [ "$CONFIG_FB_SA1100" = "y" -a "$CONFIG_SA1100_CERF_CPLD" = "y" ]; then
        bool 'Cerfboard Backlight (CerfPDA)' CONFIG_SA1100_CERF_LCD_BACKLIGHT
      fi
+     if [ "$CONFIG_ARCH_OMAP" = "y" ]; then
+        tristate 'OMAP Framebuffer Driver' CONFIG_FB_OMAP
+        dep_bool 'OMAP Framebuffer in SDRAM (default is SRAM)' CONFIG_FB_SDRAM $CONFIG_FB_OMAP n
+     fi
    fi
    dep_tristate '  CyberPro 2000/2010/5000 support' CONFIG_FB_CYBER2000 $CONFIG_PCI
    if [ "$CONFIG_APOLLO" = "y" ]; then
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/cyberfb.c linux-2.4.19/drivers/video/cyberfb.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/cyberfb.c	2001-11-15 00:52:20.000000000 +0200
+++ linux-2.4.19/drivers/video/cyberfb.c	2003-01-09 18:15:22.000000000 +0200
@@ -33,6 +33,9 @@
 *   - 05 Jan 96: Geert: integration into the current source tree
 *   - 01 Aug 98: Alan: Merge in code from cvision.c and cvision_core.c
 * $Log: cyberfb.c,v $
+* Revision 1.2  2003/01/09 16:15:22  tmlind
+* Imported 2.4.19-rmk4 patch
+*
 * Revision 1.6  1998/09/11 04:54:58  abair
 * Update for 2.1.120 change in include file location.
 * Clean up for public release.
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/Makefile linux-2.4.19/drivers/video/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/Makefile	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/drivers/video/Makefile	2003-01-09 19:49:04.000000000 +0200
@@ -110,6 +110,11 @@
 obj-y				  += aty/atyfb.o
 endif
 
+subdir-$(CONFIG_FB_OMAP)	  += omap
+ifeq ($(CONFIG_FB_OMAP),y)
+obj-y				  += omap/omapfb.o
+endif
+
 obj-$(CONFIG_FB_SUN3)             += sun3fb.o
 obj-$(CONFIG_FB_BWTWO)            += bwtwofb.o
 obj-$(CONFIG_FB_HGA)              += hgafb.o  
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/innovator.h linux-2.4.19/drivers/video/omap/innovator.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/innovator.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/innovator.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,461 @@
+/*
+ * File: fb_omap1510.h
+ *
+ * This file is the header file for the omap1510 framebuffer.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. 
+ * Author: Alex McMains <aam@ridgerun.com> 2001/09/20
+ *         Greg Lonnon <glonnon@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs and problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#ifndef _fb_omap1510_h_
+#define _fb_omap1510_h_
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/ck.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#define NUM_XPIXELS 240
+#define NUM_YPIXELS 320
+
+#define COLOR_16BIT
+
+#ifdef COLOR_16BIT
+#define BPP 16
+#define PALETTE_SIZE 32
+#define BPP_MASK 0x4000
+#else
+#define BPP 8
+#define PALETTE_SIZE 512
+#define BPP_MASK 0x3000
+#endif
+
+#define MAX_FRAMEBUFFER_SIZE (((NUM_XPIXELS) * (NUM_YPIXELS) * (BPP)/8) + \
+                              (PALETTE_SIZE) + PAGE_SIZE)
+
+// Put the framebuffer at top of SRAM
+#if	0
+/*  REVISIT: Caveat Emptor: Whatever value we use, it _must_ be page
+ *  aligned. For now, just use the (currently page aligned) default
+ *  define from <asm/hardware.h>.
+ */
+#undef SRAM_FRAMEBUFFER_MEMORY
+#define SRAM_FRAMEBUFFER_MEMORY PAGE_ALIGN(OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - MAX_FRAMEBUFFER_SIZE - 8192)
+#endif
+
+// we use this to check for valid displays in set_var
+struct _displays 
+{
+        int xres;
+        int yres;
+        int bpp;
+};
+static struct _displays displays_supported[] = { {NUM_XPIXELS, NUM_YPIXELS, 16} };
+
+static struct fb_var_screeninfo tifb_default8 = 
+{
+        xres: NUM_XPIXELS, 
+        yres: NUM_YPIXELS, 
+        xres_virtual: NUM_XPIXELS, 
+        yres_virtual: NUM_YPIXELS, 
+        xoffset: 0, 
+        yoffset: 0, 
+        bits_per_pixel: 8, 
+        grayscale : 0,
+        red: {0, 8, 0}, 
+        green: {0, 8, 0}, 
+        blue: {0, 8, 0}, 
+        transp: {0, 0, 0},
+        nonstd: 0, 
+        activate: 0, 
+        height: -1, 
+        width: -1, 
+        accel_flags: 0, 
+        pixclock: 171521, 
+        left_margin: 64, 
+        right_margin: 64, 
+        upper_margin: 32, 
+        lower_margin: 32,
+        hsync_len : 64, 
+        vsync_len: 2,
+        sync: 0, 
+        vmode: FB_VMODE_NONINTERLACED
+};
+
+static struct fb_var_screeninfo tifb_default16 = 
+{
+        xres: NUM_XPIXELS, 
+        yres: NUM_YPIXELS, 
+        xres_virtual: NUM_XPIXELS, 
+        yres_virtual: NUM_YPIXELS, 
+        xoffset: 0, 
+        yoffset: 0, 
+        bits_per_pixel: 16, 
+        grayscale : 0,
+        red: {11, 5, 0}, 
+        green: {5, 6, 0}, 
+        blue: {0, 5, 0}, 
+        transp: {0, 0, 0},
+        nonstd: 0, 
+        activate: 0, 
+        height: -1, 
+        width: -1, 
+        accel_flags: 0, 
+        pixclock: 171521, 
+        left_margin: 64, 
+        right_margin: 64, 
+        upper_margin: 32, 
+        lower_margin: 32,
+        hsync_len : 64, 
+        vsync_len: 2,
+        sync: 0, 
+        vmode: FB_VMODE_NONINTERLACED
+};
+
+static inline void hardware_enable(void)
+{
+        // initialize LCD
+        fpga_write(0x7, OMAP1510P1_FPGA_LCD_PANEL_CONTROL);
+
+        /* 
+           According to the errata, if the framebuffer is in SDRAM, the max clock
+           is 1/2 the TC clock rate.  If the framebuffer is in SRAM, the max clock is
+           = the TC clock rate.
+        */
+        ck_set_rate(lcd_ck, (ck_get_rate(tc_ck) / 2));
+        ck_enable(lcd_ck);
+        
+}
+
+static inline void hardware_disable(void)
+{
+        // stop LCD
+        fpga_write(0x0, OMAP1510P1_FPGA_LCD_PANEL_CONTROL);
+        ck_disable(lcd_ck);        
+}
+
+static inline int lcd_active(void)
+{
+    // Return true if LCD controller is running.
+    return(LCD_READ(TI925_LCD_CONTROL) & 1);
+}
+
+static inline void lcd_enable(void)
+{
+        unsigned long value;
+
+        // enable the LCD
+        value = LCD_READ(TI925_LCD_CONTROL);
+        value |= 1;
+        LCD_WRITE(value,TI925_LCD_CONTROL);
+}
+
+static inline void lcd_disable(void)
+{
+        unsigned long value;
+
+        // enable the LCD
+        value = LCD_READ(TI925_LCD_CONTROL);
+        value &= ~1;
+        LCD_WRITE(value,TI925_LCD_CONTROL);
+
+        // Wait until current frame finished.
+        //  Poll on LCDStatus[Done] bit.
+        while (LCD_READ(TI925_LCD_STATUS) & 0x1);
+}
+
+static inline void orl(unsigned long val, unsigned long reg) 
+{
+        outl((inl(reg) | val),reg);
+}
+
+static inline unsigned long omap1510_dma_reg_addr(int global, int chan, int reg) 
+{ 
+        return (OMAP1510_DMA_BASE + (global << 10) + (chan << 6) + (reg << 1));
+}
+
+static inline void lcd_write_top_address(unsigned long addr) 
+{
+        unsigned long reg;
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_U);
+
+        DBG(__FUNCTION__ "\n%lux %lux\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_L);
+
+        DBG("%lux %lux\n", reg, addr & 0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+}
+
+static inline void lcd_write_bottom_address(unsigned long addr) 
+{
+        unsigned long reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL, 
+                                                  DMA_LCD_BOT_F1_U);
+
+        DBG(__FUNCTION__ "\n%lux %lux\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                    LCD_CHANNEL, DMA_LCD_BOT_F1_L);
+
+        DBG("%lux %lux\n", reg, addr&0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+}
+
+static inline void lcd_dma_enable(void) 
+{
+        unsigned long reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL,
+                                                  DMA_LCD_CTRL);
+        DBG("%lux\n",reg);
+
+#if 0
+        /*
+          Nope.  The LCD doesn't get to set global DMA state.  SKJ
+        */
+        reg = omap1510_dma_reg_addr(GLOBAL_DMA_ACCESS, 0, 0);
+        outw((1<<2),reg);  // dma is free running ????
+        DBG("wrote %lux %lux\n",reg,inl(reg));
+#endif
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,LCD_CHANNEL,
+                                    DMA_LCD_CTRL);
+#if CONFIG_FB_SDRAM
+        outw((LCD_BUS_ERROR_IT_IE),reg);
+#else
+        outw((LCD_BUS_ERROR_IT_IE | LCD_SOURCE_IMIF),reg);
+#endif
+        DBG("wrote %lux %lux\n",reg,inl(reg));
+}
+
+#ifdef FB_DEBUG 
+static inline void print_lcd_regs(void)
+{
+	DBG(__FUNCTION__ "\n");
+
+	DBG("control: %8.8x status %8.8x timing0 %8.8x" 
+	     " timing1 %8.8x timing2 %8.8x\n", 
+	     (int)LCD_READ(TI925_LCD_CONTROL), 
+	     (int)LCD_READ(TI925_LCD_STATUS),
+	     (int)LCD_READ(TI925_LCD_TIMING0),
+	     (int)LCD_READ(TI925_LCD_TIMING1),
+	     (int)LCD_READ(TI925_LCD_TIMING2));
+
+#ifdef CONFIG_OMAP_INNOVATOR
+        DBG("lcd register %lux power %lux\n", inb(0xe8000002),
+            inb(0xe8000005) );
+#else
+        DBG("lcd register %lux power %lux fpga %lux\n", inb(0xe8000002),
+            inb(0xe8000005), inw(0xe97ffffe));
+#endif
+}
+#else
+static inline void print_lcd_regs(void) {}
+#endif
+
+static void tifb_init_dma(void)
+{
+        int size = current_par.palette_size + current_par.screen_size;
+
+        lcd_write_top_address((unsigned long) current_par.p_palette_base);
+        lcd_write_bottom_address((unsigned long)current_par.p_palette_base + 
+                                 size - 2);
+        lcd_dma_enable();
+
+        DBG(__FUNCTION__ " size=%d\n", size);
+        DBG(__FUNCTION__ " base=%lux\n", current_par.p_palette_base);
+        DBG(__FUNCTION__ " end=%lux\n", current_par.p_palette_base + size - 2);
+        print_lcd_regs();
+}
+
+static void __init tifb_init_registers(void)
+{
+        unsigned long value;
+        DBG(__FUNCTION__ "\n");
+
+        hardware_enable();
+
+        // setup the LCD Control
+        value = 0;
+        value |= (0<<12); // FDD to 16 wait cycles
+        value |= (1<<3);  // turn on the done mask
+        value |= (1<<9);
+        value |= (1<<7);  // tft
+
+        value = 0xcec;
+        LCD_WRITE(value, TI925_LCD_CONTROL);
+
+        // setup the Timing0
+        value = NUM_XPIXELS -1; // current_par.xres -1;
+        value |= ((4-1)<<10);   // HSW width for LCD is 4-1
+        value |= ((4-1)<<16);   // H Front Porch is 4-1
+        value |= ((40-1)<<24);  // H Back Porch is 40-1
+
+        //value = 0x27030cef;  This is what the above should equal
+        LCD_WRITE(value, TI925_LCD_TIMING0);
+
+        // setup the Timing1
+        value = NUM_YPIXELS -1; //current_par.yres - 1;
+        value |= (2 << 10);     // VSW width for the LCD is 2
+        value |= (2 << 16);     // Front Porch is 2
+        value |= (8 << 24);     // Back Porch is 8
+
+        //value = 0x0802093f;  This is what the above should equal
+        LCD_WRITE(value, TI925_LCD_TIMING1);
+
+        // setup the Timing2
+        //value = 2;           //  PCD 
+        //value |= (255 << 8); // ACB 
+        //value |= (0 << 16);  // ACBI this should be disabled
+        //value |= (0 << 20);  // IVS 
+        //value |= (0 << 21);  // IHS
+        //value |= (0 << 22);  // IPC
+        //value |= (0 << 23);  // IEO
+
+        value = 0x00300004;
+        LCD_WRITE(value, TI925_LCD_TIMING2);
+
+        // setup dma
+        tifb_init_dma();
+        print_lcd_regs();
+
+        lcd_enable();
+
+	/* REVISIT: This is req'd to get LCD DMA to free run. */
+        ck_disable(dma_ck);
+}
+
+static void lcd_dma_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+        unsigned long status = inw(omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                         LCD_CHANNEL,
+                                                         DMA_LCD_CTRL));
+        if ( status & (1<<5) )
+                printk("LCD DMA bus error");
+
+        if ( status & (1<<4) )
+                printk("LCD DMA end of frame 2");
+
+        if ( status & (1<<3) )
+                printk("LCD DMA end of frame 1");
+}
+ 
+static void lcd_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+	unsigned long status;
+	int reset = 0;
+	static int abc = 0;
+	static int fuf = 0;
+	static int sync = 0;
+	static int done = 0;
+
+	DBG(__FUNCTION__ "\n");
+	
+	status = LCD_READ(TI925_LCD_STATUS);
+	
+	if ( status & (1<<3) ) 
+        {
+		DBG("ABC interrupt");
+
+		status &= (1<<3);
+		LCD_WRITE(status,TI925_LCD_STATUS);
+		abc++;
+	}
+	
+	if ( status & (1<<5) ) 
+        {
+		DBG("FUF interrupt");
+
+		reset = 1;
+		fuf++;
+	}
+
+	if ( status & (1<<2) ) 
+        {
+		DBG("synch interrupt");
+
+		reset = 1;
+		sync++;
+	}
+
+	if ( status & (1<<0) ) 
+        {
+		DBG("DONE interrupt");
+
+		reset = 1;
+		done++;
+	}
+
+	if ( (sync % 1024) == 0 ) 
+        {
+		DBG(" abc %d fuf %d sync %d done %d\n",abc, fuf, sync, done);
+		print_lcd_regs();     
+	}
+
+	if ( reset ) 
+        {
+		// This will clear the error condition and restart the LCD
+		unsigned long control;
+
+		control = inl(IO_ADDRESS(TI925_LCD_CONTROL));
+		control &= ~(1<<0);
+		outl(control, IO_ADDRESS(TI925_LCD_CONTROL));
+		control = inl(IO_ADDRESS(TI925_LCD_CONTROL));
+		control |= (1<<0);
+		outl(control, IO_ADDRESS(TI925_LCD_CONTROL));
+	}
+}
+
+#endif /* _fb_omap1510_h_ */ 
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/Makefile linux-2.4.19/drivers/video/omap/Makefile
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/Makefile	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/Makefile	2003-01-09 19:50:05.000000000 +0200
@@ -0,0 +1,16 @@
+
+O_TARGET := omapfb.o
+
+# All of the (potential) objects that export symbols.
+# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
+
+export-objs    :=  omapfb.o
+
+# Each configuration option enables a list of files.
+
+obj-$(CONFIG_FB_OMAP)		+= omapfb.o
+
+include $(TOPDIR)/Rules.make
+
+clean:
+	rm -f core *.o *.a *.s
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omap1510.h linux-2.4.19/drivers/video/omap/omap1510.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omap1510.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/omap1510.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,461 @@
+/*
+ * File: fb_omap1510.h
+ *
+ * This file is the header file for the omap1510 framebuffer.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. 
+ * Author: Alex McMains <aam@ridgerun.com> 2001/09/20
+ *         Greg Lonnon <glonnon@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs and problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#ifndef _fb_omap1510_h_
+#define _fb_omap1510_h_
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/ck.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#define NUM_XPIXELS 320
+#define NUM_YPIXELS 240
+
+#define COLOR_16BIT
+
+#ifdef COLOR_16BIT
+#define BPP 16
+#define PALETTE_SIZE 32
+#define BPP_MASK 0x4000
+#else
+#define BPP 8
+#define PALETTE_SIZE 512
+#define BPP_MASK 0x3000
+#endif
+
+#define MAX_FRAMEBUFFER_SIZE (((NUM_XPIXELS) * (NUM_YPIXELS) * (BPP)/8) + \
+                              (PALETTE_SIZE) + PAGE_SIZE)
+
+// Put the framebuffer at top of SRAM
+#if	0
+/*  REVISIT: Caveat Emptor: Whatever value we use, it _must_ be page
+ *  aligned. For now, just use the (currently page aligned) default
+ *  define from <asm/hardware.h>.
+ */
+#undef SRAM_FRAMEBUFFER_MEMORY
+#define SRAM_FRAMEBUFFER_MEMORY PAGE_ALIGN(OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - MAX_FRAMEBUFFER_SIZE - 8192)
+#endif
+
+// we use this to check for valid displays in set_var
+struct _displays 
+{
+        int xres;
+        int yres;
+        int bpp;
+};
+static struct _displays displays_supported[] = { {NUM_XPIXELS, NUM_YPIXELS, 16} };
+
+static struct fb_var_screeninfo tifb_default8 = 
+{
+        xres: NUM_XPIXELS, 
+        yres: NUM_YPIXELS, 
+        xres_virtual: NUM_XPIXELS, 
+        yres_virtual: NUM_YPIXELS, 
+        xoffset: 0, 
+        yoffset: 0, 
+        bits_per_pixel: 8, 
+        grayscale : 0,
+        red: {0, 8, 0}, 
+        green: {0, 8, 0}, 
+        blue: {0, 8, 0}, 
+        transp: {0, 0, 0},
+        nonstd: 0, 
+        activate: 0, 
+        height: -1, 
+        width: -1, 
+        accel_flags: 0, 
+        pixclock: 171521, 
+        left_margin: 64, 
+        right_margin: 64, 
+        upper_margin: 32, 
+        lower_margin: 32,
+        hsync_len : 64, 
+        vsync_len: 2,
+        sync: 0, 
+        vmode: FB_VMODE_NONINTERLACED
+};
+
+static struct fb_var_screeninfo tifb_default16 = 
+{
+        xres: NUM_XPIXELS, 
+        yres: NUM_YPIXELS, 
+        xres_virtual: NUM_XPIXELS, 
+        yres_virtual: NUM_YPIXELS, 
+        xoffset: 0, 
+        yoffset: 0, 
+        bits_per_pixel: 16, 
+        grayscale : 0,
+        red: {11, 5, 0}, 
+        green: {5, 6, 0}, 
+        blue: {0, 5, 0}, 
+        transp: {0, 0, 0},
+        nonstd: 0, 
+        activate: 0, 
+        height: -1, 
+        width: -1, 
+        accel_flags: 0, 
+        pixclock: 171521, 
+        left_margin: 64, 
+        right_margin: 64, 
+        upper_margin: 32, 
+        lower_margin: 32,
+        hsync_len : 64, 
+        vsync_len: 2,
+        sync: 0, 
+        vmode: FB_VMODE_NONINTERLACED
+};
+
+static inline void hardware_enable(void)
+{
+        // initialize LCD
+        fpga_write(0x7, OMAP1510P1_FPGA_LCD_PANEL_CONTROL);
+
+        /* 
+           According to the errata, if the framebuffer is in SDRAM, the max clock
+           is 1/2 the TC clock rate.  If the framebuffer is in SRAM, the max clock is
+           = the TC clock rate.
+        */
+        ck_set_rate(lcd_ck, (ck_get_rate(tc_ck) / 2));
+        ck_enable(lcd_ck);
+        
+}
+
+static inline void hardware_disable(void)
+{
+        // stop LCD
+        fpga_write(0x0, OMAP1510P1_FPGA_LCD_PANEL_CONTROL);
+        ck_disable(lcd_ck);        
+}
+
+static inline int lcd_active(void)
+{
+    // Return true if LCD controller is running.
+    return(LCD_READ(TI925_LCD_CONTROL) & 1);
+}
+
+static inline void lcd_enable(void)
+{
+        unsigned long value;
+
+        // enable the LCD
+        value = LCD_READ(TI925_LCD_CONTROL);
+        value |= 1;
+        LCD_WRITE(value,TI925_LCD_CONTROL);
+}
+
+static inline void lcd_disable(void)
+{
+        unsigned long value;
+
+        // enable the LCD
+        value = LCD_READ(TI925_LCD_CONTROL);
+        value &= ~1;
+        LCD_WRITE(value,TI925_LCD_CONTROL);
+
+        // Wait until current frame finished.
+        //  Poll on LCDStatus[Done] bit.
+        while (LCD_READ(TI925_LCD_STATUS) & 0x1);
+}
+
+static inline void orl(unsigned long val, unsigned long reg) 
+{
+        outl((inl(reg) | val),reg);
+}
+
+static inline unsigned long omap1510_dma_reg_addr(int global, int chan, int reg) 
+{ 
+        return (OMAP1510_DMA_BASE + (global << 10) + (chan << 6) + (reg << 1));
+}
+
+static inline void lcd_write_top_address(unsigned long addr) 
+{
+        unsigned long reg;
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_U);
+
+        DBG(__FUNCTION__ "\n%lux %lux\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_L);
+
+        DBG("%lux %lux\n", reg, addr & 0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+}
+
+static inline void lcd_write_bottom_address(unsigned long addr) 
+{
+        unsigned long reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL, 
+                                                  DMA_LCD_BOT_F1_U);
+
+        DBG(__FUNCTION__ "\n%lux %lux\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                    LCD_CHANNEL, DMA_LCD_BOT_F1_L);
+
+        DBG("%lux %lux\n", reg, addr&0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lux %lux\n", reg, inw(reg));
+}
+
+static inline void lcd_dma_enable(void) 
+{
+        unsigned long reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL,
+                                                  DMA_LCD_CTRL);
+        DBG("%lux\n",reg);
+
+#if 0
+        /*
+          Nope.  The LCD doesn't get to set global DMA state.  SKJ
+        */
+        reg = omap1510_dma_reg_addr(GLOBAL_DMA_ACCESS, 0, 0);
+        outw((1<<2),reg);  // dma is free running ????
+        DBG("wrote %lux %lux\n",reg,inl(reg));
+#endif
+
+        reg = omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,LCD_CHANNEL,
+                                    DMA_LCD_CTRL);
+#if CONFIG_FB_SDRAM
+        outw((LCD_BUS_ERROR_IT_IE),reg);
+#else
+        outw((LCD_BUS_ERROR_IT_IE | LCD_SOURCE_IMIF),reg);
+#endif
+        DBG("wrote %lux %lux\n",reg,inl(reg));
+}
+
+#ifdef FB_DEBUG 
+static inline void print_lcd_regs(void)
+{
+	DBG(__FUNCTION__ "\n");
+
+	DBG("control: %8.8x status %8.8x timing0 %8.8x" 
+	     " timing1 %8.8x timing2 %8.8x\n", 
+	     (int)LCD_READ(TI925_LCD_CONTROL), 
+	     (int)LCD_READ(TI925_LCD_STATUS),
+	     (int)LCD_READ(TI925_LCD_TIMING0),
+	     (int)LCD_READ(TI925_LCD_TIMING1),
+	     (int)LCD_READ(TI925_LCD_TIMING2));
+
+#ifdef CONFIG_OMAP_INNOVATOR
+        DBG("lcd register %lux power %lux\n", inb(0xe8000002),
+            inb(0xe8000005) );
+#else
+        DBG("lcd register %lux power %lux fpga %lux\n", inb(0xe8000002),
+            inb(0xe8000005), inw(0xe97ffffe));
+#endif
+}
+#else
+static inline void print_lcd_regs(void) {}
+#endif
+
+static void tifb_init_dma(void)
+{
+        int size = current_par.palette_size + current_par.screen_size;
+
+        lcd_write_top_address((unsigned long) current_par.p_palette_base);
+        lcd_write_bottom_address((unsigned long)current_par.p_palette_base + 
+                                 size - 2);
+        lcd_dma_enable();
+
+        DBG(__FUNCTION__ " size=%d\n", size);
+        DBG(__FUNCTION__ " base=%lux\n", current_par.p_palette_base);
+        DBG(__FUNCTION__ " end=%lux\n", current_par.p_palette_base + size - 2);
+        print_lcd_regs();
+}
+
+static void __init tifb_init_registers(void)
+{
+        unsigned long value;
+        DBG(__FUNCTION__ "\n");
+
+        hardware_enable();
+
+        // setup the LCD Control
+        value = 0;
+        value |= (0<<12); // FDD to 16 wait cycles
+        value |= (1<<3);  // turn on the done mask
+        value |= (1<<9);
+        value |= (1<<7);  // tft
+
+        value = 0xcec;
+        LCD_WRITE(value, TI925_LCD_CONTROL);
+
+        // setup the Timing0
+        value = NUM_XPIXELS -1; // current_par.xres -1;
+        value |= ((4-1)<<10);   // HSW width for LCD is 4-1
+        value |= ((4-1)<<16);   // H Front Porch is 4-1
+        value |= ((40-1)<<24);  // H Back Porch is 40-1
+
+        //value = 0x27030cef;  This is what the above should equal
+        LCD_WRITE(value, TI925_LCD_TIMING0);
+
+        // setup the Timing1
+        value = NUM_YPIXELS -1; //current_par.yres - 1;
+        value |= (2 << 10);     // VSW width for the LCD is 2
+        value |= (2 << 16);     // Front Porch is 2
+        value |= (8 << 24);     // Back Porch is 8
+
+        //value = 0x0802093f;  This is what the above should equal
+        LCD_WRITE(value, TI925_LCD_TIMING1);
+
+        // setup the Timing2
+        //value = 2;           //  PCD 
+        //value |= (255 << 8); // ACB 
+        //value |= (0 << 16);  // ACBI this should be disabled
+        //value |= (0 << 20);  // IVS 
+        //value |= (0 << 21);  // IHS
+        //value |= (0 << 22);  // IPC
+        //value |= (0 << 23);  // IEO
+
+        value = 0x00300004;
+        LCD_WRITE(value, TI925_LCD_TIMING2);
+
+        // setup dma
+        tifb_init_dma();
+        print_lcd_regs();
+
+        lcd_enable();
+
+	/* REVISIT: This is req'd to get LCD DMA to free run. */
+        ck_disable(dma_ck);
+}
+
+static void lcd_dma_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+        unsigned long status = inw(omap1510_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                         LCD_CHANNEL,
+                                                         DMA_LCD_CTRL));
+        if ( status & (1<<5) )
+                printk("LCD DMA bus error");
+
+        if ( status & (1<<4) )
+                printk("LCD DMA end of frame 2");
+
+        if ( status & (1<<3) )
+                printk("LCD DMA end of frame 1");
+}
+ 
+static void lcd_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+	unsigned long status;
+	int reset = 0;
+	static int abc = 0;
+	static int fuf = 0;
+	static int sync = 0;
+	static int done = 0;
+
+	DBG(__FUNCTION__ "\n");
+	
+	status = LCD_READ(TI925_LCD_STATUS);
+	
+	if ( status & (1<<3) ) 
+        {
+		DBG("ABC interrupt");
+
+		status &= (1<<3);
+		LCD_WRITE(status,TI925_LCD_STATUS);
+		abc++;
+	}
+	
+	if ( status & (1<<5) ) 
+        {
+		DBG("FUF interrupt");
+
+		reset = 1;
+		fuf++;
+	}
+
+	if ( status & (1<<2) ) 
+        {
+		DBG("synch interrupt");
+
+		reset = 1;
+		sync++;
+	}
+
+	if ( status & (1<<0) ) 
+        {
+		DBG("DONE interrupt");
+
+		reset = 1;
+		done++;
+	}
+
+	if ( (sync % 1024) == 0 ) 
+        {
+		DBG(" abc %d fuf %d sync %d done %d\n",abc, fuf, sync, done);
+		print_lcd_regs();     
+	}
+
+	if ( reset ) 
+        {
+		// This will clear the error condition and restart the LCD
+		unsigned long control;
+
+		control = inl(IO_ADDRESS(TI925_LCD_CONTROL));
+		control &= ~(1<<0);
+		outl(control, IO_ADDRESS(TI925_LCD_CONTROL));
+		control = inl(IO_ADDRESS(TI925_LCD_CONTROL));
+		control |= (1<<0);
+		outl(control, IO_ADDRESS(TI925_LCD_CONTROL));
+	}
+}
+
+#endif /* _fb_omap1510_h_ */ 
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omap710.h linux-2.4.19/drivers/video/omap/omap710.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omap710.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/omap710.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,460 @@
+/*
+ * File: fb_omap710.h
+ *
+ * This file is the header file for the omap710 framebuffer.
+ *
+ * Copyright (C) 2002 RidgeRun, Inc. 
+ * Author: Alex McMains <aam@ridgerun.com> 2001/09/20
+ *         Greg Lonnon <glonnon@ridgerun.com>
+ *         Brian Mahaffy <brianm@ridgerun.com> 2002/01/29 ported to omap710
+ *
+ *             RIDGERUN, INC. PROPRIETARY INFORMATION
+ *  Property of RidgeRun, Inc. For Unrestricted Internal Use Only.
+ *  Unauthorized reproduction and/or distribution is strictly prohibited.
+ *  This product is protected under copyright law and trade secret law
+ *  as an unpublished work.
+ *
+ *  This source is provided for reference only and rights have not been
+ *  granted to modify or redistribute.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRPROCR (do not remove)
+ *
+ */
+
+#ifndef _fb_omap710_h_
+#define _fb_omap710_h_
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/ck.h>
+#include <asm/arch/dma.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#define NUM_XPIXELS 320
+#define NUM_YPIXELS 240
+#define BPP 8
+#define PALETTE_SIZE 512
+
+#define COLOR_8BIT
+
+#define MAX_FRAMEBUFFER_SIZE (((NUM_XPIXELS) * (NUM_YPIXELS) * (BPP)/8) + \
+                              (PALETTE_SIZE) + PAGE_SIZE)
+#define BPP_MASK 0x3000
+
+// we use this to check for valid displays in set_var
+struct _displays 
+{
+        int xres;
+        int yres;
+        int bpp;
+};
+static struct _displays displays_supported[] = { {320, 240, 8} };
+
+static struct fb_var_screeninfo tifb_default8 = 
+{
+        xres: 320, 
+        yres: 240, 
+        xres_virtual: 320, 
+        yres_virtual: 240, 
+        xoffset: 0, 
+        yoffset: 0, 
+        bits_per_pixel: BPP, 
+        grayscale : 0,
+        red: {0, 8, 0},
+        green: {0, 8, 0}, 
+        blue: {0, 8, 0},  
+        transp: {0, 0, 0},
+        nonstd: 0, 
+        activate: 0, 
+        height: -1, 
+        width: -1, 
+        accel_flags: 0, 
+        pixclock: 171521, 
+        left_margin: 64, 
+        right_margin: 64, 
+        upper_margin: 32, 
+        lower_margin: 32,
+        hsync_len : 64, 
+        vsync_len: 2,
+        sync: 0, 
+        vmode: FB_VMODE_NONINTERLACED
+};
+
+static inline void hardware_enable(void)
+{
+        DBG(__FUNCTION__ "\n");
+        // initialize LCD
+        fpga_write(0x2, FPGA_LCD_PANEL_CONTROL);
+        fpga_write(0x6, FPGA_LCD_PANEL_CONTROL);
+        udelay(100);
+
+        /* 
+           According to the errata, if the framebuffer is in SDRAM, the max clock
+           is 1/2 the TC clock rate.  If the framebuffer is in SRAM, the max clock is
+           = the TC clock rate.
+        */
+        ck_set_rate(lcd_ck, (ck_get_rate(tc_ck) / 2));
+        ck_enable(lcd_ck);
+        ck_enable(lbfree_ck);
+        
+}
+
+static inline void hardware_disable(void)
+{
+        DBG(__FUNCTION__ "\n");
+        // stop LCD
+        fpga_write(0x0, FPGA_LCD_PANEL_CONTROL);
+
+        ck_disable(lcd_ck);        
+        ck_disable(lbfree_ck);        
+}
+
+static inline int lcd_active(void)
+{
+    // Return true if LCD controller is running.
+    return(LCD_READ(OMAP710_LCD_CONTROL) & 1);
+}
+
+static inline void lcd_enable(void)
+{
+        unsigned long value;
+
+        DBG(__FUNCTION__ "\n");
+        // enable the LCD
+        value = LCD_READ(OMAP710_LCD_CONTROL);
+        value |= 1;
+        LCD_WRITE(value,OMAP710_LCD_CONTROL);
+        fpga_write(0x7, FPGA_LCD_PANEL_CONTROL);
+}
+
+static inline void lcd_disable(void)
+{
+        unsigned long value;
+
+        // Clear the AutoIdle bit in the Global DMA control reg to work around the DMA
+        // state machine bug in TI's errata doc.  Have to do this to be able to stop and
+        // restart the LCD controller reliably.  We'll turn the bit back on in sys_idle.
+        omap_dma_autoidle_set(DISABLE_AUTOIDLE); 
+
+        DBG(__FUNCTION__ "\n");
+        // enable the LCD
+        value = LCD_READ(OMAP710_LCD_CONTROL);
+        value &= ~1;
+        LCD_WRITE(value,OMAP710_LCD_CONTROL);
+}
+
+static inline void orl(unsigned long val, unsigned long reg) 
+{
+        DBG(__FUNCTION__ "\n");
+        outl((inl(reg) | val),reg);
+}
+
+static inline unsigned long omap710_dma_reg_addr(int global, int chan, int reg) 
+{ 
+        DBG(__FUNCTION__ " global:%8.8x chan:%8.8x reg:%8.8x\n", global, chan, reg);
+        return (OMAP710_DMA_BASE + (global << 10) + (chan << 6) + (reg << 1));
+}
+
+static inline void lcd_write_top_address(unsigned long addr) 
+{
+        unsigned long reg;
+
+        DBG(__FUNCTION__ "\n");
+        reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_U);
+
+        DBG(__FUNCTION__ "\n%lX %lX\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lX %8.8x\n", reg, inw(reg));
+
+        reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS, LCD_CHANNEL, 
+                                    DMA_LCD_TOP_F1_L);
+
+        DBG("%lX %lX\n", reg, addr & 0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lX %8.8x\n", reg, inw(reg));
+}
+
+static inline void lcd_write_bottom_address(unsigned long addr) 
+{
+        unsigned long reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL, 
+                                                  DMA_LCD_BOT_F1_U);
+
+        DBG(__FUNCTION__ "\n%lX %lX\n", reg, addr >> 16);
+
+        outw(addr >> 16, reg);
+
+        DBG("wrote %lX %8.8x\n", reg, inw(reg));
+
+        reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                    LCD_CHANNEL, DMA_LCD_BOT_F1_L);
+
+        DBG("%lX %lX\n", reg, addr&0xffff);
+
+        outw(addr & 0xffff, reg);
+
+        DBG("wrote %lX %8.8x\n", reg, inw(reg));
+}
+
+static inline void lcd_dma_enable(void) 
+{
+        unsigned long reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                  LCD_CHANNEL,
+                                                  DMA_LCD_CTRL);
+	    DBG(__FUNCTION__ "\n");
+        DBG("%lX\n",reg);
+
+        //reg = omap710_dma_reg_addr(GLOBAL_DMA_ACCESS, 0, 0);
+        //outw((1<<2),reg);  // dma is free running ????
+        DBG("wrote %lX %lX\n",reg,inl(reg));
+
+        reg = omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,LCD_CHANNEL,
+                                    DMA_LCD_CTRL);
+
+#if CONFIG_FB_SDRAM
+        outw((LCD_BUS_ERROR_IT_IE),reg);
+#else
+        outw((LCD_BUS_ERROR_IT_IE | LCD_SOURCE_IMIF),reg);
+#endif
+        DBG("wrote %lX %lX\n",reg,inl(reg));
+}
+
+#ifdef CONFIG_PM
+/*
+  Power management.
+*/
+
+static int tifb_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
+{
+	DBG(__FUNCTION__ "\n");
+
+	if (rqst == PM_SUSPEND || rqst == PM_RESUME) {
+		int state = (int)data;
+
+                switch (state) {
+                case 0:
+                        hardware_enable();
+                        lcd_enable();
+                        break;
+                default:
+			/* Enter D1-D3.  Disable the LCD controller.  */
+                        lcd_disable();
+                        hardware_disable();
+                        break;
+                }
+	}
+	DBG("done\n");
+	return 0;        
+}
+#endif
+
+#ifdef FB_DEBUG 
+static inline void print_lcd_regs(void)
+{
+	DBG(__FUNCTION__ "\n");
+
+	DBG("control: %8.8x status %8.8x\n\ttiming0 %8.8x" 
+	     " timing1 %8.8x timing2 %8.8x\n", 
+	     (int)LCD_READ(OMAP710_LCD_CONTROL), 
+	     (int)LCD_READ(OMAP710_LCD_STATUS),
+	     (int)LCD_READ(OMAP710_LCD_TIMING0),
+	     (int)LCD_READ(OMAP710_LCD_TIMING1),
+	     (int)LCD_READ(OMAP710_LCD_TIMING2));
+
+//        DBG("lcd register %8.8x power %8.8x fpga %8.8x\n", inb(0xe8000002),
+//            inb(0xe8000005), inw(0xe97ffffe));
+}
+#else
+static inline void print_lcd_regs(void) {}
+#endif
+
+static void tifb_init_dma(void)
+{
+        int size = current_par.palette_size + current_par.screen_size;
+	    DBG(__FUNCTION__ "\n");
+
+        lcd_write_top_address((unsigned long) current_par.p_palette_base);
+        lcd_write_bottom_address((unsigned long)current_par.p_palette_base + 
+                                 size - 2);
+        lcd_dma_enable();
+
+        DBG(__FUNCTION__ " size=%d\n", size);
+        DBG(__FUNCTION__ " base=%lX\n", (unsigned long int)current_par.p_palette_base);
+        DBG(__FUNCTION__ " end=%lX\n", (unsigned long int)current_par.p_palette_base + size - 2);
+        print_lcd_regs();
+}
+
+static void __init tifb_init_registers(void)
+{
+        unsigned long value;
+        DBG(__FUNCTION__ "\n");
+
+        hardware_enable();
+
+        // setup the LCD Control
+//        value = 0;
+//        value |= (0<<12); // FDD to 16 wait cycles
+//        value |= (1<<3);  // turn on the done mask
+//        value |= (1<<9);
+//        value |= (1<<7);  // tft
+
+        value = 0x00000C64;
+        value = 0x00010E6C;
+        LCD_WRITE(value, OMAP710_LCD_CONTROL);
+
+        // setup the Timing0
+//        value = 320 -1;         // current_par.xres -1;
+//        value |= (11<<10);      // HSW width for LCD is 11
+//        value |= (13<<16);      // H Front Porch is 13
+//        value |= ((71-12)<<24); // H Back Porch is 71-12 
+
+        value = 0x314F093F;
+        LCD_WRITE(value, OMAP710_LCD_TIMING0);
+
+        // setup the Timing1
+//        value = 240 - 1;    //current_par.yres - 1;
+//        value |= (0 << 10); // VSW width for the LCD is 1 (minus 1)
+//        value |= (1 << 16); // Front Porch not used
+//        value |= (0 << 24); // Back Porch not used
+
+        value = 0x000004EF;
+        LCD_WRITE(value, OMAP710_LCD_TIMING1);
+
+        // setup the Timing2
+//        value = 2;           //  PCD 
+//        value |= (255 << 8); // ACB 
+//        value |= (0 << 16);  // ACBI this should be disabled
+//        value |= (0 << 20);  // IVS 
+//        value |= (0 << 21);  // IHS
+//        value |= (0 << 22);  // IPC
+//        value |= (0 << 23);  // IEO
+
+        value = 0x00000006;
+        LCD_WRITE(value, OMAP710_LCD_TIMING2);
+
+        // setup dma
+        tifb_init_dma();
+        print_lcd_regs();
+
+        lcd_enable();
+
+        // Not sure why this needs to happen, but SteveK and BrianM determined
+        // it was needed by trial and error to get the LCD dma to go on the 710.
+        // We just turn off the dma clock and then turn it right back on.
+        ck_disable(dma_ck);
+        ck_enable(dma_ck);
+
+#ifdef CONFIG_PM
+        /*
+	 * Note that the console registers this as well, but we want to
+	 * power down the display prior to sleeping.
+	 */
+	pm_register(PM_SYS_DEV, PM_SYS_VGA, tifb_pm_callback);
+#endif
+}
+
+static void lcd_dma_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+        unsigned long status = inw(omap710_dma_reg_addr(NO_GLOBAL_DMA_ACCESS,
+                                                         LCD_CHANNEL,
+                                                         DMA_LCD_CTRL));
+	    DBG(__FUNCTION__ "\n");
+        if ( status & (1<<5) )
+                printk("LCD DMA bus error");
+
+        if ( status & (1<<4) )
+                printk("LCD DMA end of frame 2");
+
+        if ( status & (1<<3) )
+                printk("LCD DMA end of frame 1");
+}
+ 
+static void lcd_irq_handler(int irq, void *dummy, struct pt_regs *fp)
+{
+	unsigned long status;
+	int reset = 0;
+	static int abc = 0;
+	static int fuf = 0;
+	static int sync = 0;
+	static int done = 0;
+    int missed_int_bug = 0;
+
+	status = LCD_READ(OMAP710_LCD_STATUS);
+
+//	DBG(__FUNCTION__ " status:%8.8x\n",status);
+	
+	if ( status & (1<<3) ) 
+        {
+		DBG("ABC interrupt");
+
+        missed_int_bug = 0;
+		status &= (1<<3);
+		LCD_WRITE(status,OMAP710_LCD_STATUS);
+		abc++;
+	}
+	
+	if ( status & (1<<5) ) 
+        {
+		DBG("FUF interrupt");
+
+        missed_int_bug = 0;
+		reset = 1;
+		fuf++;
+	}
+
+	if ( status & (1<<2) ) 
+        {
+		DBG("synch interrupt");
+
+        missed_int_bug = 0;
+		reset = 1;
+		sync++;
+	}
+
+	if ( status & (1<<0) ) 
+        {
+		DBG("DONE interrupt");
+
+        missed_int_bug = 0;
+		reset = 1;
+		done++;
+	}
+
+	if ( (sync % 1024) == 0 ) 
+        {
+		DBG(" abc %d fuf %d sync %d done %d\n",abc, fuf, sync, done);
+		print_lcd_regs();     
+	}
+
+
+	if ( reset || missed_int_bug ) 
+        {
+		// This will clear the error condition and restart the LCD
+		unsigned long control;
+
+		control = inl(IO_ADDRESS(OMAP710_LCD_CONTROL));
+		control &= ~(1<<0);
+		outl(control, IO_ADDRESS(OMAP710_LCD_CONTROL));
+		control = inl(IO_ADDRESS(OMAP710_LCD_CONTROL));
+		control |= (1<<0);
+		outl(control, IO_ADDRESS(OMAP710_LCD_CONTROL));
+	}
+}
+
+#endif /* _fb_omap710_h_ */ 
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omapfb.c linux-2.4.19/drivers/video/omap/omapfb.c
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omapfb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/omapfb.c	2003-01-09 19:50:05.000000000 +0200
@@ -0,0 +1,706 @@
+/*
+ * File: fb.c
+ *
+ * The frame buffer driver for TI arm9 boards: ti925, omap710 & omap1510.
+ *
+ * Copyright (C) 2001, 2002 RidgeRun, Inc. 
+ * Author: Alex McMains <aam@ridgerun.com> 2001/05/10
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs and problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#include "omapfb.h"
+
+static struct tifb_par current_par;
+
+#include <linux/config.h>
+#include <video/fbcon.h>
+#include <video/fbcon-mfb.h>
+#include <video/fbcon-cfb4.h>
+#include <video/fbcon-cfb8.h>
+#include <video/fbcon-cfb16.h>
+
+#ifdef CONFIG_ARCH_TI925
+#include "ti925.h"
+#elif defined(CONFIG_ARCH_OMAP710)
+#include "omap710.h"
+#elif defined(CONFIG_ARCH_OMAP1510)
+#if defined(CONFIG_OMAP_INNOVATOR)
+#include "innovator.h"
+#else
+#include "omap1510.h"
+#endif
+#else
+#error "ARCHITECTURE NOT SUPPORTED"
+#endif
+
+// NOTE: DEBUG defined in omapfb.h
+
+static u_long tifb_memory;
+static struct display disp;
+static struct fb_info tifb_info;
+
+#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32)
+static union {
+#ifdef FBCON_HAS_CFB16
+    u16 cfb16[16];
+#endif
+#ifdef FBCON_HAS_CFB24
+    u32 cfb24[16];
+#endif
+#ifdef FBCON_HAS_CFB32
+    u32 cfb32[16];
+#endif
+} fbcon_cmap;
+#endif
+
+static const char desc[]   = "RR TI ARM9 Framebuffer Driver";
+static const char author[] = "Copyright (C) 2001 RidgeRun, Inc.";
+
+//static char *tifb_name = "RR TI FB";
+static int tifb_enable = 1;
+static int currcon     = 0;
+
+/********************************
+ Standard frame buffer interface
+*********************************/
+
+int __init tifb_setup(char *);
+static int tifb_get_fix(struct fb_fix_screeninfo *fix, int con, 
+                        struct fb_info *info);
+static int tifb_get_var(struct fb_var_screeninfo *var, int con,
+                        struct fb_info *info);
+static int tifb_set_var(struct fb_var_screeninfo *var, int con,
+                        struct fb_info *info);
+static int tifb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
+                         struct fb_info *info);
+static int tifb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
+                         struct fb_info *info);
+static int tifb_pan_display(struct fb_var_screeninfo *var, int con,
+                            struct fb_info *info);
+
+/*****************************************
+ Interface to the low level console driver
+ *****************************************/
+
+static int __init tifb_init(void);
+static int tifbcon_switch(int con, struct fb_info *info);
+//static int tifbcon_updatevar(int con, struct fb_info *info);
+static void tifbcon_blank(int blank, struct fb_info *info);
+
+/*****************
+ Internal routines
+ *****************/
+
+static void tifb_encode_fix(struct fb_fix_screeninfo *fix,
+                            struct fb_var_screeninfo *var);
+static int tifb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
+                          u_int *transp, struct fb_info *info);
+static int tifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                          u_int transp, struct fb_info *info);
+static void do_install_cmap(int con, struct fb_info *info);
+static void tifb_init_palette(void);
+static void tifb_init_palette_color(void);
+static void tifb_init_registers(void);
+static void tifb_init_dma(void);
+static int tifb_map_video_memory(void);
+
+static struct fb_ops tifb_ops =
+{
+        owner:          THIS_MODULE,
+        fb_get_fix:     tifb_get_fix,
+        fb_get_var:     tifb_get_var,
+        fb_set_var:     tifb_set_var,
+        fb_get_cmap:    tifb_get_cmap,
+        fb_set_cmap:    tifb_set_cmap,
+        fb_pan_display: tifb_pan_display,
+};
+
+/************************************
+ tifb_get_fix()
+ Purpose: 
+   Get the fixed part of the display
+ *************************************/
+static int tifb_get_fix(struct fb_fix_screeninfo *fix, int con, 
+                        struct fb_info *info)
+{
+        struct fb_var_screeninfo *var;
+        
+        if ( con == -1 )
+        {
+#ifdef COLOR_8BIT
+                var = &tifb_default8;
+#elif defined(COLOR_16BIT)
+                var = &tifb_default16;
+#else
+#error "COLOR DEPTH NOT SUPPORTED" 
+#endif
+        }
+        else
+                var = &fb_display[con].var;
+
+        tifb_encode_fix(fix, var);
+        
+        return 0;
+}
+
+/******************************************
+ tifb_get_var()
+ Purpose: 
+   Get the user defined part of the display
+ *******************************************/
+static int tifb_get_var(struct fb_var_screeninfo *var, int con, 
+                        struct fb_info *info)
+{
+        if ( con == -1 )
+        {
+#ifdef COLOR_8BIT
+                *var = tifb_default8;
+#elif defined(COLOR_16BIT)
+                *var = tifb_default16;
+#else
+#error "COLOR DEPTH NOT SUPPORTED"
+#endif
+        }
+        else
+                *var = fb_display[con].var;
+        
+        return 0;
+}
+
+/******************************************
+ tifb_set_var()
+ Purpose: 
+   Set the user defined part of the display
+ *******************************************/
+static int tifb_set_var(struct fb_var_screeninfo *var, int con, 
+                        struct fb_info *info)
+{
+        struct display *display;
+        int i;
+        int ok_display;
+
+        // make sure we support the new display
+        ok_display = 0;
+        for ( i=0; i < (sizeof(displays_supported)/sizeof(struct _displays)); i++ )
+        {
+                if ( (var->xres == displays_supported[i].xres) &&
+                     (var->yres == displays_supported[i].yres) &&
+                     (var->bits_per_pixel == displays_supported[i].bpp) )
+                {
+                        ok_display = 1;
+                        break;
+                }
+        }
+
+        if ( ! ok_display )
+                return -EINVAL;
+        
+	if ( con >= 0 )
+		display = &fb_display[con];
+	else
+		display = info->disp;	/* used during initialization */
+
+	/* update the display interface */
+	display->var            = *var;
+	display->screen_base	= current_par.v_screen_base;
+
+#ifdef COLOR_8BIT
+	display->visual	        = FB_VISUAL_PSEUDOCOLOR;
+#elif defined(COLOR_16BIT)
+        display->visual         = FB_VISUAL_TRUECOLOR; 
+#else
+#error "COLOR DEPTH NOT SUPPORTED"
+#endif
+
+	display->type		= FB_TYPE_PACKED_PIXELS;
+	display->type_aux	= 0;
+	display->ypanstep	= 0;
+	display->ywrapstep	= 0;
+	display->line_length	= (var->xres_virtual * var->bits_per_pixel) 
+                / 8; 
+        display->next_line      = (var->xres_virtual * var->bits_per_pixel) 
+                / 8;
+	display->can_soft_blank = 1;
+	display->inverse	= 0;
+
+	DBG(__FUNCTION__ " display->bpp = %d\n", display->var.bits_per_pixel);
+  
+	switch ( display->var.bits_per_pixel ) 
+        {
+#ifdef FBCON_HAS_CFB4
+	case 4:
+		display->dispsw = &fbcon_cfb4;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB8
+	case 8: 
+		DBG(__FUNCTION__ " &fbcon_cfb8 = %lX\n", (unsigned long int)&fbcon_cfb8);
+		DBG(__FUNCTION__ " dispsw pre-set\n");
+		display->dispsw = &fbcon_cfb8;
+		DBG(__FUNCTION__ " dispsw set\n");
+		DBG(__FUNCTION__ " dispsw = %lX\n", (unsigned long int)display->dispsw);
+        if (display->dispsw) {
+		DBG(__FUNCTION__ " fontwidthmask = %X\n",
+                     display->dispsw->fontwidthmask);
+        }
+		break;
+#endif
+#ifdef FBCON_HAS_CFB16
+	case 16:
+		display->dispsw = &fbcon_cfb16;
+                display->dispsw_data = fbcon_cmap.cfb16;
+		break;
+#endif
+	default:
+		DBG((__FUNCTION__ " arghh! No display that supports 
+                                    fonts!\n"));
+		display->dispsw = &fbcon_dummy;
+		break;
+	}
+
+	{
+		struct fb_cmap *cmap;
+		cmap = fb_default_cmap(current_par.palette_size);
+		fb_set_cmap(cmap, 1, tifb_setcolreg, info);
+	}
+  
+	return 0;
+}
+
+/****************************
+ tifb_get_cmap()
+ Purpose: 
+   Get the display's colormap
+*****************************/
+static int tifb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
+                         struct fb_info *info)
+{
+	if ( (!info->display_fg) || (con == info->display_fg->vc_num) ) 
+        { /* current console? */
+		return fb_get_cmap(cmap, kspc, tifb_getcolreg, info);
+        }
+	else if ( fb_display[con].cmap.len ) /* non default colormap? */
+        {
+		fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
+        }
+	else 
+        {
+		int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
+		fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
+	}
+
+	return 0;
+}
+
+/****************************
+ tifb_set_cmap()
+ Purpose: 
+   Set the display's colormap
+*****************************/
+static int tifb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
+                         struct fb_info *info)
+{
+        int err;
+	struct display *disp;
+
+	if ( con >= 0 )
+		disp = &fb_display[con];
+	else
+		disp = info->disp;
+
+	if ( !disp->cmap.len ) 
+        {	/* no colormap allocated? */
+		int size = disp->var.bits_per_pixel == 16 ? 32 : 256;
+
+		if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
+			return err;
+	}
+
+	if ( !info->display_fg || con == info->display_fg->vc_num )
+		return fb_set_cmap(cmap, kspc, tifb_setcolreg, info);
+	else
+		fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
+
+	return 0;
+}
+
+/***************************
+ tifb_pan_display()
+ Purpose: 
+   Pan or wrap the display
+ ***************************/
+static int tifb_pan_display(struct fb_var_screeninfo *var, int con,
+                            struct fb_info *info)
+{
+        return 0;
+}
+
+/***************************
+ tifb_encode_fix()
+ Purpose: 
+   
+ ***************************/
+static void tifb_encode_fix(struct fb_fix_screeninfo *fix,
+                            struct fb_var_screeninfo *var)
+{
+        memset(fix, 0, sizeof(struct fb_fix_screeninfo));
+        strcpy(fix->id, desc);
+        
+        fix->smem_start  = (unsigned long) current_par.p_screen_base;
+        fix->smem_len    = NUM_XPIXELS * NUM_YPIXELS * (var->bits_per_pixel / 8); //AAMtifb_memorysize;
+        fix->type        = FB_TYPE_PACKED_PIXELS;
+        fix->type_aux    = 0;
+#ifdef COLOR_8BIT
+        fix->visual      = FB_VISUAL_PSEUDOCOLOR;
+#elif defined(COLOR_16BIT)
+        fix->visual      = FB_VISUAL_TRUECOLOR;
+#else 
+#error "COLOR DEPTH NOT SUPPORTED"
+#endif
+        fix->ywrapstep   = 1;
+        fix->xpanstep    = 1;
+        fix->ypanstep    = 1;
+        fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
+        fix->accel       = FB_ACCEL_NONE;
+}
+
+int __init tifb_setup(char *options) 
+{
+	char *this_opt;
+	
+	printk(KERN_INFO "DSPLinux: TIFB DMA options: %s\n", options);
+
+	if ( !options || !*options )
+		return 0;
+  
+	for (this_opt = strtok(options, ","); this_opt;
+	     this_opt = strtok(NULL, ",")) 
+        {
+    
+/*      if (!strncmp(this_opt, "bpp:", 4)) */
+/*        current_par.max_bpp = simple_strtoul(this_opt+4, NULL, 0); */
+    
+	}
+
+	return 0;
+}
+
+static int tifbcon_switch(int con, struct fb_info *info)
+{
+	/* Do we have to save the colormap? */
+	if ( fb_display[currcon].cmap.len )
+		fb_get_cmap(&fb_display[currcon].cmap, 1, tifb_getcolreg, 
+                            info);
+
+        currcon = con;
+
+	/* Install new colormap */
+	do_install_cmap(con, info);
+
+	return 0;
+}
+
+/*  Blank the display. */
+static void tifbcon_blank(int blank, struct fb_info *info)
+{
+	DBG((__FUNCTION__ "\n"));
+
+        if (blank) {       // turn off 
+                lcd_disable();
+                hardware_disable();
+        }
+        else {             // turn back on
+                hardware_enable();
+                lcd_enable();
+        }
+}
+
+
+/*
+ *  Read a single color register and split it into
+ *  colors/transparent. Return != 0 for invalid regno.
+ */
+static int tifb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
+                          u_int *transp, struct fb_info *info)
+{
+	u_short pal_entry;
+	unsigned short *palette = (unsigned short *)current_par.v_palette_base;
+
+	if ( regno > (PALETTE_SIZE/2 - 1) )
+		return 1;
+
+	pal_entry = palette[regno];
+
+	*red    = (pal_entry & 0x000f) << 12;
+	*green  = (pal_entry & 0x00f0) << 8;
+	*blue   = (pal_entry & 0x0f00) << 4;
+	*transp = 0;
+
+	return 0;
+}
+
+/*
+ *  Set a single color register. The values supplied are already
+ *  rounded down to the hardware's capabilities (according to the
+ *  entries in the var structure). Return != 0 for invalid regno.
+ */
+
+static int tifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                          u_int transp, struct fb_info *info)
+{
+
+	u_short pal;
+	unsigned short *palette = (unsigned short *)current_par.v_palette_base;
+
+	if ( regno > (PALETTE_SIZE/2 - 1) )
+		return 1;
+
+	pal   = ((red   >>  4) & 0xf00);
+	pal  |= ((green >>  8) & 0x0f0);
+	pal  |= ((blue  >> 12) & 0x00f);
+        
+	palette[regno] = pal;
+
+	palette[0] |= BPP_MASK;  // encode the bpp in the first palette entry
+
+        switch ( current_par.bpp ) 
+        {
+        case 8:
+                break;
+#ifdef FBCON_HAS_CFB16
+        case 16:
+                fbcon_cmap.cfb16[regno] = pal;
+                break;
+#endif
+        default:
+                printk(KERN_WARNING "unsupported video bpp %d\n",current_par.bpp);
+                break;
+        }
+
+	return 0;
+}
+
+static void do_install_cmap(int con, struct fb_info *info)
+{
+
+	DBG((__FUNCTION__ "\n"));
+
+	if ( con != currcon )
+		return;
+
+	if ( fb_display[con].cmap.len )
+		fb_set_cmap(&fb_display[con].cmap, 1, tifb_setcolreg, info);
+	else
+		fb_set_cmap(
+                        fb_default_cmap(1<<fb_display[con].var.bits_per_pixel),
+                        1, tifb_setcolreg, info);
+}
+         
+static void tifb_init_palette()
+{
+        tifb_init_palette_color();
+}
+
+static void tifb_init_palette_color()
+{
+	unsigned short *palette = (unsigned short *)current_par.v_palette_base;
+	
+	memset(palette, 0, current_par.palette_size);
+ 
+	// setup the bpp
+        palette[0] |= BPP_MASK;
+
+//	tifb_init_dma();
+}
+
+static int tifb_map_video_memory(void)
+{
+	struct page *page;
+
+	/* set reserved flag for fb memory to allow it to be remapped into
+	 * user space by the fbmem driver 
+	 */
+	for ( page = virt_to_page(current_par.v_screen_base); 
+              page < virt_to_page(current_par.v_screen_base + 
+                                  current_par.screen_size); 
+              page++) 
+        {
+		mem_map_reserve(page);
+	}
+
+	/* REVISIT: remap the fb memory to a non-buffered, non-cached region */
+
+	memset(current_par.v_screen_base, 0, current_par.screen_size); 
+
+	return 1;
+}
+
+/******************************
+ tifb_init()
+ Purpose: 
+   Initialize the frame buffer
+ ******************************/
+static __init int tifb_init(void)
+{
+        char *buf;
+
+        if ( !tifb_enable )
+                return -ENXIO;
+
+        printk(KERN_INFO "DSPLinux FB (c) 2001 RidgeRun, Inc.\n");
+
+        if (lcd_active())  // If the LCD is already running (RRload Image), we need to stop it.
+        {
+            lcd_disable(); // Call the disble routine to stop stuff.
+        }
+
+#if CONFIG_FB_SDRAM
+        tifb_memory = __get_dma_pages(GFP_KERNEL,
+                                      get_order(MAX_FRAMEBUFFER_SIZE));
+
+#else
+        tifb_memory = (char *)SRAM_FRAMEBUFFER_MEMORY;
+#endif
+
+        buf = (char *)tifb_memory;
+        if ( buf == NULL) 
+        {
+                printk(KERN_INFO "DSPLinux: unable to allocate memory for framebuffer");
+                return -EINVAL;
+        }
+        buf += PAGE_SIZE;  // the start of the framebuffer, not the palette
+
+        DBG(__FUNCTION__ " v_screen_base:%lX\n",(unsigned long int)buf);
+
+        // initialize fbinfo
+        strcpy(tifb_info.modename, desc);
+        strcpy(tifb_info.fontname, "Acorn8x8");
+        tifb_info.node       = -1;
+        tifb_info.flags      = FBINFO_FLAG_DEFAULT;
+        tifb_info.fbops      = &tifb_ops;
+        tifb_info.disp       = &disp;
+        tifb_info.switch_con = &tifbcon_switch;
+        tifb_info.blank      = &tifbcon_blank;
+        tifb_info.changevar  = NULL;
+
+        // initialize current_par
+#ifdef COLOR_8BIT
+        current_par.bpp            = 8;
+#elif defined(COLOR_16BIT)
+        current_par.bpp            = 16;
+#else
+#error "COLOR DEPTH NOT SUPPORTED"
+#endif
+        current_par.screen_size    = (NUM_XPIXELS * NUM_YPIXELS * 
+                                      current_par.bpp) / 8;
+        current_par.palette_size   = PALETTE_SIZE;
+	current_par.p_palette_base = 
+                (unsigned char *) virt_to_phys(buf - PALETTE_SIZE);
+	current_par.v_palette_base = (buf - PALETTE_SIZE);
+	current_par.p_screen_base  = (unsigned char *) virt_to_phys(buf);
+	current_par.v_screen_base  = buf;
+	current_par.currcon	   = -1;
+
+        // initialize hardware
+        tifb_init_palette();
+        tifb_init_registers();
+
+        tifb_map_video_memory();
+        // setup irq handlers
+        if ( request_irq(INT_LCD_CTRL, lcd_irq_handler, 0, 
+                         "console/lcd", 0) < 0)
+        {
+                printk(KERN_INFO "DSPLinux: unable to get LCD irq\n");
+		goto free_mem;
+        }
+
+#ifndef CONFIG_ARCH_TI925
+        if ( request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
+                         "console/lcddma", 0) < 0)
+        {
+                printk(KERN_INFO "DSPLinux: unable to get DMA irq\n");
+                goto free_lcd_irq;
+        }
+#endif
+
+        // initialize var_screeninfo
+#ifdef COLOR_8BIT
+        tifb_set_var(&tifb_default8, -1, &tifb_info);
+#elif defined(COLOR_16BIT)
+        tifb_set_var(&tifb_default16, -1, &tifb_info);
+#else
+#error "COLOR DEPTH NOT SUPPORTED"
+#endif
+
+        // register frame buffer
+        if ( register_framebuffer(&tifb_info) < 0 )
+        {
+                printk(KERN_INFO "DSPLinux: register_framebuffer failed\n");
+
+                //free_pages(tifb_memory, get_order(MAX_FRAMEBUFFER_SIZE));
+
+                goto free_irq;
+        }
+        
+        return 0;
+
+ free_irq:
+#ifndef CONFIG_ARCH_TI925
+        free_irq(INT_DMA_LCD, 0);
+#endif
+ free_lcd_irq:
+        free_irq(INT_LCD_CTRL, 0);
+
+ free_mem:
+#if CONFIG_FB_SDRAM
+        free_pages(tifb_memory, get_order(MAX_FRAMEBUFFER_SIZE)); 
+#endif
+        return -EINVAL;
+}
+
+static void __exit tifb_cleanup(void)
+{
+        unregister_framebuffer(&tifb_info);
+        
+#if CONFIG_FB_SDRAM
+        free_pages(tifb_memory, get_order(MAX_FRAMEBUFFER_SIZE));
+#endif
+        free_irq(INT_LCD_CTRL, 0);
+
+#ifndef CONFIG_ARCH_TI925
+        free_irq(INT_DMA_LCD, 0);
+#endif
+}
+
+module_init(tifb_init);
+module_exit(tifb_cleanup);
+
+/*
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omapfb.h linux-2.4.19/drivers/video/omap/omapfb.h
--- ../linux-2.4.19-rmk4-vanilla/drivers/video/omap/omapfb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/drivers/video/omap/omapfb.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,99 @@
+/*
+ * File: fb.h
+ *
+ * This file is the common header file for the arm9 framebuffers.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.  
+ * Author: Alex McMains <aam@ridgerun.com> 2001/05/10
+ *         Greg Lonnon <glonnon@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs and problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+
+#ifndef _fb_h_
+#define _fb_h_
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/wrapper.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/page.h>
+
+#undef FB_DEBUG 
+#ifdef FB_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+struct tifb_par 
+{
+        unsigned char *p_screen_base;
+        unsigned char *v_screen_base;
+        unsigned char *p_palette_base;
+        unsigned char *v_palette_base;
+        unsigned long screen_size;
+        unsigned int  palette_size;
+        unsigned int  currcon;
+        unsigned int  bpp;
+};
+
+static void lcd_irq_handler(int irq, void *dummy, struct pt_regs *fp);
+
+// LCD inlines
+inline void LCD_WRITE(unsigned long v, unsigned long a) 
+{ 
+        outl((v),(IO_ADDRESS(a))); 
+}
+
+inline unsigned long LCD_READ(unsigned long a) 
+{ 
+        return inl(IO_ADDRESS(a)); 
+}
+
+#endif /* _fb_h_ */
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/arch_ck.h linux-2.4.19/include/asm-arm/arch-omap1510/arch_ck.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/arch_ck.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/arch_ck.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,106 @@
+/*****************************************************************************
+  NAME
+        arch_ck.h -- enumerate the clocks for the omap1510 platform
+     
+  AUTHOR
+        gmcnutt@ridgerun.com
+
+  REFERENCES
+        [1] Dsc21ArmPeripherals0.1.pdf Section 14
+        [2] TMS320DSC21 Design Workshop Student Guide v3 p 5-14
+
+  COPYRIGHT
+        (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+
+   This program is free software; you can redistribute  it and/or modify it
+   under  the terms of  the GNU General  Public License as published by the
+   Free Software Foundation;  either version 2 of the  License, or (at your
+   option) any later version.
+ 
+   THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+   WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ 
+   Please report all bugs and problems to the author or <support@dsplinux.net> 
+
+   key: RRGPLCR (do not remove)
+ *****************************************************************************/
+#ifndef arch_ck_h
+#define arch_ck_h
+
+#include <linux/config.h>
+
+/* This enum is the bare minimum needed to support the kmod/ck.h interface. 
+   I don't list entries for ck_gen2/ck_gen3 since these aren't really supported
+   yet for OMAP. To use these we'd have to select one of the non-recommended
+   clocking schemes.
+*/
+typedef enum { 
+
+        /* system clocks (fixed) */
+        clkin = 0,
+
+        /* DPLL1 */
+        ck_gen1, ck_gen2, ck_gen3,
+
+        /*  
+            Special:  TC needs to be checked before anything else,
+            so I'll put it first so I can easily loop through.
+        */
+        tc_ck,
+        
+        /* CLKM1 */
+        arm_ck, mpuper_ck, arm_gpio_ck, mpuxor_ck, mputim_ck, mpuwd_ck,
+
+        /* CLKM2 */
+        dsp_ck, dspmmu_ck, 
+
+#if 0
+        /* accessible only from the dsp... */
+        dspper_ck, gpio_ck, dspxor_ck, dsptim_ck, dspwd_ck,
+        uart_ck,
+#endif
+        /* CLKM3 */
+        /* tc_ck, */ dma_ck, api_ck, hsab_ck, lbfree_ck, lb_ck, lcd_ck
+
+} ck_t;
+
+typedef enum {
+        /* Reset the MPU */
+        arm_rst,
+
+        /* Reset the DSP */
+        dsp_rst,
+
+        /* Reset priority registers, EMIF config, and MPUI control logic */
+        api_rst,
+
+        /* Reset DSP, MPU, and Peripherals */
+        sw_rst,
+} reset_t;
+
+#define CK__MIN clkin
+#define CK__MAX lcd_ck
+//#define CK__MAX_RATE (12 * 31)
+#if defined(CONFIG_OMAP_ARM_120MHZ)
+#define CK__MAX_RATE 120
+#elif defined(CONFIG_OMAP_ARM_60MHZ)
+#define CK__MAX_RATE 60
+#elif defined(CONFIG_OMAP_ARM_30MHZ)
+#define CK__MAX_RATE 30
+#elif defined(CONFIG_OMAP_ARM_168MHZ)
+#define CK__MAX_RATE 168
+#endif
+
+// This is used by CK and DSPC, so put it somewhere they can both see it.
+#define MPUI_STROBE_MAX_1509 24
+#define MPUI_STROBE_MAX_1510 30
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/ck.h linux-2.4.19/include/asm-arm/arch-omap1510/ck.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/ck.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/ck.h	2003-01-15 12:37:35.000000000 +0200
@@ -0,0 +1,129 @@
+/*****************************************************************************
+  NAME
+        ck.h -- generic interface to clock control
+     
+  DESCRIPTION
+        This interface will be implemented by arch-specific DPLL/CLKM/Clock
+        Controller drivers. It's NOT a user interface -- if you want to
+        provide a user interface then lay a proc or dev driver over it. The
+        idea is that you can either do that or you can keep clock control
+        entirely inside the kernel by having a clock policy module use this
+        interface for control/sense.
+
+        This shows some possible architectures for supporting power management
+        or whatever on top of the clock control interface:
+
+        +--------------------------+
+        | pm app                   |
+        +--------------------------+
+        +-----------+ +------------+ +-----------+
+        | proc "pm" | | /dev/clock | | pm module |
+        +-----------+ +------------+ +-----------+
+        /----------------------------------------\
+        | ck.h ifc                               |
+        \----------------------------------------/
+        +----------------------------------------+
+        | arch-specific clock driver(s)          |
+        +----------------------------------------+
+        
+        Since this is a kernel-only interface it doesn't belong in the kernel
+        includes -- only other modules should include this file.
+
+        For a platform to support this interface it needs at least a clock
+        driver module to implement the functions defined here and another
+        include file (asm/arch/ck.h) to enumerate the different clocks.
+
+  AUTHOR
+        gmcnutt@ridgerun.com
+
+  COPYRIGHT
+        (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+
+   This program is free software; you can redistribute  it and/or modify it
+   under  the terms of  the GNU General  Public License as published by the
+   Free Software Foundation;  either version 2 of the  License, or (at your
+   option) any later version.
+ 
+   THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+   WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ 
+   You should have received a copy of the  GNU General Public License along
+   with this program; if not, write  to the Free Software Foundation, Inc.,
+   675 Mass Ave, Cambridge, MA 02139, USA.
+ 
+   Please report all bugs and problems to the author or <support@dsplinux.net> 
+
+   key: RRGPLCR (do not remove)
+ *****************************************************************************/
+#ifndef ck_h
+#define ck_h
+
+/* This enumerates the ck_t values on a per-platform basis. */
+#include <asm/arch/arch_ck.h>
+
+/*  Clock initialization.  */
+int init_ck(void);
+
+/* For some clocks you have a choice of which "parent" clocks they are derived
+   from. Use this to select a "parent". See the platform documentation for 
+   valid combinations. */
+int ck_can_set_input(ck_t);
+int ck_set_input(ck_t ck, ck_t input);
+int ck_get_input(ck_t ck, ck_t *input);
+
+/* Use this to set a clock rate. If other clocks are derived from this one, 
+   their rates will all change too. If this is a derived clock and I can't 
+   change it to match your request unless I also change the parent clock, then
+   tough luck -- I won't change the parent automatically. I'll return an error
+   if I can't get the clock within 10% of what you want. Otherwise I'll return
+   the value I actually set it to. If I have to switch parents to get the rate
+   then I will do this automatically (since it only affects this clock and its
+   descendants). */
+int ck_can_set_rate(ck_t);
+int ck_set_rate(ck_t ck, int val_in_mhz);
+int ck_get_rate(ck_t ck);
+
+/* Use this to get a bitmap of available rates for the clock. Caller allocates 
+   the buffer and passes in the length. Clock module fills up to len bytes of 
+   the buffer & passes back actual bytes used. */
+int ck_get_rates(ck_t ck, void *buf, int len);
+
+/* Idle a clock. What happens next depends on the clock ;). For example, if 
+   you idle the ARM_CK you might well end up in sleep mode on some platforms.
+   If you try to idle a clock that doesn't support it I'll return an error. 
+   Note that idling a clock does not always take affect until certain h/w 
+   conditions are met. Consult the platform specs to learn more. */
+int ck_can_idle(ck_t);
+int ck_idle(ck_t);
+int ck_activate(ck_t);
+int ck_is_idle(ck_t);
+
+/* Enable/disable a clock. I'll return an error if the h/w doesn't support it.
+   If you disable a clock being used by an active device then you probably 
+   just screwed it. YOU are responsible for making sure this doesn't happen. 
+   Good luck. */
+int ck_can_disable(ck_t);
+int ck_enable(ck_t);
+int ck_disable(ck_t);
+int ck_is_enabled(ck_t);
+
+/* Enable/reset ARM peripherals (remove/set reset signal) */
+void ck_enable_peripherals(void);
+void ck_reset_peripherals(void);
+
+/* Generate/clear a MPU or DSP reset */
+void ck_generate_reset(reset_t reset);
+void ck_release_from_reset(reset_t reset);
+
+/* This gets a string representation of the clock's name. Useful for proc. */
+char *ck_get_name(ck_t);
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/dma.h linux-2.4.19/include/asm-arm/arch-omap1510/dma.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/dma.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/dma.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,186 @@
+/*
+ *  linux/include/asm-arm/arch-omap1510/dma.h
+ *  derived from:
+ *    linux/include/asm-arm/arch-sa1100/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *  Copyright (C) 2000 Nicolas Pitre
+ *  Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ */
+#define MAX_DMA_ADDRESS		0xffffffff
+
+/*
+ * The regular generic DMA interface is inappropriate for the
+ * OMAP DMA model.  None of the OMAP specific drivers using
+ * DMA are portable anyway so it's pointless to try to twist the
+ * regular DMA API to accommodate them.
+ */
+#define MAX_DMA_CHANNELS	0
+
+#define MAX_OMAP_DMA_CHANNELS 9  // + LCD channel, which is handled by LCD controller
+
+/*
+ * Maximum physical DMA buffer size, and smaller CUT size is a nice
+ * page size.
+ */
+#define MAX_DMA_SIZE		0x1000000  // Max size is larger, but this is OK for now
+#define CUT_DMA_SIZE		0x1000
+
+
+/*
+ * All possible OMAP1510 devices a DMA channel can be attached to.
+ *  See Table 5-7 in TRM.
+ */
+typedef enum {
+        eDMANotSync,
+        eMCSI1Tx,
+        eMCSI1Rx,
+        eI2CRx,
+        eI2CTx,
+        eExt0,             // 5
+        eExt1,
+        eMicroWireTx,
+        eAudioTx,
+        eAudioRx,
+        eOpticalTx,        // 10
+        eOpticalRx,
+        eBluetoothTx,
+        eBluetoothRx,
+        eModemTx,
+        eModemRx,          // 15
+        eModemDataTx,
+        eModemDataRx,
+        eUART3Tx,
+        eUART3Rx,
+        eCameraRx,         // 20
+        eMMCTx,
+	eMMCRx,
+        eUSBRx0 = 26,
+        eUSBRx1,
+        eUSBRx2,
+        eUSBTx0,
+	eUSBTx1,           // 30
+	eUSBTx2
+} dma_device_t;
+
+typedef enum {
+        eDmaIn,
+        eDmaOut
+} dma_direction_t;
+
+/*
+ * DMA control register structure, without LCD registers
+ */
+typedef struct {
+        volatile u16 csdp;      // channel s/d parameters -- working set (current transfer)
+        volatile u16 ccr;       // channel control -- working set
+        volatile u16 cicr;      // channel interrupt control -- working set
+        volatile u16 csr;       // channel status -- working set
+        volatile u16 cssa_l;    // source lower bits -- programming set (next transfer)
+        volatile u16 cssa_u;    // source upper bits -- programming set
+        volatile u16 cdsa_l;    // destn lower bits -- programming set
+        volatile u16 cdsa_u;    // destn upper bits -- programming set
+        volatile u16 cen;       // channel element number -- programming set
+        volatile u16 cfn;       // channel frame number -- programming set
+        volatile u16 cfi;       // channel frame index -- programming set
+        volatile u16 cei;       // channel element index -- programming set
+        volatile u16 cpc;       // channel progress counter
+        volatile u16 null[19];  // for alignment
+} dma_regs_t;
+
+/*
+  Defines for register state.
+*/
+
+#define DCSR_ERROR  0x3
+#define DCSR_SYNC_SET (1 << 6)
+#define DCCR_EN     (1 << 7)
+#define DCCR_AI     (1 << 8)
+#define DCCR_REPEAT (1 << 9)
+#define DCCR_FF     (1 << 10)
+#define DCCR_EP     (1 << 11)
+
+/*
+ * Defines for the autoidle set routine.
+ */
+
+#define DISABLE_AUTOIDLE 0
+#define ENABLE_AUTOIDLE  1
+
+typedef void (*dma_callback_t)(void *data);
+
+extern void omap_dma_autoidle_set( int set );
+extern int omap_request_dma( dma_device_t device, const char *device_id,
+                             dma_callback_t callback, void *data,
+                             dma_regs_t **regs );
+extern void omap_free_dma( dma_regs_t *regs );
+extern int omap_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
+extern dma_addr_t omap_get_dma_pos(dma_regs_t *regs);
+extern void omap_reset_dma(dma_regs_t *regs);
+extern int omap_dma_setup( dma_device_t device, dma_direction_t direction );
+extern int omap_dma_busy( void );
+
+/**
+ * 	omap_stop_dma - stop DMA in progress
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This stops DMA without clearing buffer pointers. Unlike
+ * 	omap_clear_dma() this allows subsequent use of omap_resume_dma()
+ * 	or omap_get_dma_pos().
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ **/
+
+#define omap_stop_dma(regs)	((regs)->ccr &= ~(DCCR_EN))
+
+/**
+ * 	omap_resume_dma - resume DMA on a stopped channel
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This resumes DMA on a channel previously stopped with
+ * 	omap_stop_dma().
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ **/
+
+#define omap_resume_dma(regs)	((regs)->ccr |= (DCCR_EN))
+
+/**
+ * 	omap_clear_dma - clear DMA pointers
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This clear any DMA state so the DMA engine is ready to restart
+ * 	with new buffers through omap_start_dma(). Any buffers in flight
+ * 	are discarded.
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	omap_request_dma().
+ **/
+
+#define omap_clear_dma(regs)	((regs)->ccr &= ~(DCCR_REPEAT | DCCR_AI | DCCR_EP | DCCR_EN))
+
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/fpga.h linux-2.4.19/include/asm-arm/arch-omap1510/fpga.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/fpga.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/fpga.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,54 @@
+/*
+ * File: fpga.h
+ *
+ * FPGA read/write prototypes
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.  (stevej@ridgerun.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ */
+
+#ifndef __fpga_h
+#define __fpga_h
+
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+
+// Power up Giga UART driver, turn on HID clock.
+// Turn off BT power, since we're not using it and it
+// draws power.
+#define FPGA_RESET_VALUE 0x42
+
+#define FPGA_PCR_IF_PD0         (1 << 7)
+#define FPGA_PCR_COM2_EN        (1 << 6)
+#define FPGA_PCR_COM1_EN        (1 << 5)
+#define FPGA_PCR_EXP_PD0        (1 << 4)
+#define FPGA_PCR_EXP_PD1        (1 << 3)
+#define FPGA_PCR_48MHZ_CLK      (1 << 2)
+#define FPGA_PCR_4MHZ_CLK       (1 << 1)
+#define FPGA_PCR_RSRVD_BIT0     (1 << 0)
+
+#endif
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/hardware.h linux-2.4.19/include/asm-arm/arch-omap1510/hardware.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/hardware.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/hardware.h	2003-01-15 12:37:04.000000000 +0200
@@ -0,0 +1,499 @@
+/*
+ *  linux/include/asm-arm/arch-omap1510/hardware.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   TI925 hardware map
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP1510_HARDWARE_H
+#define __ASM_ARCH_OMAP1510_HARDWARE_H
+ 
+#include <asm/arch/sizes.h>
+#include <linux/config.h>
+#include <asm/mach-types.h>
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ * ???_BASE is the virtual address
+ * ???_START is the physical address
+ */
+#define IO_BASE			0xFFFB0000                 // VA of IO 
+#define IO_SIZE			   0x40000                 // How much?
+#define IO_START		0xFFFB0000                 // PA of IO
+
+#define OMAP1510_DSP_BASE       0xE0000000                // VA
+#define OMAP1510_DSP_SIZE       0x50000                   // size
+#define OMAP1510_DSP_START      0xE0000000                // PA
+
+#define OMAP1510_DSPREG_BASE    0xE1000000                // VA
+#define OMAP1510_DSPREG_SIZE    SZ_128K                   // size
+#define OMAP1510_DSPREG_START   0xE1000000                // PA
+
+#define OMAP1510_SRAM_BASE       0xD0000000                // VA
+#define OMAP1510_SRAM_SIZE       ( SZ_128K + SZ_64K )      // size
+#define OMAP1510_SRAM_START      0x20000000                // PA
+
+// These definitions define an area of FLASH set aside
+// for the use of MTD/JFFS2. This is the area of flash
+// that a JFFS2 filesystem will reside which is mounted
+// at boot with the "root=/dev/mtdblock/0 rw"
+// command line option. The flash address used here must
+// fall within the legal range defined by rrload for storing
+// the filesystem component. This address will be sufficiently
+// deep into the overall flash range to avoid the other
+// components also stored in flash such as the bootloader,
+// the bootloader params, and the kernel.
+// The SW2 settings for the map below are:
+// 1 off, 2 off, 3 on, 4 off.
+
+// Intel flash_0, partitioned as expected by rrload.
+#define OMAP_FLASH_0_BASE	0xD8000000	// VA
+#define OMAP_FLASH_0_START	0x00000000	// PA
+#define OMAP_FLASH_0_SIZE	SZ_16M
+
+// Intel flash_1, used for cramfs or other flash file systems
+#define OMAP_FLASH_1_BASE	0xD9000000	// VA
+#define OMAP_FLASH_1_START	0x01000000	// PA
+#define OMAP_FLASH_1_SIZE	SZ_16M
+
+/*
+  There are 2 sets of general I/O -->
+  1. GPIO (shared between ARM & DSP, configured by ARM)
+  2. MPUIO which can be used only by the ARM.
+  
+  Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
+  (see 7.2.2 of the TRM for MPUIO reg definitions).
+  
+  Base address E101:5000 is reserved for ARM access of the same MPUIO control
+  regs, but via the DSP I/O map.  This address is unavailable on 1510.
+  
+  Base address FFFC:E000 is where the ARM accesses the GPIO config registers
+  directly via its own peripheral bus.
+  
+  Base address E101:E000 is where the ARM can access the same GPIO config
+  registers, but the access takes place through the ARM port interface (called
+  API or MPUI) via the DSP's peripheral bus (DSP I/O space).
+  
+  Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
+  instead of the E101:E000 addresses.  The DSP has only read access of the pin
+  control register, so this may explain the inability to write to E101:E018.
+  Try accessing pin control reg at FFFC:E018.
+ */
+#define OMAP1510_GPIO_BASE       0xfffce000
+#define OMAP1510_GPIO_START      OMAP1510_GPIO_BASE
+#define OMAP1510_GPIO_SIZE       SZ_4K
+
+#define OMAP1510_MCBSP1_BASE     0xE1011000               // VA
+#define OMAP1510_MCBSP1_SIZE     SZ_4K                    // size
+#define OMAP1510_MCBSP1_START    0xE1011000               // PA
+
+#define OMAP1510_MCBSP3_BASE     0xE1017000               // VA
+#define OMAP1510_MCBSP3_SIZE     SZ_4K                    // size
+#define OMAP1510_MCBSP3_START    0xE1017000               // PA
+
+/*
+ * Where's the flush address (for flushing D and I cache?)
+ */
+#define FLUSH_BASE              0xdf000000
+#define FLUSH_BASE_PHYS		TI925_FLASH_BASE
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE		0
+
+/*
+ * RAM definitions
+ */
+#define MAPTOPHYS(a)		((unsigned long)(a) - PAGE_OFFSET)
+#define KERNTOPHYS(a)		((unsigned long)(&a))
+#define KERNEL_BASE             (0x10008000)  
+#endif
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x)) 
+
+#define PLATFORM_ID                     0x00000045
+
+/*
+ *  TI925 memory map
+ */
+#define TI925_FLASH_BASE           0x00000000
+#define TI925_SDRAM_BASE           0x10000000
+
+
+#if 0
+#define TI925_FLASH_START          TI925_FLASH_BASE
+#define TI925_FLASH_SIZE           0x04000000
+#define TI925_FLASH_BUSWIDTH       2
+#define TI925_FLASH_SETUP_REGISTER 0x08000B00
+#endif
+
+/* ----------------------------------------------------------------------------
+ *  OMAP1510 system registers
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1510_UART1_BASE        0xfffb0000    /* "BLUETOOTH-UART" */
+#define OMAP1510_UART2_BASE        0xfffb0800    /* "MODEM-UART" */
+//#define OMAP1510_UART3_BASE        0xfffce800    /* Shared MPU/DSP UART, 1509 ESG */
+#define OMAP1510_UART3_BASE        0xfffb9800    /* Shared MPU/DSP UART, 1510 */
+#define OMAP1510_COM_MCBSP2_BASE   0xffff1000    /* Com McBSP2 */
+#define OMAP1510_AUDIO_MCBSP_BASE  0xffff1800    /* Audio McBSP2 */
+#define OMAP1510_RTC_BASE          0xffff4800    /* RTC */
+#define OMAP1510_ARMIO_BASE        0xfffb5000    /* keyboard/gpio */
+
+
+/*
+ * Configuration Registers
+ */
+#define FUNC_MUX_CTRL_0         0xfffe1000
+#define FUNC_MUX_CTRL_1         0xfffe1004
+#define FUNC_MUX_CTRL_2         0xfffe1008
+#define COMP_MODE_CTRL_0	0xfffe100c
+#define FUNC_MUX_CTRL_3         0xfffe1010
+#define FUNC_MUX_CTRL_4         0xfffe1014
+#define FUNC_MUX_CTRL_5         0xfffe1018
+#define FUNC_MUX_CTRL_6         0xfffe101c
+#define FUNC_MUX_CTRL_7         0xfffe1020
+#define FUNC_MUX_CTRL_8         0xfffe1024
+#define FUNC_MUX_CTRL_9         0xfffe1028
+#define FUNC_MUX_CTRL_A         0xfffe102c
+#define FUNC_MUX_CTRL_B         0xfffe1030
+#define FUNC_MUX_CTRL_C         0xfffe1034
+#define FUNC_MUX_CTRL_D         0xfffe1038
+
+#define PULL_DWN_CTRL_0		0xfffe1040
+#define PULL_DWN_CTRL_1		0xfffe1044
+#define PULL_DWN_CTRL_2		0xfffe1048
+#define PULL_DWN_CTRL_3		0xfffe104c
+
+#define GATE_INH_CTRL_0		0xfffe1050
+#define VOLTAGE_CTRL_0		0xfffe1060
+#define TEST_DBG_CTRL_0		0xfffe1070
+#define MOD_CONF_CTRL_0		0xfffe1080
+
+/*
+ * Traffic Controller Memory Interface Registers
+ */
+#define TCMIF_BASE              0xfffecc00
+#define IMIF_PRIO               (TCMIF_BASE + 0x00)
+#define EMIFS_PRIO_REG          (TCMIF_BASE + 0x04)
+#define EMIFF_PRIO_REG          (TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG_REG        (TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG        (TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG        (TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG        (TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG        (TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG      (TCMIF_BASE + 0x20)
+#define EMIFF_MRS               (TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1             (TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2             (TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3             (TCMIF_BASE + 0x30)
+#define TC_ENDIANISM            (TCMIF_BASE + 0x34)
+#define EMIF_CFG_DYNAMIC_WS     (TCMIF_BASE + 0x40)
+
+/*
+ * LCD Panel
+ */
+#define TI925_LCD_BASE        0xFFFEC000        // VA of the LCD controller
+#define TI925_LCD_CONTROL     (TI925_LCD_BASE)
+#define TI925_LCD_TIMING0     (TI925_LCD_BASE+0x4)
+#define TI925_LCD_TIMING1     (TI925_LCD_BASE+0x8)
+#define TI925_LCD_TIMING2     (TI925_LCD_BASE+0xc)
+#define TI925_LCD_STATUS      (TI925_LCD_BASE+0x10)
+#define TI925_LCD_SUBPANEL    (TI925_LCD_BASE+0x14)
+
+#define OMAP_LCD_CONTROL      TI925_LCD_CONTROL
+
+/* 2.9.2 MPUI Interface Registers FFFE:C900 */
+
+#define	MPUI_CTRL_REG		(volatile __u32 *)(0xfffec900)
+#define	MPUI_DEBUG_ADDR		(volatile __u32 *)(0xfffec904)
+#define	MPUI_DEBUG_DATA		(volatile __u32 *)(0xfffec908)
+#define	MPUI_DEBUG_FLAG		(volatile __u16 *)(0xfffec90c)
+#define	MPUI_STATUS_REG		(volatile __u16 *)(0xfffec910)
+#define	MPUI_DSP_STATUS_REG	(volatile __u16 *)(0xfffec914)
+#define	MPUI_DSP_BOOT_CONFIG	(volatile __u16 *)(0xfffec918)
+#define	MPUI_DSP_API_CONFIG	(volatile __u16 *)(0xfffec91c)
+
+/* 2.9.6 Traffic Controller Memory Interface Registers: */
+#define OMAP_IMIF_PRIO_REG		0xfffecc00
+#define OMAP_EMIFS_PRIO_REG		0xfffecc04
+#define OMAP_EMIFF_PRIO_REG		0xfffecc08
+#define OMAP_EMIFS_CONFIG_REG		0xfffecc0c
+#define OMAP_EMIFS_CS0_CONFIG		0xfffecc10
+#define OMAP_EMIFS_CS1_CONFIG		0xfffecc14
+#define OMAP_EMIFS_CS2_CONFIG		0xfffecc18
+#define OMAP_EMIFS_CS3_CONFIG		0xfffecc1c
+#define OMAP_EMIFF_SDRAM_CONFIG		0xfffecc20
+#define OMAP_EMIFF_MRS			0xfffecc24
+#define OMAP_TIMEOUT1			0xfffecc28
+#define OMAP_TIMEOUT2			0xfffecc2c
+#define OMAP_TIMEOUT3			0xfffecc30
+#define OMAP_ENDIANISM			0xfffecc34
+
+/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
+#define OMAP_EMIFS_CONFIG_FR		(1 << 4)
+#define OMAP_EMIFS_CONFIG_PDE		(1 << 3)
+#define OMAP_EMIFS_CONFIG_PWD_EN	(1 << 2)
+#define OMAP_EMIFS_CONFIG_BM		(1 << 1)
+#define OMAP_EMIFS_CONFIG_WP		(1 << 0)
+
+/*
+ * Memory chunk set aside for the Framebuffer in SRAM
+ */
+#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
+
+
+/* 
+ * DMA
+ */
+
+#define OMAP1510_DMA_BASE 0xFFFED800
+#define OMAP_DMA_BASE     OMAP1510_DMA_BASE
+
+/* Global Register selection */
+#define NO_GLOBAL_DMA_ACCESS 0
+
+/* Channel select field
+ * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
+ */
+#define LCD_CHANNEL 0xc
+
+/* Register Select Field (LCD) */
+#define DMA_LCD_CTRL        0
+#define DMA_LCD_TOP_F1_L    1
+#define DMA_LCD_TOP_F1_U    2
+#define DMA_LCD_BOT_F1_L    3
+#define DMA_LCD_BOT_F1_U    4
+
+#define LCD_FRAME_MODE             (1<<0)
+#define LCD_FRAME_IT_IE            (1<<1)
+#define LCD_BUS_ERROR_IT_IE        (1<<2)
+#define LCD_FRAME_1_IT_COND        (1<<3)
+#define LCD_FRAME_2_IT_COND        (1<<4) 
+#define LCD_BUS_ERROR_IT_COND      (1<<5)
+#define LCD_SOURCE_IMIF            (1<<6)
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 Interrupt Handlers
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define OMAP_IH1_BASE          0xfffecb00
+#define OMAP_IH2_BASE          0xfffe0000
+#define OMAP1510_ITR               0x0
+#define OMAP1510_MASK              0x4
+
+#define INTERRUPT_HANDLER_BASE   OMAP_IH1_BASE
+#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
+#define INTERRUPT_MASK_REGISTER  OMAP1510_MASK
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIMERS
+ * ---------------------------------------------------------------------------
+ * 
+ */
+
+#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
+
+#define OMAP1510_TIMER1_BASE 0xfffec500
+#define OMAP1510_TIMER2_BASE 0xfffec600
+#define OMAP1510_TIMER3_BASE 0xfffec700
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 GPIO (only)
+ * ---------------------------------------------------------------------------
+ * 
+ */
+#define GPIO_DATA_INPUT_REG  (OMAP1510_GPIO_BASE + 0x0)
+#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4)
+#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8)
+#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc)
+#define GPIO_INT_MASK_REG    (OMAP1510_GPIO_BASE + 0x10)
+#define GPIO_INT_STATUS_REG  (OMAP1510_GPIO_BASE + 0x14)
+#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18)
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIPB (only)
+ * ---------------------------------------------------------------------------
+ * 
+ */
+#define TIPB_PUBLIC_CNTL_BASE          0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL_REG       (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE         0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL_REG      (TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/* ---------------------------------------------------------------------------
+ *  Differentiating processor versions for those who care.
+ * ---------------------------------------------------------------------------
+ * 
+ */
+#define OMAP1509 0
+#define OMAP1510 1
+
+#define OMAP1510_ID_CODE_REG 0xfffed404
+
+#ifndef __ASSEMBLY__
+int cpu_type(void);
+#endif
+
+/*
+ * EVM Implementation Specifics.
+ * 
+ * *** NOTE ***
+ * Any definitions in these files should be prefixed by an identifier -
+ * eg. OMAP1510P1_FLASH0_BASE .
+ *
+ */
+#ifdef CONFIG_OMAP_INNOVATOR
+#include "innovator.h"
+#endif
+
+#ifdef CONFIG_OMAP_1510P1
+#include "omap1510p1.h"
+#endif
+
+/*****************************************************************************/
+
+#define CLKGEN_RESET_BASE  (0xfffece00)
+#define ARM_CKCTL          (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)    
+#define ARM_IDLECT1        (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)    
+#define ARM_IDLECT2        (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)    
+#define ARM_EWUPCT         (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)    
+#define ARM_RSTCT1         (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)    
+#define ARM_RSTCT2         (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)    
+#define ARM_SYSST          (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
+
+
+#define CK_CLKIN     12 /* MHz */
+#define CK_RATEF     1
+#define CK_IDLEF     2
+#define CK_ENABLEF    4
+#define CK_SELECTF   8
+#define CK_DPLL1     ((volatile __u16 *)0xfffecf00)
+#define SETARM_IDLE_SHIFT
+
+/* ARM_CKCTL bit shifts */
+#define PERDIV          0
+#define LCDDIV          2
+#define ARMDIV          4
+#define DSPDIV          6
+#define TCDIV           8
+#define DSPMMUDIV       10
+#define ARM_TIMXO       12
+#define EN_DSPCK        13
+#define ARM_INTHCK_SEL  14 /* REVISIT -- where is this used? */
+
+#define ARM_CKCTL_RSRVD_BIT15		(1 << 15)
+#define ARM_CKCTL_ARM_INTHCK_SEL	(1 << 14)
+#define ARM_CKCTL_EN_DSPCK		(1 << 13)
+#define ARM_CKCTL_ARM_TIMXO		(1 << 12)
+#define ARM_CKCTL_DSPMMU_DIV1		(1 << 11)
+#define ARM_CKCTL_DSPMMU_DIV2		(1 << 10)
+#define ARM_CKCTL_TCDIV1		(1 << 9)
+#define ARM_CKCTL_TCDIV2		(1 << 8)
+#define ARM_CKCTL_DSPDIV1		(1 << 7)
+#define ARM_CKCTL_DSPDIV0		(1 << 6)
+#define ARM_CKCTL_ARMDIV1		(1 << 5)
+#define ARM_CKCTL_ARMDIV0		(1 << 4)
+#define ARM_CKCTL_LCDDIV1		(1 << 3)
+#define ARM_CKCTL_LCDDIV0		(1 << 2)
+#define ARM_CKCTL_PERDIV1		(1 << 1)
+#define ARM_CKCTL_PERDIV0		(1 << 0)
+
+/* ARM_IDLECT1 bit shifts */
+#define IDLWDT_ARM      0
+#define IDLXORP_ARM     1
+#define IDLPER_ARM      2
+#define IDLLCD_ARM      3
+#define IDLLB_ARM       4
+#define IDLHSAB_ARM     5
+#define IDLIF_ARM       6
+#define IDLDPLL_ARM     7
+#define IDLAPI_ARM      8
+#define IDLTIM_ARM      9
+#define SETARM_IDLE     11
+
+/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK        0
+#define EN_XORPCK       1
+#define EN_PERCK        2
+#define EN_LCDCK        3
+#define EN_LBCK         4
+#define EN_HSABCK       5
+#define EN_APICK        6
+#define EN_TIMCK        7
+#define DMACK_REQ       8
+#define EN_GPIOCK       9
+#define EN_LBFREECK     10
+
+#define ARM_RSTCT1_SW_RST       (1 << 3)
+#define ARM_RSTCT1_DSP_RST      (1 << 2)
+#define ARM_RSTCT1_DSP_EN       (1 << 1)
+#define ARM_RSTCT1_ARM_RST      (1 << 0)
+
+#define ARM_SYSST_RSRVD_BIT15	(1 << 15)
+#define ARM_SYSST_RSRVD_BIT14	(1 << 14)
+#define ARM_SYSST_CLOCK_SELECT2	(1 << 13)
+#define ARM_SYSST_CLOCK_SELECT1	(1 << 12)
+#define ARM_SYSST_CLOCK_SELECT0	(1 << 11)
+#define ARM_SYSST_RSRVD_BIT10	(1 << 10)
+#define ARM_SYSST_RSRVD_BIT9	(1 << 9)
+#define ARM_SYSST_RSRVD_BIT8	(1 << 8)
+#define ARM_SYSST_RSRVD_BIT7	(1 << 7)
+#define ARM_SYSST_IDLE_DSP	(1 << 6)
+#define ARM_SYSST_POR		(1 << 5)
+#define ARM_SYSST_EXT_RST	(1 << 4)
+#define ARM_SYSST_ARM_MCRST	(1 << 3)
+#define ARM_SYSST_ARM_WDRST	(1 << 2)
+#define ARM_SYSST_GLOB_SWRST	(1 << 1)
+#define ARM_SYSST_DSP_WDRST	(1 << 0)
+
+/*****************************************************************************/
+
+// OMAP INTERRUPT REGISTERS
+#define IRQ_ITR			0x00
+#define IRQ_MIR			0x04
+#define IRQ_SIR_IRQ		0x10
+#define IRQ_SIR_FIQ		0x14
+#define IRQ_CONTROL_REG		0x18
+#define IRQ_ISR			0x9c
+#define IRQ_ILR0		0x1c
+
+// INTERRUPT LEVEL REGISTER BITS
+#define ILR_PRIORITY_MASK 	(0x3c)
+#define ILR_PRIORITY_SHIFT	(2)
+#define ILR_LEVEL_TRIGGER	(1<<1)
+#define ILR_FIQ			(1<<0)
+
+#define IRQ_LEVEL_INT		1
+#define IRQ_EDGE_INT		0
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/innovator.h linux-2.4.19/include/asm-arm/arch-omap1510/innovator.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/innovator.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/innovator.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,41 @@
+/*
+ *  linux/include/asm-arm/arch-omap1510/innovator.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP1510_INNOVATOR_H
+#define __ASM_ARCH_OMAP1510_INNOVATOR_H
+
+/*
+ * NOTE:  ALL DEFINITIONS IN THIS FILE NEED TO BE PREVIXED BY IDENTIFIER
+ *        INNOVATOR_ since they are specific to the EVM and not the chip.
+ */
+
+/*
+ * Innovator based heavily on OMAP1510DC P1 EVM.  At this time, it is 
+ * more straight forward to redefine deltas than to duplicate.
+ */
+#include "omap1510p1.h" 
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/io.h linux-2.4.19/include/asm-arm/arch-omap1510/io.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/io.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/io.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,33 @@
+/*
+ * linux/include/asm-arm/arch-omap1510/io.h
+ *
+ * Copied from linux/include/asm-arm/arch-sa1100/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997	RMK	Created.
+ *  07-04-1999	RMK	Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many 
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)			(PCIO_BASE + (a))
+#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_isa(a)		((unsigned long)(a))
+
+/*
+ * Generic virtual read/write
+ */
+#define __arch_getw(a)		(*(volatile unsigned short *)(a))
+#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
+
+#define iomem_valid_addr(iomem,sz)	(1)
+#define iomem_to_phys(iomem)		(iomem)
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/irq.h linux-2.4.19/include/asm-arm/arch-omap1510/irq.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/irq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/irq.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-omap1510/irq.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   TI925 irq interface
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+/**
+ * Define this if someone or something is mysteriously clearing the ethernet
+ * bit in the FPGA interrupt mask register.
+ */
+
+extern void IRQ_interrupt(void);
+extern void timer_IRQ_interrupt(void);
+extern void fast_IRQ_interrupt(void);
+extern void bad_IRQ_interrupt(void);
+extern void probe_IRQ_interrupt(void);
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/irqs.h linux-2.4.19/include/asm-arm/arch-omap1510/irqs.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/irqs.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/irqs.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,145 @@
+/*
+ *  linux/include/asm-arm/arch-ti925/omap1510/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_OMAP1510_IRQS_H
+#define __ASM_ARCH_OMAP1510_IRQS_H
+/* ---------------------------------------------------------------------------
+ *  Interrupts
+ * ---------------------------------------------------------------------------
+ */
+
+/* These interrupt vectors are for the OMAP1510.
+ * The interrupt vectors for the OMAP1509/OMAP1510DC are different.
+ */
+
+/* 
+ *  IRQ Numbers for INT1
+ * 
+ */
+#define INT_IH2_IRQ      0
+#define INT_CAMERA       1 
+#define INT_RES2         2 
+#define INT_FIQ          3
+#define INT_SPI_TX       4
+#define INT_SPI_RX       5
+#define INT_RTDX         6
+#define INT_DSP_MMU_ABORT 7
+#define INT_HOST         8
+#define INT_ABORT        9
+#define INT_DSP_MAILBOX1 10
+#define INT_DSP_MAILBOX2 11
+#define INT_RES12        12
+#define INT_BRIDGE_PRIV  13
+#define INT_GPIO         14
+#define INT_UART3        15
+#define INT_TIMER3       16
+#define INT_LB_MMU       17
+#define INT_RES18        18
+#define INT_DMA_CH0_6    19
+#define INT_DMA_CH1_7    20
+#define INT_DMA_CH2_8    21
+#define INT_DMA_CH3      22
+#define INT_DMA_CH4      23
+#define INT_DMA_CH5      24
+#define INT_DMA_LCD      25
+#define INT_TIMER1       26
+#define INT_WD_TIMER     27
+#define INT_BRIDGE_PUB   28
+#define INT_LOCAL_BUS    29
+#define INT_TIMER2       30
+#define INT_LCD_CTRL     31
+
+/* 
+ * IRQ Numbers for Interrupt Handler 2
+ */
+#define IH2_BASE 32
+ 
+#define INT_HW_ERRORS 0 + IH2_BASE
+#define INT_KEYBOARD  1 + IH2_BASE
+#define INT_uWireTX   2 + IH2_BASE
+#define INT_uWireRX   3 + IH2_BASE
+#define INT_I2C       4 + IH2_BASE
+#define INT_MPUIO     5 + IH2_BASE
+#define INT_McBSP3TX  10 + IH2_BASE
+#define INT_McBSP3RX  11 + IH2_BASE
+#define INT_McBSP1TX  12 + IH2_BASE
+#define INT_McBSP1RX  13 + IH2_BASE
+#define INT_UART1     14 + IH2_BASE // Bluetooth
+#define INT_UART2     15 + IH2_BASE
+#define INT_BT_MCS1TX 16 + IH2_BASE
+#define INT_BT_MCS1RX 17 + IH2_BASE
+#define INT_OS_32kHz_TIMER 22 + IH2_BASE
+#define	TIMER_IRQ	INT_OS_32kHz_TIMER
+#define INT_MMC         23 + IH2_BASE
+#define INT_GAUGE_32K   24 + IH2_BASE
+#define INT_DSP_MMU     28 + IH2_BASE
+#define INT_USB_GENI    29 + IH2_BASE
+#define INT_USB_SBI1    30 + IH2_BASE
+#define INT_COM_SPI_RO  31 + IH2_BASE
+
+/*
+ * IRQ Numbers for interrupts muxed through GPIO
+ */
+#define IH_GPIO_BASE 64
+#define INT_GPIO0    (IH_GPIO_BASE + 0)
+#define INT_GPIO1    (IH_GPIO_BASE + 1)
+#define INT_GPIO2    (IH_GPIO_BASE + 2)
+#define INT_GPIO3    (IH_GPIO_BASE + 3)
+#define INT_GPIO4    (IH_GPIO_BASE + 4)
+#define	FPGA_IRQ	4	// REVISIT: ??? schematics have FPGA_INT -> GPIO_13/KBR_5
+#define INT_GPIO5    (IH_GPIO_BASE + 5)
+#define INT_GPIO6    (IH_GPIO_BASE + 6)
+#define INT_GPIO7    (IH_GPIO_BASE + 7)
+#define INT_GPIO8    (IH_GPIO_BASE + 8)
+#define INT_GPIO9    (IH_GPIO_BASE + 9)
+#define INT_GPIO10   (IH_GPIO_BASE + 10)
+#define INT_GPIO11   (IH_GPIO_BASE + 11)
+#define INT_GPIO12   (IH_GPIO_BASE + 12)
+#define INT_FPGA     (IH_GPIO_BASE + 13)
+#define INT_GPIO14   (IH_GPIO_BASE + 14)
+#define INT_GPIO15   (IH_GPIO_BASE + 15)
+
+/*
+ * IRQ Numbers for interrupts muxed through the FPGA
+ */
+#define IH_FPGA_BASE    80
+#define INT_FPGA_ATN    (IH_FPGA_BASE + 0)
+#define INT_FPGA_ACK    (IH_FPGA_BASE + 1)
+#define INT_FPGA2       (IH_FPGA_BASE + 2)
+#define INT_FPGA3       (IH_FPGA_BASE + 3)
+#define INT_FPGA4       (IH_FPGA_BASE + 4)
+#define INT_FPGA5       (IH_FPGA_BASE + 5)
+#define INT_FPGA6       (IH_FPGA_BASE + 6)
+#define INT_FPGA7       (IH_FPGA_BASE + 7)
+#define INT_FPGA8       (IH_FPGA_BASE + 8)
+#define INT_FPGA9       (IH_FPGA_BASE + 9)
+#define INT_FPGA10      (IH_FPGA_BASE + 10)
+#define INT_FPGA11      (IH_FPGA_BASE + 11)
+#define INT_FPGA12      (IH_FPGA_BASE + 12)
+#define INT_ETHER       (IH_FPGA_BASE + 13)
+#define INT_FPGAUART1   (IH_FPGA_BASE + 14)
+#define INT_FPGAUART2   (IH_FPGA_BASE + 15)
+
+#define MAXIRQNUM                       (IH_FPGA_BASE + 15)
+#define MAXFIQNUM                       MAXIRQNUM
+#define MAXSWINUM                       MAXIRQNUM
+
+#define NR_IRQS                         (MAXIRQNUM + 1)
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/keyboard.h linux-2.4.19/include/asm-arm/arch-omap1510/keyboard.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/keyboard.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/keyboard.h	2003-01-15 12:37:22.000000000 +0200
@@ -0,0 +1,57 @@
+/*
+ * linux/include/asm-arm/arch-omap1510/keyboard.h
+ *
+ * Keyboard driver definitions for OMAP1510 architecture
+ *
+ * Copyright (C) 1998-2001 Russell King
+ * (C) 1998 Phil Blundell
+ */
+#include <linux/config.h>
+#include <linux/ioport.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+
+#define kbd_disable_irq()	do { } while (0)
+#define kbd_enable_irq()	do { } while (0)
+
+extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
+extern int pckbd_getkeycode(unsigned int scancode);
+extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
+			   char raw_mode);
+extern char pckbd_unexpected_up(unsigned char keycode);
+extern void pckbd_leds(unsigned char leds);
+extern void pckbd_init_hw(void);
+extern unsigned char pckbd_sysrq_xlate[128];
+
+static inline void kbd_init_hw(void)
+{
+	k_setkeycode    = pckbd_setkeycode;
+	k_getkeycode    = pckbd_getkeycode;
+	k_translate     = pckbd_translate;
+	k_unexpected_up = pckbd_unexpected_up;
+	k_leds          = pckbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+	k_sysrq_key     = 0x54;
+	k_sysrq_xlate   = pckbd_sysrq_xlate;
+#endif
+}
+
+/*
+ * The rest of this file is to do with supporting pc_keyb.c
+ */
+
+/* resource allocation */
+#define kbd_request_region()		(0)
+#define kbd_request_irq(handler)	(0)
+
+/* How to access the keyboard macros on this platform.  */
+#define kbd_read_input()		(0)
+#define kbd_read_status()		(0)
+#define kbd_write_output(val)		(0)
+#define kbd_write_command(val)		(0)
+
+/* Some stoneage hardware needs delays after some operations.  */
+#define kbd_pause() do { } while(0)
+
+#define aux_request_irq(hand,dev_id) (0)
+#define aux_free_irq(dev_id) (0)
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/mcbsp.h linux-2.4.19/include/asm-arm/arch-omap1510/mcbsp.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/mcbsp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/mcbsp.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,146 @@
+/*
+ * File: mcbsp.h
+ *
+ * Defines for Multi-Channel Buffered Serial Port
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Please report all bugs/problems to the author or <support@dsplinux.net>
+ *
+ * key: RRGPLCR (do not remove)
+ *
+ */
+#ifndef mcbsp_h
+#define mcbsp_h
+
+#include <asm/arch/hardware.h>
+
+#define AUDIO_DRR2  (OMAP1510_MCBSP1_BASE + 0x800)
+#define AUDIO_DRR1  (OMAP1510_MCBSP1_BASE + 0x802)
+#define AUDIO_DXR2  (OMAP1510_MCBSP1_BASE + 0x804)
+#define AUDIO_DXR1  (OMAP1510_MCBSP1_BASE + 0x806)
+#define AUDIO_SPCR2 (OMAP1510_MCBSP1_BASE + 0x808)
+#define AUDIO_SPCR1 (OMAP1510_MCBSP1_BASE + 0x80a)
+#define AUDIO_RCR2  (OMAP1510_MCBSP1_BASE + 0x80c)
+#define AUDIO_RCR1  (OMAP1510_MCBSP1_BASE + 0x80e)
+#define AUDIO_XCR2  (OMAP1510_MCBSP1_BASE + 0x810)
+#define AUDIO_XCR1  (OMAP1510_MCBSP1_BASE + 0x812)
+#define AUDIO_SRGR2 (OMAP1510_MCBSP1_BASE + 0x814)
+#define AUDIO_SRGR1 (OMAP1510_MCBSP1_BASE + 0x816)
+#define AUDIO_MCR2  (OMAP1510_MCBSP1_BASE + 0x818)
+#define AUDIO_MCR1  (OMAP1510_MCBSP1_BASE + 0x81a)
+#define AUDIO_RCERA (OMAP1510_MCBSP1_BASE + 0x81c)
+#define AUDIO_RCERB (OMAP1510_MCBSP1_BASE + 0x81e)
+#define AUDIO_XCERA (OMAP1510_MCBSP1_BASE + 0x820)
+#define AUDIO_XCERB (OMAP1510_MCBSP1_BASE + 0x822)
+#define AUDIO_PCR0  (OMAP1510_MCBSP1_BASE + 0x824)
+
+/************************** McBSP SPCR1 bit definitions ***********************/
+#define RRST                    0x0001
+#define RRDY                    0x0002
+#define RFULL                   0x0004
+#define RSYNC_ERR               0x0008
+#define RINTM(value)            (value<<4)       /* bits 4:5   */
+#define ABIS                    0x0040
+#define DXENA                   0x0080
+#define CLKSTP(value)           (value<<11)      /* bits 11:12 */
+#define RJUST(value)            (value<<13)      /* bits 13:14 */
+#define DLB                     0x8000
+
+/************************** McBSP SPCR2 bit definitions ***********************/
+#define XRST           0x0001
+#define XRDY           0x0002
+#define XEMPTY         0x0004
+#define XSYNC_ERR      0x0008
+#define XINTM(value)   (value<<4)           /* bits 4:5   */
+#define GRST           0x0040
+#define FRST           0x0080
+#define SOFT           0x0100
+#define FREE           0x0200
+
+/************************** McBSP PCR bit definitions *************************/
+#define CLKRP          0x0001
+#define CLKXP          0x0002
+#define FSRP           0x0004
+#define FSXP           0x0008
+#define DR_STAT        0x0010
+#define DX_STAT        0x0020
+#define CLKS_STAT      0x0040
+#define SCLKME         0x0080
+#define CLKRM          0x0100
+#define CLKXM          0x0200
+#define FSRM           0x0400
+#define FSXM           0x0800
+#define RIOEN          0x1000 
+#define XIOEN          0x2000
+#define IDLE_EN        0x4000
+
+/************************** McBSP RCR1 bit definitions ************************/
+#define RWDLEN1(value)      (value<<5)      /* Bits 5:7  */
+#define RFRLEN1(value)      (value<<8)      /* Bits 8:14 */
+
+/************************** McBSP XCR1 bit definitions ************************/
+#define XWDLEN1(value)      (value<<5)      /* Bits 5:7  */
+#define XFRLEN1(value)      (value<<8)      /* Bits 8:14 */
+
+/*************************** McBSP RCR2 bit definitions ***********************/
+#define RDATDLY(value)      (value)         /* Bits 0:1 */
+#define RFIG                0x0004
+#define RCOMPAND(value)     (value<<3)      /* Bits 3:4 */
+#define RWDLEN2(value)      (value<<5)      /* Bits 5:7 */
+#define RFRLEN2(value)      (value<<8)      /* Bits 8:14 */
+#define RPHASE              0x8000
+
+/*************************** McBSP XCR2 bit definitions ***********************/
+#define XDATDLY(value)      (value)         /* Bits 0:1 */
+#define XFIG                0x0004
+#define XCOMPAND(value)     (value<<3)      /* Bits 3:4 */
+#define XWDLEN2(value)      (value<<5)      /* Bits 5:7 */
+#define XFRLEN2(value)      (value<<8)      /* Bits 8:14 */
+#define XPHASE              0x8000
+
+/************************* McBSP SRGR1 bit definitions ************************/
+#define CLKGDV(value)      (value)         /* Bits 0:7 */
+#define FWID(value)        (value<<8)      /* Bits 8:15 */
+
+/************************* McBSP SRGR2 bit definitions ************************/
+#define FPER(value)       (value)         /* Bits 0:11 */
+#define FSGM              0x1000
+#define CLKSM             0x2000
+#define CLKSP             0x4000
+#define GSYNC             0x8000
+
+/************************* McBSP MCR1 bit definitions *************************/
+#define RMCM              0x0001
+#define RCBLK(value)      (value<<2)      /* Bits 2:4 */
+#define RPABLK(value)     (value<<5)      /* Bits 5:6 */
+#define RPBBLK(value)     (value<<7)      /* Bits 7:8 */
+
+/************************* McBSP MCR2 bit definitions *************************/
+#define XMCM(value)       (value)         /* Bits 0:1 */
+#define XCBLK(value)      (value<<2)      /* Bits 2:4 */
+#define XPABLK(value)     (value<<5)      /* Bits 5:6 */
+#define XPBBLK(value)     (value<<7)      /* Bits 7:8 */
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/memory.h linux-2.4.19/include/asm-arm/arch-omap1510/memory.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/memory.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/memory.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,72 @@
+/*
+ *  linux/include/asm-arm/arch-ti925/memory.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ * memory map  
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * This file was derived from 
+ * linux/include/asm-arm/arch-intergrator/memory.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ */
+
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE	(0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET     (0xC0000000UL)
+#define PHYS_OFFSET     (0x10000000UL)
+/*
+ * The DRAM is contiguous.
+ */
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#define PHYS_TO_NID(addr) (0)
+#endif
+ 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/omap1510p1.h linux-2.4.19/include/asm-arm/arch-omap1510/omap1510p1.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/omap1510p1.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/omap1510p1.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,85 @@
+/*
+ *  linux/include/asm-arm/arch-ti925/omap1510/omap1510p1.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP1510_OMAP1510P1_H
+#define __ASM_ARCH_OMAP1510_OMAP1510P1_H
+
+/*
+ * NOTE:  ALL NEW DEFINITIONS IN THIS FILE NEED TO BE PREVIXED BY IDENTIFIER
+ *        OMAP1510P1 since they are specific to the EVM and not the chip.
+ */
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 FPGA
+ * ---------------------------------------------------------------------------
+ * 
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define OMAP1510P1_FPGA_BASE              0xE8000000                 // VA
+#define OMAP1510P1_FPGA_SIZE              SZ_4K                      // SIZE
+#define OMAP1510P1_FPGA_START             0x08000000                 // PA   
+
+#define OMAP1510P1_FPGA_REV_LOW           (OMAP1510P1_FPGA_BASE + 0x0)   /* Revision */ 
+#define OMAP1510P1_FPGA_REV_HIGH          (OMAP1510P1_FPGA_BASE + 0x1)   /* Revision */
+#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2)
+#define OMAP1510P1_FPGA_LED_DIGIT         (OMAP1510P1_FPGA_BASE + 0x3)
+#define OMAP1510P1_FPGA_HID_SPI           (OMAP1510P1_FPGA_BASE + 0x4)
+#define OMAP1510P1_FPGA_POWER             (OMAP1510P1_FPGA_BASE + 0x5)
+#define OMAP1510P1_FPGA_ISR_LO            (OMAP1510P1_FPGA_BASE + 0x6)   /* Interrupt Status Register (Low) */ 
+#define OMAP1510P1_FPGA_ISR_HI            (OMAP1510P1_FPGA_BASE + 0x7)   /* Interrupt Status Register (High) */
+#define OMAP1510P1_FPGA_IMR_LO            (OMAP1510P1_FPGA_BASE + 0x8)   /* Interrupt Mask Register (Low) */
+#define OMAP1510P1_FPGA_IMR_HI            (OMAP1510P1_FPGA_BASE + 0x9)   /* Interrupt Mask Register (High) */
+#define OMAP1510P1_FPGA_HOST_RESET        (OMAP1510P1_FPGA_BASE + 0xa)
+#define OMAP1510P1_FPGA_RST               (OMAP1510P1_FPGA_BASE + 0xb) /* Peripheral Reset */
+#define OMAP1510P1_FPGA_AUDIO             (OMAP1510P1_FPGA_BASE + 0xc)
+#define OMAP1510P1_FPGA_DIP               (OMAP1510P1_FPGA_BASE + 0xe)
+#define OMAP1510P1_FPGA_FPGA_IO           (OMAP1510P1_FPGA_BASE + 0xf)
+#define OMAP1510P1_FPGA_UART1             (OMAP1510P1_FPGA_BASE + 0x14)
+#define OMAP1510P1_FPGA_UART2             (OMAP1510P1_FPGA_BASE + 0x15)
+#define OMAP1510P1_FPGA_OMAP1510_STATUS   (OMAP1510P1_FPGA_BASE + 0x16)
+#define OMAP1510P1_FPGA_BOARD_REV         (OMAP1510P1_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA               (OMAP1510P1_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS             (OMAP1510P1_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL            (OMAP1510P1_FPGA_BASE + 0x102)
+
+#define OMAP1510P1_FPGA_TOUCHSCREEN	(OMAP1510P1_FPGA_BASE + 0x204)
+
+#define OMAP1510P1_FPGA_ETHR_BASE         0xE8000300
+
+// Power up Giga UART driver, turn on HID clock.
+// Turn off BT power, since we're not using it and it
+// draws power.
+#define OMAP1510P1_FPGA_RESET_VALUE       0x42
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE                 D256M_1X16_4B
+#endif
+
+#define OMAP1510P1_IMIF_PRI_VALUE	  0x00
+#define OMAP1510P1_EMIFS_PRI_VALUE	  0x00
+#define OMAP1510P1_EMIFF_PRI_VALUE	  0x00
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/omap_pm.h linux-2.4.19/include/asm-arm/arch-omap1510/omap_pm.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/omap_pm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/omap_pm.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,84 @@
+/*
+ * omap_pm.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ *        This file defines the interface to the TI925-specific Power 
+ *        Management (PM) module.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: Gordon McNutt <gmcnutt@ridgerun.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef OMAP_PM_H
+#define OMAP_PM_H
+
+#include <linux/ioctl.h>
+
+#define OMAP_PM__IOCTL__MAGIC      0xb2
+#define OMAP_PM__IOCTL__SUSPEND    _IO(OMAP_PM__IOCTL__MAGIC, 0)
+#define OMAP_PM__IOCTL__RESUME     _IO(OMAP_PM__IOCTL__MAGIC, 1)
+#define OMAP_PM__IOCTL__ENABLE     _IO(OMAP_PM__IOCTL__MAGIC, 2)
+#define OMAP_PM__IOCTL__DISABLE    _IO(OMAP_PM__IOCTL__MAGIC, 3)
+
+// Set/Get LCD and DSP are in MHz
+#define OMAP_PM__IOCTL__SET_LCD    _IOR(OMAP_PM__IOCTL__MAGIC, 4, sizeof(unsigned long))
+#define OMAP_PM__IOCTL__GET_LCD    _IOW(OMAP_PM__IOCTL__MAGIC, 5, sizeof(unsigned long))
+#define OMAP_PM__IOCTL__SET_DSP    _IOR(OMAP_PM__IOCTL__MAGIC, 6, sizeof(unsigned long))
+#define OMAP_PM__IOCTL__GET_DSP    _IOW(OMAP_PM__IOCTL__MAGIC, 7, sizeof(unsigned long))
+
+// Set/Get Time is in milliseconds
+#define OMAP_PM__IOCTL__SET_TIME   _IOR(OMAP_PM__IOCTL__MAGIC, 8, sizeof(unsigned long))
+#define OMAP_PM__IOCTL__GET_TIME   _IOW(OMAP_PM__IOCTL__MAGIC, 9, sizeof(unsigned long))
+
+#if NOT_PLUMBED_YET
+
+// Set/Get Blank time is in seconds
+#define OMAP_PM__IOCTL__SET_BLANK  _IOR(OMAP_PM__IOCTL__MAGIC, 10, sizeof(unsigned long))
+#define OMAP_PM__IOCTL__GET_BLANK  _IOW(OMAP_PM__IOCTL__MAGIC, 11, sizeof(unsigned long))
+
+#endif  // not plumbed yet
+
+#define OMAP_PM__IOCTL__MAX        7
+
+#ifdef __KERNEL__
+
+// Functions exposed for /proc interface
+
+/*
+  These set/get a value for one of the settable parameters.  "cmd"
+  is one of the ioctl defines from above.
+*/
+int pm_set_rate(unsigned int cmd, unsigned long value);
+int pm_get_rate(unsigned int cmd);
+
+/*  These enable/disable the more aggressive PM */
+void pm_enable(void);
+void pm_disable(void);
+
+/*  This returns a 1 if the more aggressive PM is enabled, 0 otherwise  */
+int pm_enabled(void);
+
+#endif  /*  __KERNEL  */
+
+#endif  /* OMAP_PM_H  */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/param.h linux-2.4.19/include/asm-arm/arch-omap1510/param.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/param.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/param.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define HZ 100
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/pm.h linux-2.4.19/include/asm-arm/arch-omap1510/pm.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/pm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/pm.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,155 @@
+/*
+ * FILE NAME include/asm/arch/pm.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: MontaVista Software, Inc.
+ *         support@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * List of global OMAP registers to preserve.  All registers are 16 bits
+ * and must be accessed with 16 read/writes.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+#ifndef __ASM_ARCH_OMAP1510_PM_H
+#define __ASM_ARCH_OMAP1510_PM_H  
+
+#define ARM_REG_BASE  		(0xfffece00)
+#define ARM_ASM_IDLECT1        	(ARM_REG_BASE + 0x4)    
+#define ARM_ASM_IDLECT2        	(ARM_REG_BASE + 0x8)    
+#define ARM_ASM_RSTCT1         	(ARM_REG_BASE + 0x10)    
+#define ARM_ASM_RSTCT2         	(ARM_REG_BASE + 0x14)    
+#define ARM_ASM_SYSST          	(ARM_REG_BASE + 0x18)
+/*
+ * Traffic Controller Memory Interface Registers
+ */
+#define TCMIF_BASE              0xfffecc00
+#define EMIFS_ASM_CONFIG_REG    (TCMIF_BASE + 0x0c)
+#define EMIFF_ASM_SDRAM_CONFIG  (TCMIF_BASE + 0x20)
+#define IRQ_MIR1	(volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR)
+#define IRQ_MIR2	(volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR)
+
+#define IDLE_WAIT_CYCLES		0x000000ff
+#define PERIPHERAL_ENABLE		0x2
+#define BIG_SLEEP_REQUEST		0x0cc5
+#define IDLE_LOOP_REQUEST		0x0c00
+#define SELF_REFRESH_MODE		0x0c000001
+#define IDLE_EMIFS_REQUEST		0xc
+#define IDLE_CLOCK_DOMAINS		0x2
+#define MODEM_32K_EN			0x1
+
+#ifndef __ASSEMBLER__
+extern void omap_pm_suspend(void);
+extern int omap1510_cpu_suspend(void);
+extern int omap1510_idle_loop_suspend(void);
+extern struct async_struct *omap_pm_sercons;
+extern unsigned int serial_in(struct async_struct *, int);
+extern unsigned int serial_out(struct async_struct *, int, int);
+
+#define OMAP1510_SRAM_IDLE_SUSPEND	0xd002F000
+#define OMAP1510_SRAM_API_SUSPEND	0xd002F200
+#define CPU_SUSPEND_SIZE	200
+#define ARM_REG_BASE  		(0xfffece00)
+#define ARM_ASM_IDLECT1        	(ARM_REG_BASE + 0x4)    
+#define ARM_ASM_IDLECT2        	(ARM_REG_BASE + 0x8)    
+#define ARM_ASM_RSTCT1         	(ARM_REG_BASE + 0x10)    
+#define ARM_ASM_RSTCT2         	(ARM_REG_BASE + 0x14)    
+#define ARM_ASM_SYSST          	(ARM_REG_BASE + 0x18)
+
+#define ULPD_REG_BASE		(0xfffe0800)
+#define ULPD_IT_STATUS_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x14)
+#define ULPD_CLOCK_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x30)
+#define ULPD_SOFT_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x34)
+#define ULPD_DPLL_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x40)
+#define ULPD_POWER_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x50)
+
+#define TCMIF_BASE              0xfffecc00
+#define EMIFS_CONFIG_REG        (volatile unsigned int *)(TCMIF_BASE + 0x0c)
+#define EMIFF_SDRAM_CONFIG      (volatile unsigned int *)(TCMIF_BASE + 0x20)
+
+#define ULPD_LOW_POWER_REQ		0x3
+
+#define DSP_IDLE_DELAY			10
+#define DSP_IDLE			0x0040
+#define DSP_ENABLE			0x0002
+#define SUFFICIENT_DSP_RESET_TIME	1000
+#define DEFAULT_MPUI_CONFIG		0x05cf
+#define ENABLE_XORCLK			0x2
+#define DSP_RESET			0x2000
+#define TC_IDLE_REQUEST			(0x0000000c)
+#define EMIFF_CONFIG_REG		EMIFF_SDRAM_CONFIG
+
+
+#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x
+#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x] 
+#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
+
+#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x
+#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] 
+#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+
+#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x
+#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x] 
+#define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
+
+enum arm_save_state {
+        ARM_SLEEP_SAVE_START = 0,
+	/*
+	 * 9 MPU control registers, all 16 bits
+	 */
+	ARM_SLEEP_SAVE_ARM_CKCTL, ARM_SLEEP_SAVE_ARM_IDLECT1, 
+	ARM_SLEEP_SAVE_ARM_IDLECT2, ARM_SLEEP_SAVE_ARM_EWUPCT, 
+	ARM_SLEEP_SAVE_ARM_RSTCT1, ARM_SLEEP_SAVE_ARM_RSTCT2,
+	ARM_SLEEP_SAVE_ARM_SYSST, 
+
+	ARM_SLEEP_SAVE_SIZE
+};
+
+enum ulpd_save_state {
+	ULDP_SLEEP_SAVE_START = 0,
+	ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG,
+	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG, 
+	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG,
+	ULPD_SLEEP_SAVE_SIZE
+};
+
+enum mpui_save_state {
+	/*
+	 * MPUI registers 32 bits
+	 */
+	MPUI_SLEEP_SAVE_MPUI_CTRL_REG, MPUI_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+	MPUI_SLEEP_SAVE_MPUI_DSP_API_CONFIG, MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG,
+	MPUI_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, MPUI_SLEEP_SAVE_EMIFS_CONFIG_REG,
+	MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2,
+
+	MPUI_SLEEP_SAVE_SIZE
+};
+
+
+#endif	/* ASSEMBLER */
+#endif 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/preem_latency.h linux-2.4.19/include/asm-arm/arch-omap1510/preem_latency.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/preem_latency.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/preem_latency.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,19 @@
+/*
+ * include/asm-arm/arch-omap1510/preem_latency.h
+ * timing support for preempt-stats patch
+ */
+
+#include "hardware.h"
+
+extern unsigned int read_mputimer1(void);
+
+#define readclock_init()
+#define readclock(x)		x = read_mputimer1()
+#define clock_to_usecs(x)	((x) / 6)
+
+#define PSR_F_BIT               0x40    /* FIQ unmask/mask (0/1) */
+#define PSR_I_BIT               0x80    /* IRQ unmask/mask (0/1) */
+#define INTERRUPTS_ENABLED(x)   (!(x & PSR_I_BIT))
+/* mputimer 1 runs @ 6Mhz  6 ticks = 1 microsecond */
+#define TICKS_PER_USEC		6
+
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/serial.h linux-2.4.19/include/asm-arm/arch-omap1510/serial.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/serial.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/serial.h	2003-01-15 12:37:20.000000000 +0200
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-arm/arch-omap1510/serial.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ * serial definitions
+ *
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+#include <asm/arch/hardware.h>
+#include <asm/irq.h>
+
+#define BASE_BAUD (12000000/16)
+
+#define RS_TABLE_SIZE	3
+
+#define	STD_COM_FLAGS	(ASYNC_SKIP_TEST)
+
+#define STD_SERIAL_PORT_DEFNS \
+	{	/* ttyS0: */					\
+		type:		PORT_OMAP,			\
+		xmit_fifo_size:	64,				\
+		baud_base:	BASE_BAUD,			\
+		iomem_base:	(u8*)OMAP1510_UART1_BASE,	\
+		iomem_reg_shift:	2,			\
+		io_type:	SERIAL_IO_MEM,			\
+		irq:		INT_UART1,			\
+		flags:		STD_COM_FLAGS			\
+	},							\
+	{	/* ttyS1: */					\
+		 type:		PORT_OMAP,			\
+		xmit_fifo_size:	64,				\
+		baud_base:	BASE_BAUD,			\
+		iomem_base:	(u8*)OMAP1510_UART2_BASE,	\
+		iomem_reg_shift:	2, 			\
+		io_type:	SERIAL_IO_MEM,			\
+		irq:		INT_UART2,			\
+		flags:		STD_COM_FLAGS			\
+	},							\
+	{	/* ttyS2: */					\
+		type:		PORT_OMAP,			\
+		xmit_fifo_size:	64,				\
+		baud_base:	BASE_BAUD,			\
+		iomem_base:	(u8*)OMAP1510_UART3_BASE,	\
+		iomem_reg_shift:	2,			\
+		io_type:	SERIAL_IO_MEM,			\
+		irq:		INT_UART3,			\
+		flags:		STD_COM_FLAGS			\
+	}
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/sizes.h linux-2.4.19/include/asm-arm/arch-omap1510/sizes.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/sizes.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/sizes.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,52 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h                       1
+
+/* handy sizes */
+#define SZ_1K                           0x00000400
+#define SZ_4K                           0x00001000
+#define SZ_8K                           0x00002000
+#define SZ_16K                          0x00004000
+#define SZ_64K                          0x00010000
+#define SZ_128K                         0x00020000
+#define SZ_256K                         0x00040000
+#define SZ_512K                         0x00080000
+
+#define SZ_1M                           0x00100000
+#define SZ_2M                           0x00200000
+#define SZ_4M                           0x00400000
+#define SZ_8M                           0x00800000
+#define SZ_16M                          0x01000000
+#define SZ_32M                          0x02000000
+#define SZ_64M                          0x04000000
+#define SZ_128M                         0x08000000
+#define SZ_256M                         0x10000000
+#define SZ_512M                         0x20000000
+
+#define SZ_1G                           0x40000000
+#define SZ_2G                           0x80000000
+
+#endif
+
+/*         END */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/system.h linux-2.4.19/include/asm-arm/arch-omap1510/system.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/system.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/system.h	2003-01-15 12:39:12.000000000 +0200
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-ti925/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2000 RidgeRun, Inc. (http://www.ridgerun.com)
+ *                Greg Lonnon (glonnon@ridgerun.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <asm/arch/hardware.h>
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void arch_idle(void)
+{
+	if (!hlt_counter) {
+		int flags;
+		local_irq_save(flags);
+		if (!current->need_resched)
+			// FIXME: Check the arguments in the MV code
+			//cpu_do_idle(0);
+			cpu_do_idle();
+		local_irq_restore(flags);
+	}
+}
+
+static void arch_reset(char mode)
+{
+	*(volatile u16 *)(ARM_RSTCT1) = 1;
+}
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/time.h linux-2.4.19/include/asm-arm/arch-omap1510/time.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/time.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/time.h	2003-01-15 12:39:15.000000000 +0200
@@ -0,0 +1,183 @@
+/*
+ * linux/include/asm-arm/arch-ti925/time.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ * 32kHz timer definition
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#if !defined(__ASM_ARCH_OMAP1510_TIME_H)
+#define __ASM_ARCH_OMAP1510_TIME_H
+
+#include <linux/config.h>
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/irq.h>
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#  define DBG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ## args)
+#  define ENTRY() DBG(":entry\n")
+#else
+#  define DBG(fmt, args...)
+#  define ENTRY()
+#endif
+
+#if 1 // debug start
+
+inline unsigned long  timer_read(int reg) {
+        unsigned long val;
+        val = (inw(IO_ADDRESS((reg) + OMAP1510_32kHz_TIMER_BASE)));
+        DBG("TR: r:%d v:%x\n",reg,val);
+        return val;
+}
+inline void timer_write(int reg,int val) {
+        DBG("TW: r:%d v:%x\n",reg,val);
+        outw( (val), (IO_ADDRESS( (reg) + OMAP1510_32kHz_TIMER_BASE)));
+}
+
+// Timer Registers
+#define TIMER_CR     0x08
+#define TIMER_TVR    0x00
+#define TIMER_TCR    0x04
+
+// Timer Control Register definition
+#define TIMER_TSS    (1<<0)
+#define TIMER_TRB    (1<<1)
+#define TIMER_INT    (1<<2)
+#define TIMER_ARL    (1<<3)
+
+/*
+ * How long is the timer interval? 100 HZ, right...
+ * IRQ rate = (TVR + 1) / 32768 seconds 
+ * TVR = 32768 * IRQ_RATE -1
+ * IRQ_RATE =  1/100
+ * TVR = 326
+ */
+#define TIMER_PERIOD 326 
+//#define TIMER_PERIOD 0x7ff
+
+
+/*
+ * IRQ handler for the timer
+ */
+static inline void start_timer(void) {
+//	timer_write(TIMER_CR,TIMER_TSS | TIMER_TRB | TIMER_INT); // start
+	timer_write(TIMER_CR,TIMER_TSS | TIMER_TRB | TIMER_INT | TIMER_ARL); // start
+}
+
+static void omap1510_32kHz_timer_interrupt(int irq, 
+        void *dev_id, 
+        struct pt_regs *regs)
+{
+        ENTRY();
+	do_leds();
+	do_timer(regs);
+	do_profile(regs);
+
+#ifdef FPGA_HACK
+
+        // True evil: if ethernet is up and running check and make sure its
+        // bit is enabled in the FPGA interrupt mask register. If not, enable
+        // it. This is a workaround for the mysterious cases where someone or
+        // something is clearing this bit and bringing down our networking.
+        // We check if ethernet is up by testing the reset bit in the FPGA.
+
+        if (! (inb(OMAP1510P1_FPGA_RST) & 1)) {
+                unmask_irq(INT_ETHER);
+        }
+
+#endif
+//        start_timer();
+}
+
+extern __inline__ void setup_timer(void)
+{
+        // since we don't call request_irq, we must init the structure
+        ENTRY();
+        timer_irq.handler = omap1510_32kHz_timer_interrupt;
+	timer_irq.flags = SA_INTERRUPT;
+	timer_write(TIMER_CR, 0x0);
+        timer_write(TIMER_TVR,TIMER_PERIOD);
+	setup_arm_irq(INT_OS_32kHz_TIMER, &timer_irq);
+        start_timer();
+}
+#endif // REVISIT
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+#if 0
+#define CNTL_TIMER 0x0
+#define LOAD_TIM   0x4
+#define READ_TMI   0x8
+
+//  CNTL_TIMER register bits
+#define SOFT (1<<7)
+#define FREE (1<<6)
+#define CLOCK_ENABLE (1<<5)
+#define PTV_MASK 0x7
+#define PTR_SHIFT (1<<2)
+#define AR (1<<1)
+#define ST (1<<0)
+
+// After programming PTV with 0, the count is 12MHz.  For 
+// a clock rate of 100Hz:  100Hz * X = 12MHz 
+//                         X = 12MHz/ 100Hz = 1200
+#define TIMER_VALUE (12000000/100) 
+
+static inline void start_timer(void) {
+        outl(CLOCK_ENABLE | AR | ST, OMAP1510_TIMER1_BASE + CNTL_TIMER);
+}
+
+static void omap1510_timer1_interrupt(int irq, void *dev_id,
+                                     struct pt_regs *regs) {
+
+        ENTRY();
+	do_leds();
+	do_timer(regs);
+	do_profile(regs);
+        start_timer();
+}
+
+extern __inline__ void setup_timer(void) {
+        ENTRY();
+        timer_irq.handler = omap1510_timer1_interrupt;
+	timer_irq.flags = SA_INTERRUPT;
+
+
+
+	outl(TIMER_VALUE,OMAP1510_TIMER1_BASE + LOAD_TIM); 
+	setup_arm_irq(INT_TIMER1, &timer_irq);
+        start_timer();  
+}
+#endif
+
+#endif
+/* ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/timer.h linux-2.4.19/include/asm-arm/arch-omap1510/timer.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/timer.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/timer.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,70 @@
+/******************************************************************************
+ NAME                                                                          
+        timer.h -- kernal API for the timer driver
+ DESCRIPTION                                                                   
+        Interface to a minimal, basic, archictecture-agnostic kernel timer 
+        library.
+ AUTHOR                                                                        
+        gmcnutt <gmcnutt@ridgerun.com>
+ COPYRIGHT                                                                     
+        (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)                      
+
+ ----------------------------------------------------------------------------
+  This program is free software; you can redistribute  it and/or modify it
+  under  the terms of  the GNU General  Public License as published by the
+  Free Software Foundation;  either version 2 of the  License, or (at your
+  option) any later version.
+ 
+  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ 
+  You should have received a copy of the  GNU General Public License along
+  with this program; if not, write  to the Free Software Foundation, Inc.,
+  675 Mass Ave, Cambridge, MA 02139, USA.
+ ----------------------------------------------------------------------------
+ *****************************************************************************/
+
+#ifndef dsplinux_timer_h
+#define dsplinux_timer_h
+
+#ifndef __KERNEL__
+#error This is a kernel API
+#endif
+
+#define TIMER_UNIT_MIN timer_unit_ns
+#define TIMER_UNIT_MAX timer_unit_Ms
+
+#define TIMERF_PERIODIC 0x1
+#define TIMERF_ONESHOT  0x2
+#define TIMERF_INT      0x4
+#define TIMERF_RST      0x8
+
+typedef enum { timer_mode_oneshot = 0, timer_mode_periodic } timer_mode_t;
+typedef enum { timer_action_interrupt = 0, timer_action_reset } timer_action_t;
+
+typedef void (*timer_cb_t)(int timer, void *data);
+
+extern int timer_get_num_timers(void);
+extern int timer_get_features(int timer, int *features);
+extern int timer_start(int timer);
+extern int timer_stop(int timer);
+extern int timer_is_running(int timer);
+extern int timer_set_mode(int timer, timer_mode_t mode);
+extern int timer_get_mode(int timer, timer_mode_t *mode);
+extern int timer_set_action(int timer, timer_action_t action);
+extern int timer_get_action(int timer, timer_action_t *action);
+extern int timer_set_period(int timer, unsigned long usecs);
+extern int timer_get_period(int timer, unsigned long *usecs);
+extern int timer_get_time_remaining(int timer, unsigned long *usecs);
+extern int timer_register_cb(int timer, timer_cb_t cb, void *data);
+extern int timer_unregister_cb(int timer, void *data);
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/timex.h linux-2.4.19/include/asm-arm/arch-omap1510/timex.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/timex.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/timex.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-arm/arch-ti925/timex.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   a place holder
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/vmalloc.h linux-2.4.19/include/asm-arm/arch-omap1510/vmalloc.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/arch-omap1510/vmalloc.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/arch-omap1510/vmalloc.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/pm.h linux-2.4.19/include/asm-arm/pm.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/pm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-2.4.19/include/asm-arm/pm.h	2003-01-09 19:49:04.000000000 +0200
@@ -0,0 +1,45 @@
+/*
+ * FILE NAME include/asm/pm.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: MontaVista Software, Inc.
+ *         support@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * List of global OMAP registers to preserve.  All registers are 16 bits
+ * and must be accessed with 16 read/writes.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+#ifndef __ASM_PM_H
+#define __ASM_PM_H  
+
+#ifdef __KERNEL__
+#include <asm/arch/pm.h>
+#endif  /* __KERNEL__ */
+
+#endif
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/asm-arm/proc-fns.h linux-2.4.19/include/asm-arm/proc-fns.h
--- ../linux-2.4.19-rmk4-vanilla/include/asm-arm/proc-fns.h	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/include/asm-arm/proc-fns.h	2003-01-15 12:36:51.000000000 +0200
@@ -68,6 +68,14 @@
 #   define CPU_NAME arm922
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM925T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME arm925
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM926T
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/linux/apm_bios.h linux-2.4.19/include/linux/apm_bios.h
--- ../linux-2.4.19-rmk4-vanilla/include/linux/apm_bios.h	2001-08-14 02:39:28.000000000 +0300
+++ linux-2.4.19/include/linux/apm_bios.h	2003-01-15 10:25:36.000000000 +0200
@@ -214,5 +214,6 @@
 
 #define APM_IOC_STANDBY		_IO('A', 1)
 #define APM_IOC_SUSPEND		_IO('A', 2)
+#define APM_IOC_SET_WAKEUP	_IO('A', 3)
 
 #endif	/* LINUX_APM_H */
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/linux/pm.h linux-2.4.19/include/linux/pm.h
--- ../linux-2.4.19-rmk4-vanilla/include/linux/pm.h	2002-08-03 03:39:45.000000000 +0300
+++ linux-2.4.19/include/linux/pm.h	2003-01-15 12:37:09.000000000 +0200
@@ -62,6 +62,7 @@
 	PM_SCSI_DEV,	    /* SCSI device */
 	PM_ISA_DEV,	    /* ISA device */
 	PM_MTD_DEV,	    /* Memory Technology Device */
+	PM_SYS_ARCH_SPECIFIC,        /* arch-specific */
 };
 
 typedef int pm_dev_t;
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/linux/serial_core.h linux-2.4.19/include/linux/serial_core.h
--- ../linux-2.4.19-rmk4-vanilla/include/linux/serial_core.h	2002-12-30 10:53:21.000000000 +0200
+++ linux-2.4.19/include/linux/serial_core.h	2003-01-09 19:49:04.000000000 +0200
@@ -37,7 +37,8 @@
 #define PORT_16654	11
 #define PORT_16850	12
 #define PORT_RSA	13
-#define PORT_MAX_8250	13	/* max port ID */
+#define PORT_OMAP	14
+#define PORT_MAX_8250	14	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/linux/serial.h linux-2.4.19/include/linux/serial.h
--- ../linux-2.4.19-rmk4-vanilla/include/linux/serial.h	2002-08-03 03:39:45.000000000 +0300
+++ linux-2.4.19/include/linux/serial.h	2003-01-15 12:37:09.000000000 +0200
@@ -75,7 +75,8 @@
 #define PORT_16654	11
 #define PORT_16850	12
 #define PORT_RSA	13	/* RSA-DV II/S card */
-#define PORT_MAX	13
+#define PORT_OMAP	14
+#define PORT_MAX	14
 
 #define SERIAL_IO_PORT	0
 #define SERIAL_IO_HUB6	1
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/include/linux/serial_reg.h linux-2.4.19/include/linux/serial_reg.h
--- ../linux-2.4.19-rmk4-vanilla/include/linux/serial_reg.h	2001-05-02 02:05:00.000000000 +0300
+++ linux-2.4.19/include/linux/serial_reg.h	2003-01-09 19:49:04.000000000 +0200
@@ -278,5 +278,17 @@
 #define SERIAL_RSA_BAUD_BASE (921600)
 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
 
+/*
+ * Extra serial register definitions for the internal UARTs 
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_TCR		0x06	/* transmission control register */
+#define UART_OMAP_TLR		0x07	/* trigger level register */
+#define UART_OMAP_MDR1		0x08	/* mode definition register */
+#define UART_OMAP_SCR		0x10	/* supplementary control register */
+#define UART_OMAP_OSC_12M_SEL	0x13	/* write 1 to select a 6.5 baud 
+					 * rate divisor to get 115200 baud 
+					 * from a 12MHz clock.
+					 */
 #endif /* _LINUX_SERIAL_REG_H */
 
diff -urN -I '\$Id: ' -I '\$Id\$ ' -I '\$Source: ' -I '\$Revision: ' -I '\$Date: ' -I '\$Log: ' -I '\$Header: ' -I ' \* Revision ' -I ' \*Revision ' -I ' \* Imported ' -I ' \*Imported ' -I ' \*\n' --exclude-from=/home/arm/dontdiff_tml_arm ../linux-2.4.19-rmk4-vanilla/Makefile linux-2.4.19/Makefile
--- ../linux-2.4.19-rmk4-vanilla/Makefile	2002-12-30 10:53:20.000000000 +0200
+++ linux-2.4.19/Makefile	2003-01-15 13:27:05.000000000 +0200
@@ -1,11 +1,12 @@
 VERSION = 2
 PATCHLEVEL = 4
 SUBLEVEL = 19
-EXTRAVERSION = -rmk4
+EXTRAVERSION = -rmk4-omap-1
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
 ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
+ARCH := arm
 KERNELPATH=kernel-$(shell echo $(KERNELRELEASE) | sed -e "s/-//g")
 
 CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
@@ -19,7 +20,7 @@
 HOSTCC  	= gcc
 HOSTCFLAGS	= -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
 
-CROSS_COMPILE 	=
+CROSS_COMPILE 	= arm-linux-
 
 #
 # Include the make variables (CC, etc...)
